optimization of pcb pdn design using enhanced vrm model
TRANSCRIPT
Optimization of PCB PDN design using enhanced
VRM model Guang Chen, Ahmed Abou-Alfotouh, Zhiwei Liu, Mostafa Shabban, Dan Oh
Altera Corporation
101 Innovation Drive, San Jose, CA 95134
Abstract— Decoupling for power rails that demand large current,
such as FPGA core, is difficult. The capacitors required for
derived solution requires excessive board area for placement and
raise system cost significantly. Switcher with high loop Band
Width helps reducing the decoupling needs with all the design
improvements. In this paper, we proposed a 3-stage behavioral
model for switcher to help PCB designer optimize PCB
decoupling design. The paper also covers some issues related to
switcher application, such as layout optimization for best noise
performance
Keywords-core power decoupling, SMPS DC-DC converter,
Switcher, Switcher model, power integrity, Switcher noise impact
I. INTRODUCTION
Modern integrated circuit (IC) requires large power consumption and needs a stable power supply rails. Proper decoupling network design to regulate AC noise is a must for ensure reliable IC operations. PCB decoupling becomes a great challenge for PCB designers. A naive implementation of PCB decoupling scheme can lead to an excessive number of decoupling capacitors and can even lead to worse PDN performance [1].
FPGA core is the most power hunger rail among all the FPGA power rails. Decoupling FPGA core is one of the most challenging tasks for PCB designer. Every new generation FPGA core design features a smaller process node, higher transistor count and faster clock speed. For example, the largest device in the latest generation Stratix V device family has 952KLEs and runs at the maximum clock speed up to 700MHz with 0.9V power supply. In comparison, the largest device in the first gen Stratix device family offers only 78K logic elements and runs at a maximum clock speed of 422MHz with 1.5V power supply. Due to increased power usage and tight system voltage margin, the target impedance Ztarget for core decoupling is reduced significantly and a large amount of PCB decoupling capacitors, especially bulk capacitors, are required to meet Ztarget. Table 1 compares the decoupling capacitors required for two designs based on the same core PDN impedance profile. Ztarget is reduced from 15mOhm in the first design to 3mOhm for the second design as power requirement changes. The number of bulk capacitors required increases from 5 to 80. These bulk capacitors occupy large board area, which makes layout work challenging and raises the BOM cost significantly.
Table 1. Comparison of decoupling capacitor requirements
Power requirements
Ztarget (mOhm)
Decoupling Caps Required
Case 1: 1.5V, 5A, 5% ripple
15 5x100uF, 2x2.2uF, 1x1uF,
1x0.47uF, 2x0.22uF, 5x0.1uF, 3x47nF
Case 2: 0.9V, 15A, 5% ripple
3 45x470uF, 35x330uF,
10x2.2uF, 27x1uF
Power supply voltage is delivered by on board voltage regulator module, i.e. VRM. For modern PCB board design, Switch Mode Power Supply (SMPS) DC-DC converters, i.e. switchers, are the most commonly used type of VRM. They are switching circuits that are powered by DC input source and covert input to stable DC voltage and current that load requires. The switchers are preferred because they are able to maintain high efficiency during all load conditions. As a comparison, the efficiency of a linear regulator is limited by the ratio of output power to the input power and is low in light load condition situation.
Figure 1. Switcher schematic and output
Figure 1 shows the simplified schematic of a switcher. It consists of two MOSFETs (Main_SW and Sync_SW), control block and Low-Pass LC filter network. The on/off of MOSFETs controls the current flow between power source and charging the MOSTFETs output duty cycle changes the output voltage value. The control block generates the Pulse Width Modulation (PWM) signal that controls on/off of the MOSFETs. The LC network filters out high frequency spikes
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on the output waveform and delivers low noise output to the load.
The output voltage regulation is achieved through feedback loop. The control block detects voltage difference at sense line from the preset voltage reference and adjusts the duty cycle of the control signal accordingly. The MOSFETs’ on/off duty cycle is changed following the change of control signal to reduce the difference.
The stability is a big concern for any system with feedback loop. Capacitors connected to the PDN network may cause instability of the switcher. However, it is suggested that the worst case noise created by step type current draw is minimized if the impedance profile of the network is flat [2]. Frequency domain Target Impedance Method (FDTIM) discussed in [1] is a commonly used frequency domain approach for deriving PCB decoupling network. Ztarget defined in FDTIM approach is a flat line in frequency domain. The stability is thus less a concern with carefully designed decoupling network generated following FDTIM approach.
The voltage change seen at sense line could come from two origins. It could be the result of switcher output drift. It can also be caused by the load transient due to FPGA core switching activity. The latter is generally considered as AC noise and regulated with PCB decoupling capacitors. Therefore, switcher helps reducing the needs for bulk capacitors at low frequency and contributes to the PDN decoupling. The ability of switcher in regulating voltage fluctuation diminishes as frequency increases due to limitation of the switcher feedback loop bandwidth.
With improvement of the design parameters, the switcher is able to regulate voltage deviation with higher slew rate during load transient. However, PCB designers are not able to take full advantage of the switcher improvement due to lack of suitable switcher model. Existing full circuit model or behavioral model of switcher is too complicated to be integrated into the existing decoupling design flow. In this paper, a lumped circuit switcher model is proposed based on switcher frequency domain response. The model extraction procedure is described in details. A switcher model is extracted and simulation suggests significant reduction in the number of bulk capacitors required using the switcher in large current draw scenario. The result is validated with lab experiment data. As shown in the given example, the new model enables PCB designer to capture the switcher contribution to PDN decoupling. Switcher PCB layout has impact on the switcher tracking capability. This paper also summarizes the layout recommendations for the best switcher performance.
II. SWITCHER FREQUENCY DOMAIN IMPEDANCE PROFILE
EXTRACTION AND BEHAVIORAL MODEL DEVELOPMENT
Figure 2 illustrates a typical PDN model. The impact of PCB board, package, die and package capacitors on PDN impedance are modeled with resistor, inductor and capacitor (R/L/C) elements. A proper linear behavior model is required to get accurate description of PDN profile.
Complete switcher module model provides good projection on contribution to transient noise reduction from switcher. But the model is not suitable for the needs of FDTIM based PCB decoupling design. Besides the complexity, the complete switcher module model has linearity issue. The frequency domain approach assumes the network is a linear time-invariant (LTI) system. MOSFETs of a switcher operate in switching mode in which power MOSFETs toggles between on and off state during normal operation. Therefore, a switcher is not a LTI system and the model cannot be used in frequency domain approach directly.
Figure 2. Effective range of decoupling approaches
The first step to generate the frequency domain behavior model of a VRM is to find out its frequency domain impedance profile. The commonly used frequency response analysis (AC sweep) requires that all the components in the network be in AC steady state. But MOSFETs of switcher operates in switching mode as explained above. As the result, AC sweep cannot be used for the purpose. The alternative is to extract equivalent impedance profile from transient simulation results.
To generate the equivalent frequency domain impedance profile of the switcher output, a sinusoidal current draw is applied to the output of the switcher model. The magnitude of the current draw equals the maximum output current of the switcher. The switcher impedance at the current draw frequency is defined as the output voltage deviation magnitude divided by the current draw magnitude. Frequency domain sweep is achieved by altering the frequency of the current draw through the interested frequency range.
Figure 3. Simulated switcher output noise
The output noise probed at switcher output consists of two types of noise, the static load noise and the transient load noise (Figure 3). The transient load noise is generated by the load
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current draw change due to device activities and it is the noise to be considered when designing PDN decoupling. For a switcher with proper LC filtering network, the system response to the dynamic current draw can be considered linear within the effective range of the switcher (1/10 of switcher switching frequency). The static load noise is generated as switcher try to deliver constant current required by device. The switcher MOSFETs are switched on and off by the PWM control signal at a constant frequency (Figure 4) and the noise generated has digital signal like waveform. The load change affects not the magnitude but the duty cycle of the output noise. The static load noise, therefore, is non-linear.
We assume that the transient load noise dominants so that the equivalent frequency domain impedance profile of the switcher network can be extracted. The static load noise contributes to DC output fluctuation. The DC output fluctuation has to be regulated below certain level per device performance requirement. The above linear system response assumption thus holds for typical switcher designs.
Figure 4. Measured static load noise
A new three-stage behavioral model (Figure 5) is proposed based on extracted impedance profile shown in Figure 6. The new model consists of three stages, two RL stages and a RLC stage connected in parallel. The two RL stages capture the parasitics from power path and ground path. The RLC stage represents the effects of the capacitances from LC filter network. The actual value for each element in the model is determined using curve fitting.
The extracted model is linear and simple comparing to the full scale switcher model. It can be easily integrated into the above PDN model for PCB decoupling design. Comparing to the generic RL model, the impedance profile of the new model has better match with the extracted impedance profile of switcher, which allows designer to take advantage of the improved switcher capability in noise reduction to reduce pessimism of decoupling as illustrated in following chapter. The new model, however, is not suitable for transient simulation since the model does not capture the nonlinear behavior portion of the switcher.
Figure 5. Proposed new 3-stage switcher model
Figure 6. Impedance profiles from extraction, new model and generaic model
III. DISCUSSIONS
A. Model Validation
To validate the accuracy of the model, an existing PCB decoupling design is analyzed. Figure 7 compares the impedance profile of the PCB portion looking from PCB pad based on generic R/L VRM model with that based on new switcher model. As suggested in the figure, PCB PDN impedance profile is still below Ztarget after reducing number of 330uF bulk capacitor used from 10 to 5.
Figure 7. Comparison of PCB impedance profile based on generic and new switcher model
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A PCB board is set up at lab to experimentally validate the simulation result. A mock up load that generates 10A /1us current draw is mounted on the board with bulk capacitors reduced by half and output noise due to the current draw is measured. The voltage deviation is 35mV, which is within 55mV voltage fluctuation target. The experiment result indicates that the pessimism within decoupling design can be further reduced with the help of new equivalent switcher model.
B. Decoupling Design Optimization with New SwitcherModel
The effectiveness of a PCB capacitor in reducing the PDN impedance diminishes as number of capacitors used increases. Therefore, a lot more PCB capacitors have to be used to achieve same amount of impedance reduction in high current consumption case comparing to low current consumption case. Figure 8 plots Ztarget and the number of capacitors needed to meet Ztarget as required current increases. For the decoupling design studied, additional 6 capacitors are needed when current increases from 5Amp to 10Amp. Additional 196 capacitors are needed when current increases from 30Amp to 35Amp.
Figure 6 suggests that the generic RL switcher model is pessimism at low frequency range. The VRM is able to regulate low frequency noise well within the effective range of VRM and the equivalent impedance of switcher is low in that range. The upper slope in the impedance profile is also pushed to higher frequency, indicating that the VRM is capable of regulating faster switching noise than that projected by generic model. VRM is in parallel with all PCB decoupling capacitors (Figure 2). The number of the bulk PCB capacitors required can be greatly reduced if the VRM can provide a low resistance path for low frequency decoupling.
The PCB decoupling design requires 80 bulk caps to achieve 3mOhm Ztarget based on generic RL switcher model as shown in the 2
nd case listed in Table 1. The decoupling
design is updated after plugging in the new switcher model. The PCB decoupling based on new switcher model requires only 48 bulk caps, which is 40% less than the original design (Table 2). Figure 9 compares the simulated PCB PDN impedance profile of both designs. Both impedance profiles meet 3mOhm Ztarget. The simulation results also indicate that the original decoupling design uses 32 more bulk capacitors because of the pessimism of the ESR value in the generic VRM model used.
Figure 8. Target impedance and number of capacitors required
Table 2. Comparison of decoupling capacitor designs
Decoupling design
Ztarget (mOhm)
Decoupling Caps Required
Generic VRM model
3 45x470uF, 35x330uF,
10x2.2uF, 27x1uF
New switcher model
3 48x470uF, 10x2.2uF, 27x1uF
Figure 9. Comparison of PCB impedance profile based on generic and new switcher model for Case 2 in Table 1
C. Layout optimization to improve switcher performance
The noise generated by MOSFET switching activities
consists of a large amount of high frequency components.
Switching output noise reduction relies on the LC filtering
network. Besides L and C value, the placement of the
components also has impact on the output ripple magnitude.
Capacitor filters out high frequency components of the output
noise by providing a low impedance path to ground for the
components. The capacitor is less effective for the purpose if
its parasitic inductance is high. The switching noise magnitude
increases as result. Figure 10 compares the noise waveforms
measured at switcher output with different ESL value for the
capacitor. As shown, the magnitude and shape of the noise can
have significant variation due to ESL variation of the switcher
module for a PDN with the same current draw profile and
PCB decoupling.
a. Output noise when cap ESL is low
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b. Output noise when cap ESL is high
Figure 10. Comparison of switcher noise with different cap ESL
The output noise has to be well regulated as higher noise
increases the equivalent impedance at low frequency and
switcher becomes less effective in reducing bulk decoupling
capacitors. The capacitor parasitic inductance can be greatly
reduced through layout optimization. Commonly used layout
optimization approaches include placing decoupling capacitors
close to switcher, selecting capacitor type with lower ESL,
optimizing PCB footprint for capacitors and etc. The
recommendations and guidelines regarding Altera switcher
layout optimization for improving switcher noise performance
can be found in [3] [4].
D. Future Work
As illustrated in the paper, the number of PCB decoupling
capacitors required increases dramatically when the system
current draw is large. This brings great challenges in board
design and placement. New switcher model is able to help
designer reducing the bulk capacitors required and eases the
difficulties in board design. The PDN tool [5] is a graphical
tool used with all Altera® FPGAs to help designer optimize
the board-level PDN. The new switcher model for Altera
switchers is developed and integrated to the coming PDN tool
release. This helps designer that uses Altera switchers reduce
the pessimism and optimize the derived decoupling design.
IV. SUMMARY
Modern switcher design is capable of regulating faster voltage fluctuation and reduces decoupling needs due to all the design improvement. But the decoupling design cannot take full advantage of it due to lack of accurate model.
The paper reports the details of a new procedure to extract the equivalent frequency domain impedance profile of a switcher from time domain transient simulation result. A new 3-stage behavioral model of switcher is proposed in this paper based on extracted impedance profile. The new model can be integrated into the existing PDN model easily. Simulation shows that bulk PCB capacitors required in existing design is reduced using the new model. The conclusion is also validated via lab measurement.
The effectiveness of VRM in reducing bulk decoupling capacitors depends on its ability in reducing low frequency ripple of output. The switcher output noise magnitude increases as the parasitic inductance of the capacitors in its LC filtering network increases and this makes switcher less helpful. Good PCB layout practices are required to maximize the decoupling benefits from switcher.
REFERENCES
[1] L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy,
“Power distribution system design methodology and capacitor
selection for modern CMOS technology,” IEEE Transactions on
Advanced Packaging, pp. 284-291, Aug. 1999.
[2] Istvan Novak. (2007). Emgerging Challenges of DC-DC converters.
International Engineering Consortium
[3] Altera application notes AN583: Designing Power Isolation Filters
with Ferrite Beads for Altera FPGAs
[4] Enpirion En23F0 power data sheet:
http://www.altera.com/literature/ds/EN23F0QI_07512.pdf
[5] Altera PDN tool: http://www.altera.com/technology/signal/power-
distribution-network/sgl-pdn.html
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