online. newsletters. magazine. resource guides. lead generation

2012

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Online. Newsletters. Magazine. Resource Guides. Lead Generation. Market Research. White Papers. Email Blasts.

Chip Design, www.chipdesignmag.com and Chip Design email newsletters reach over 100,000 design engineers and engineering managers working on advanced SoC designs.

Chip Design’s readers and www.chipdesignmag.com visitors are chip, programmable logic device and IP-related architects, designers, and testers.

The readership also includes software protocol-application engineers and technical program managers. These architect-design-test engineers and

managers are responsible for creating the latest generations of ASICs, structured ASIC, ASSPs , FPGAs, memory cores and SoC devices.

Circulation Breakdown by Purchasing Responsibility

94.7% 80.4% 69.9% 53.1% 55.8% 35.6%Specify/Authorize/

Influence the

purchase of

Design Automation

tools and software

Specify/Authorize/

Influence the

purchase of ASICs,

FPGAs and PLDs

Specify/Authorize/

Influence the

purchase of

Intellectual

Property

Specify/Authorize/

Influence the

purchase of Standard

ICs Services

Specify/Authorize/

Influence the purchase

of Test Equipment/

Development Tools

Influence, specify or authorize the purchasing at

companies with revenues of over

$500 million.

Engineering 53.4%

Executive and other Management 13.3%

Other (R&D etc.) 5.4%

Engineering Management 27.9%

AMD Broadcom Fujitsu Intel NXP Semiconductors

Analog Devices Chartered Semiconductor Hewlett-Packard LSI Logic Qualcomm

AppliedMicro Cisco IDT National Semiconductor ST Microelectronics

Atmel Freescale Infineon NVIDIA Texas Instruments

Powerful Purchasing Influence

Top 20 Subscribing Companies

Circulation

Average Monthly Visitors

on www.chipdesignmag.comMagazine

ReadershipEmail Newsletters

Readership

Page Views: 227,013

Visits: 40,502

Average Time on Site: 42:34

Chip Design Magazine is distributed to over

40,000 qualified design engineers and

engineering managers working on advanced

SoC designs

➲ Chip Designer is distributed to 32,011 subscribers

➲ IP Designer & Integrator is distributed to 28,214 subscribers

➲ FPGA & PLD E-Product Alert is distributed to 44,018 subscribers

➲ RF & Microwave Systems is distributed to 27,018 subscribers

53.4%

5.4%

13.3%

27.9%

System architect, design and test engineers and engineering managers working on advanced SoC designs—Chip Design readers—account for a

third of all design engineers. These key enablers influence the purchase of nearly 80% of the total EDA market—or about $4 billion.

Market Leader Sponsorship (limited to 2 sponsors)

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headlines, white paper headlines, viewpoint headlines, data sheet headlines run across

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lines, white paper headlines, viewpoint headlines, data sheet headlines will run across

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Chip Design Online Gateway Sponsorships Generate best ROI

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Website Marketing – Zero in on the Chip Design Community

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Dedicated Email BlastSend your own email blast to Chip Design subscriber lists

Market Research and Lead Generation ProgramThese programs enable sponsors to gain valuable market intelligence and generate leads with detailed demographics. Sponsor provides up to 15 questions. We provide a 4

White Paper Editorial Development

White Paper Lead Generation ProgramSubmit your White Papers in PDF format and generate leadsfrom the Chip Design market with these promos:

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email newsletters that are broadcast monthly

White Paper(s) for $2500.

Common pitfalls in PCI Express design PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors. It employs a protocol that allows devices to communicate simultaneously by implementing dual uni-directional paths between them. This protocol is layered – it has a transaction layer, data link layer, and physical layer – and this article highlights a number of error-prone areas on each of those layers based upon our experience of verifying such projects. An experienced PCI designer has knowledge of configuration space, configuration cycles, memory cycles, device number, bus number, base addresses, TAG, and split cycles. Most are also comfortable with transaction layer concepts and terminology. But in general terms, it is the newer concepts which need special attention and are more error-prone. Let us now consider the problems on each layer in turn.

Figure 1. PCI Express topology

Transaction layer

The transaction layer is the upper layer of the architecture. It primarily assembles and disassembles the transaction layer packets (TLPs) used to communicate transactions (i.e., read, write). It also manages the credit-based flow control for TLPs.

Every request packet requiring a response is implemented as a split transaction. The packet format supports different forms of addressing, depending on the transaction type. The transaction layer supports four address spaces: the three PCI address spaces (memory, I/O, and configuration) and the message space.

Misinterpretation of the RCB parameter

A memory read request can be completed with one or multiple completions, based on the request size and the Max_Payload_Size. The read completion boundary (RCB) parameter determines the naturally aligned address boundaries in which a read request may be serviced with multiple completions. At times, endpoint designs assume that they can send 64byte-aligned completions when the RCB bit is set to 0. As a consequence, completions are incorrectly sent out broken into chunks aligned to the 64byte boundary instead of the 128byte boundary. The receiver treats these as malformed.

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Market Research/Lead Generation Topics Include:

questions with detailed demographics

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$2,500 per program)

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Sponsor Fee: $5,000

Chip Designer e-Newsletter (Bi-monthly)

SoC digital and analog designers, system

-

tion engineers benefit from the latest news,

viewpoints and technical articles. Covers such

IP Designer – Integrator e-Newsletter(Monthly)

Intellectual Property (IP) design and integration

remains one of the hottest trends in the chip

industry. Coverage includes trends in analog-

digital, core-memory, design, verification, inte-

gration and qualification of IP in the SoC space.

OptionsExclusive Roadblock-- Limited to one Sponsor468x60 banner at top center position; side banner 125 x up to 728; up to three text ads; - $6,000/issue

Platinum Sponsor468x90 banner at top center position and first text ad - $2,500/issue

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Silver Sponsor Second from top 125x125 banner position and third text ad - $1,500/issue

The #1 Magazine for the Advanced IC Design Market

Chip Design covers all of the technical challenges and implementation options that engineers face in

SoC design and the semiconductor manufacturing process as it affects the design of SoCs

including FPGAs and other programmable devices.

Make sure you participate in the following 2012 Interoperability Guides:

Sponsor or participate in:

➡ RF & Microwave Systems Special Issue (May release)

➡ Semiconductor Manufacturing (June release)

Affiliate Sponsors:

www.chipdesignmag.com

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qualified engineers, embedded developers and chip designers make effective design and purchasing decisions all year long.

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Purchasing guides for the electronics industry

Platinum Sponsor:

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www.lowpowersystems.com

Gold Sponsors

Engineers’ Guide to Low Power Systems Design

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Microchip’s 500 kHz Synchronous Boost Regulator offers low power operation; low

start up and input voltages, and offers selectable shutdown states, and integrated

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NXP’s award-winning Cortex™-M0 microcontrollers are changing the way

engineers think about design.

The NPS63-M from Emerson is the latest in a growing portfolio of openframe, low

power standard products which include the NPS20-M and NPS40-M power supplies.

Gold Sponsors

Annual Industry GuideProducts and techniques to optimize the efficiency of low power electronic designs

Low Power Design Trends

Techniques and Considerations in Low-Power Embedded Development

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Engineers’ Guide to PCI Express Solutions

Annual Industry GuideSolutions for engineers and embedded developers using PCI Express technologies

Featured Products

LeCroy’s PCI Express® Protocol Analysis and Test Tools

From PLX Technology:ExpressLane™ PCI Express 3.0

Three Generations of Choices for Developers

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PCI-SIG Looks Ahead to Gen 4

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Debugging PCI Express 3.0

VersaLogic’s Mamba single boardcomputer (SBC) provides extremeperformance and high reliability

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Engineers’ Guide to Multicore & Virtualization

Annual Industry GuideLeading Hardware, Software and Tools used in multiprocessor systems

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The Enea Multicore Migration Platform (MMP) directly addresses the challenges

of multicore migration through a combination of technology, expertise and

training.

From B Labs: Codezero® Embedded Hypervisor is the most comprehensive

virtualization solution for ARM/Linux as a stack - a solution developed by ARM/

Linux kernel engineers.

Multicore Trends Follow Performance Demands

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Embedded Applications Move to Multicore

Multicore Opportunities and ChallengesFrom Cavium Networks Inc.: The OCTEON II CN68XX family of multi-core MIPS64

processors.

1786 18th StreetSan Francisco, CA 94107Tel: +1 415.255.0390Fax: +1 415.255.9214www.extensionmedia.com

About Extension Media

Extension Media is a publisher of busi-ness-to-business magazines, resource catalogs and web sites that address high-technology industry platforms and emerging technologies such as embed-ded systems, chip design, intellectual property, software and infrastructure, architectures and operating systems.

Advertising / MarketingKaren PoppPublisher, Sales [email protected]

Article / Abstract SubmissionJohn [email protected]

CONTACTS

Custom Research and Lead

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www.eecatalog.com/fpga

Engineers’ Guide to FPGA & CPLD Solutions

Annual Industry Guide Hardware and software for FPGA system and application engineers

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The Virtex®-6 FPGA Connectivity Kit is a high performance

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digitizing with signal processing on a PMC IO module.

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Dual-Architecture FPGAs Provide New Opportunities for Embedded Developers

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FPGA & CPLD Quarterly Update e-newsletter

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RF & Microwave Systems e-newsletter (Quarterly)Trends, viewpoints, news and tech-

nical articles for design engineers and

2012 Chip Design Editorial Calendar

Issue

Focus

Report/Insert Key Editorial Topics

Show

Distribution

Ad

Close

Materials

Deadline

Spring Foundry Ecosystem Programs

10

Summer Resource 14

24

Partner

Guide

Editorial Leadership

John Blyler, Editorial

Director

Ed Sperling, Consulting Editor

Mark LaPedus, Senior Editor

Cheryl Berglund Coupé, EECatalog.com Editor®

Jim Kobylecky, Managing Editor

Pallab Chatterjee, Regional Editor

Dave Bursky, Senior Editor,

Cheryl Ajluni, Contributing Editor

Ann Steffora Mutschler, Contributing Editor

Editorial Board

2012 contributed article placement is limited. Guarantee coverage of your product, solution and company by reserving a guaranteed editorial position.

Contact John Blyler for details ([email protected])

2012 Editorial Calendar Magazines, Special Issues, Webcasts, and Market Research &

Lead Generation Programs

Chip Design Market Research & Lead Generation Programs

Research Topic Description Schedule Order Deadline

2012 Special Issues

Issue Key Editorial Topics

Show

Distribution

Ad

Close

Materials

Deadline

RF &

Symposium

Semiconductor June 22

2012 Editorial Calendar Newsletters and Resource Catalogs

Chip Design Email Newsletter Editorial Calendar

IP Designer & Integrator newsletter

Issue Feature Topic Ad Close Materials

January

June Jun 11


Sept 14

Chip Designer newsletter


January Jan 9 Jan 10

Jan 20 Jan 24

June Jun 1

Jun 19


Sep 11

Sep 21

1786 18th StreetSan Francisco, CA 94107Tel: +1 415.255.0390Fax: +1 415.255.9214www.extensionmedia.com

About Extension Media

Extension Media is a publisher of busi-ness-to-business magazines, resource catalogs and web sites that address high-technology industry platforms and emerging technologies such as embed-ded systems, chip design, intellectual property, software and infrastructure, architectures and operating systems.

Advertising / MarketingKaren PoppPublisher, Sales [email protected]

Article / Abstract SubmissionJohn [email protected]

Marketing & Editorial Contacts

2012 Resource Guide Editorial Calendar

Market Focus Pub Date Formats

Space

Deadline

Materials

Deadline Targeted Reach Bonus Distribution

Low Power System Design (including Energy Harvesting)

Multicore and VirtualizationTechnologies

Engineers’ Guide to Sensors and MEMS Design

Chip Design Resource Catalog June

PCI Express

FPGA and PLD Solutions

Chip Designer newsletter



Issue Ad Close Materials

Q1

Q2


Q4

FPGA & CPLD Quarterly Update Newsletter



Q1

Q2


Q4

RF & Microwave Systems

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