LOW POWER AND OPTIMAL DELAY MULTI THRESHOLD VOLTAGE LEVEL CONVERTERS

Abstract: Minimizing power consumption without

compromising speed in any integrated circuit (IC) is a challenge. Employing multiple supply voltages (multi-VdJJ is an effective technique to achieve this. In order to minimize the power dissipation in an integrated circuit, voltage level converter circuits are required. There are two novel multi-threshold voltage (multi-V,h) based level converters are proposed. When these novel level converters are applied in an integrated circuit and compared with the previous level converter which are of feed back based circuit. The power dissipation is decreased in this approach up to 47% and the Delay is optimized by 50% with multi threshold based level converter in a 0.18- pm technology. Index: multi-threshold, level converters, power dissipation

I. Introduction Power dissipation reduction in an

integrated circuit (ICs) is the most demanding issue for present chip-design. When a low voltage level signal directly drives a gate that is connected to a higher supply voltage, the pull-up network of the receiver cannot be fully turned off A receiver driven by a low voltage level signal therefore produces static dc current. In order to suppress this dc current, specialized voltage level converter circuits are employed between a low voltage driver and a full voltage level receiver. The main cause for static power dissipation is due to low level signal the voltage level converter circuits are inserted in critical region of integrated circuit to converter the low level signal to high level signal which is the main cause for power dissipation, previously level converters are of feed back based which rely on some feed back circuit for controlling the operation of pull up network transistor to avoid power dissipation within the level converter but these feedback based level converters have many disadvantages like circuit has slow response due to feed back circuit it also suffers form short circuit current and trapper inverters are required to drive the circuit at very low voltage this further increases the power consumptions, to over avoid these the novel multi­V th based level converters are proposed.

II. Implementation (a)Feedback-Based Level Converters:

The feedback-based level converters rely on some form of feedback circuitry for controlling the operation of the pull-up network transistors in order to avoid static dc current within the level converter. In feedback-based voltage level converter circuits, the pull-up transistors are not

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directly driven by the low voltage level signal provided by the driver. The operation of the pull-up transistors is controlled by an internal feedback mechanism isolated from the low voltage swing input signal, thereby avoiding the formation of static dc current paths within the circuit[l]. (a.i) Feedback Level converter:

VDDL

oI

Input

Node3

Node 1

III � 112

Figure 1: Feedback level converter

VDDH

The feedback-based level converter is shown in Figure 1: transistor Ml and M2 experience a low gate overdrive voltage (VDDL-VTH) during the operation of the circuit. Transistor Ml and M2 need to be sized larger to produce more current as compared to the transistor M 3 and M4 , respectively. When the input is at 0 V is turned off Nodel is charged to VDDL.Ml is turned on. Node 3 is discharged to 0 V turning M4 on. Node2 is charged to turning M3 off. The output is pulled down to 0 V. When the input transitions to VDDL, M2 is turned on. Nodel is discharged, turning Ml off. Node2 is discharged, turning M30n. Node3 is charged up to VDDH turning M4 off. The output transitions to VDDH. A feedback loop, isolated from the input, controls the operation of M3 and � during both transitions of the output.

Due to the transitory contention between the pull-up and the pull-down networks and the large size of the NMOS transistors (Ml and M2), however, Feedback level converter dissipates significant short-circuit and dynamic switching power. To maintain functionality with the lower values of VDDL, the sizes of Ml and M2 need to be further increased in order compensate for the gate overdrive degradation. The load seen by the previous stage is therefore increased, thereby further degrading the speed and increasing the power consumption. Tapered buffers are required to drive Ml and M2 at very low voltages. These tapered buffers further increase the power consumption of feedback level converter.

(b) Multi-Vth level converters:The Multi-Vth level converters employ a multi-CMOS technology

in order to eliminate the static dc current. The high threshold voltage pull-up transistors in this level converter are directly driven by the low level signals without producing a static dc current problem.

(b.i) Multi-Vth Level converters (MLC1):

----(vDDH

VDDL

Node1

VDDH

Input Output

Figure 3: Multi-Vth Level converter (MLCI)

The level converter is shown in Figure 3 Multi Vth level converter is composed of two cascaded inverters with dual- transistors. The threshold voltage of M2(V TH-M2) is more negative (higher IVthl) for avoiding static dc current in the first inverter when the input is at VDDL.IVth-M2 I is required to be higher than VDDH-VDDL for eliminating the static dc current. The Multi V th level converter operates as follow input is at 0 V, M2 is turned on.MI is cutoff.Nodel is pulled up to VDDH. The output is discharged to 0 V. When the input transitions to VDDL. MI is turned on. M2 is turned off since V GS, M2> V TH, M2. Node I is discharged to 0 V. The output is charged to VDDH[I].

(b.ii) Multi-Vth Level converters (MLC,):

Node 1-4

VDDH

VDDL

JL! Input Output

Figure 4: Multi-Vth Level converter (MLC2)

The level converter is shown in Figure 3 Multi-V th level converter is composed of two cascaded inverters with dual- transistors. In this level converter when the input is at 0 V, Node 1 is pulled high to VDDL turning M2 off .The output node is discharged to 0 V through the pass transistor MI. When the input transitions to VDDL,

the output node is initially charged to VDDH-Vthn-MI­Vthn-M3 and VDDL-Vthn-Mlthrough Ml.

Multi-Vth level converter has fewer transistors as compared feedback level converters. Furthermore, the elimination of the slow feedback circuitry reduces the short-circuit power of Multi­V th level converter as compared to feedback based level converter. No increase in the size of MI is required for achieving functionality at lower input voltages with the proposed circuit. Therefore, particularly for the very low values of VDDL, Multi­Vth level converter consumes lower power, occupies significantly smaller area, and imposes a much smaller load capacitance[l].

(c) Application of level converter in an integrated circuit:

CRITICAL PATH • - LEVEL CONVERTER

Figure 5.Circuit in which level converters are inserted into needed portions.

Circuit with shaded portion activates in V DDL In Figure 5 the integrated circuit has a

critical path from flip-flop A (FF A) to flip-flop B (FF B). Due to excessive slack in the gates or flip­flops off the critical path, the timing constraints could be met even if we partially use V DDL gates. However, the structure has a problem while implementing it in CMOS large scale integrated circuits. DC current flows at a V DDH gate due to the direct connection of a VDDL gate to a VDDH one. This becomes a problem in low-power CMOS circuits. A typical way to block the static current is to insert a level-converter circuit in between the circuit where there is direct connection for low voltage to higher voltage [2] [4]. The level converter converts the voltage level from VDDL to VDDH.

III. Results:

Figure 6.Layout for the circuit of an Ie in which feed back level converters are inserted into needed

portions. In Figure 6 Integrated circuits feed back level converters is inserted where is a transfer of low voltage level to high voltage level to avoid the static current dissipation, the input is given across the filp flop A and the output is take across filp flop B then power and delay is calculated for this integrated circuit.

Figure 7.Waveform for the circuit of an Ie in which feed back level converters are inserted into

needed portions.

Figure 7 shows the output waveforms of the above layout where the feedback level converters are inserted at critical region, the output is taken across filp flop B, power and delay is calculated.

Figure 8.Layout for the circuit of an Ie in which Multi V th level converters are inserted into needed

portions. In Figure 8 Integrated circuits Multi V th

level converters is inserted where is a transfer of low voltage level to high voltage level to avoid the static current dissipation, the input is given across the filp flop A and the output is take across filp flop B then power and delay is calculated for this integrated circuit.

Figure 9.Waveform for the circuit of an Ie in which Multi V th level converters are inserted into

needed portions. Figure 9 shows the output waveforms of

the above layout where the Multi V th level converters are inserted at critical region, the output is taken across filp flop B, power and delay is calculated.

(a) Comparison of power and delay at different values

Using different level converters in an integrated circuit the delay and power is calculated for different input voltage values.

Optimized Optimized Delay power

VDDL Delay Power (v) (ps) (�w)

Feedback 1.2 167 205.4 level 1 234 426.4

converter 0.8 454 620.68

Multi Vth 1.2 177 158.92 level 1 167 342.9

converter 0.8 234 546.2

Table: 1 average propagation delay (D), and average power

1 %

90i!

80i,

1;&

0%

Consumption (P) of the level converters

'"

\ --- - ,\ ....---

\\ �

t-- -A.. \

1.2 0.8

Vohage (v)

\l . I • I •

Figure 8. Plot for percentage of delay and power with respective voltage

In the Figure 8 the power is optimized to 47% and delay has reduced to 50% with the different input voltage levels. IV Conclusion:

The aim of this paper is to demonstrate the successful implementation of the "Multi Level Converter ". After a brief overview of the background information, design considerations with particular interest on the selection of voltage level converter, the operation of the multi threshold voltage level converter were discussed. This particularly made to decrease the power dissipation without affecting speed. It is found to be 47% and Delay is optimized by 50% Thus, the feedback based level converter is replacing with the multi threshold based level converter to decrease the

power dissipation and the speed is increased. This proves the circuit that having multi threshold and multi voltage level converters will reduce the power dissipation with out scarifying speed. References: [1] Sherif A. Tawfik and Volkan Kursun,"Low Power and High Speed Multi Threshold Voltage Interface Circuits," IEEE Trans. Very Large Scale Integr. (VLSI) syst., vol 17, No.5.May2009 [2] Stephan Henzler, Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. [3] V.Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design. New York: Wiley, 2006. [4] K. Usami et ai, "Automated low-power technique exploiting multiple supply voltages applied to a media processor," IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463-471, Mar. 1998. [5] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, MA:

Cambridge University Press, 1998. [6] S. H. Kulkarni and D. Sylvester, "High performance level conversion for dual VDD design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 926-936, Sep. 2004. [7] S. H. Kulkarni, A. N. Srivastava, and D.

Sylvester, "A new algorithm for improved VDD assignment in low power dual VDD systems," in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 2004, pp. 200-205. [8] F. Ishihara, F. Sheikh, and B. Nikolic', "Level conversion for dual supply systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2,pp. 185-195,Feb. 2004. [9] V. Kursun, R. M. Secareanu, and E. G. Friedman, "CMOS voltage interface circuit for low power systems," in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 3, pp. 667-670. [10] M. Hamada et aI., "A top-down low power

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