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ACM SIGDA Publications on CDROM
ICCAD 2001 November 4 - 8, 2001
San Jose, CA
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Table of Contents Front Matter Author Index Cover Page
IEEE/ACM DIGEST OFTECHNICAL PAPERS
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THE INSTITUTE OF ELECTRICAL ANDELECTRONICS ENGINEERS, INC.
ASSOCIATION FOR COMPUTING MACHINERY/SIGDA
THE IEEE COMPUTER SOCIETY DATC
Sponsored by:
IEEE Circuits &Systems Society
In cooperation with:
®
IEEE/ACM
INTERNATIONAL
CONFERENCE ON CAD--0011
DIGEST OF
TECHNICAL PAPERS
ICCAD proceedings 01 8/30/01 2:45 PM Page 1
FOREWORD
On behalf of the ICCAD 2001 Executive and Technical Program committees, I would like to welcomeyou to the International Conference on Computer-Aided Design which will take place November 4 - 8 atthe San Jose DoubleTree Hotel.
The main part of the ICCAD program consists of 30 technical paper sessions. The 92 papers which will bepresented in these sessions were selected from 301 paper submissions. The technical paper sessions arecomplemented by 5 embedded tutorials, each giving an overview on the most recent developments in anemerging or hot topic presented by leading experts in the field. This time, the embedded tutorials coverembedded software & systems, platform based design, RF and analog synthesis, power design issues, andEDA problems of MEMS design. A panel on Wednesday afternoon titled "Automatic Hierarchical Design:Fantasy or Reality?" will discuss the highly controversial matter of hierarchical versus flat design.
A core task of forward looking EDA research is the observation of long term trends in design technologies totimely identify upcoming challenges and opportunities for EDAtools and methodologies. As a novel approachto increase the awareness of the EDA community for such trends, ICCAD 2001 has invited key experts tointroduce and discuss materials, circuits, architectures, and design issues of nanotechnologies. The keynote,"Nanotechnology and the Information Age" by Thomas Theis, Director of Physical Sciences at IBM Research,will be followed by a panel: "Will Nanotechnology Change the Way We Design and Verify Systems?" onMonday evening, bringing together experts from different areas of this exciting research field.
This technical program has been organized by the Program Chair, Larry Pileggi, and by the Vice ProgramChair, Andreas Kuehlmann, with the support of the Program and the Executive Committees. Thursday, November 8, brings a new set of the very successful series of ICCAD full-day tutorials. They wereorganized by our tutorial chair, Hidetoshi Onodera, and will cover the topics 1) Low-Power EmbeddedSoftware: What, Why, and How? 2) Optimization Strategies for Physical Synthesis and Timing Closure 3)Signal Integrity (new edition of the best selling tutorial of ICCAD 2000) 4) Boolean Satisfiability.
I hope you will enjoy the conference and experience some of the enthusiasm and excitement which spursour research community to accept the ever increasing challenges of EDA in the deep submicron design age.
Rolf ErnstGeneral Chair
Larwrence T. PileggiTechnical Program Chair
PROGRAM CHAIRLawrence T. PileggiCarnegie Mellon Univ.Dept. of ECE5000 Forbes Ave.Pittsburgh, PA 15213(412) [email protected]
PROGRAM VICE CHAIRAndreas KuehlmannCadence Berkeley Labs.2001 Addison St., 3rd Fl.Berkeley, CA 94704-1103(510) [email protected]
PAST CHAIREllen M. SentovichCadence Berkeley Labs.2001 Addison St., 3rd Fl.Berkeley, CA 94704-1103(510) [email protected]
TUTORIAL CHAIRHidetoshi OnoderaKyoto Univ.Dept. of CCESakyo-kuKyoto 606-8501, Japan(81) [email protected]
EUROPEANREPRESENTATIVEFrancky CatthoorIMECKapeldreef 75, DESICS Div.Leuven, B-3001 Belgium(32) [email protected]
ASIAN REPRESENTATIVEKiyoung ChoiSeoul National Univ.School of EECSKwanak P.O. Box 34Seoul, 151-744 Korea(82) [email protected]
SIGDA REPRESENTATIVESoha HassounTufts Univ.Dept. of EE and CS161 College Ave.Medford, MA 02155(617) [email protected]
IEEE CS/DATCREPRESENTATIVEJohn DarringerIBM Corp. TJ Watson Research Ctr.P.O. Box 218Yorktown Heights, NY 10598(914) [email protected]
IEEE/CAS REPRESENTATIVEGeorges GielenKatholieke Univ.ESAT-MICASKasteelpark Arenberg10Leuven, B-3001 Belgium(32) [email protected]
CONFERENCE MANAGERKathy MacLennanMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) [email protected]
CONFERENCE COMMITTEEGENERAL CHAIRRolf ErnstTech. Univ. of BraunschweigHans-Sommer-Str 66Braunschweig, D38106 Germany(49) [email protected]
Miron AbramoviciAgere SystemsMurray Hill, [email protected]
Charles J. AlpertIBM Corp.Austin, [email protected]
Peter BeerelUniv. of Southern CaliforniaLos Angeles, [email protected]
Reinaldo BergamaschiIBM Corp. TJ Watson Research Ctr.Yorktown Heights, [email protected]
Armin BiereETH ZentrumZurich, [email protected]
Tim BurksMagma Design Automation, Inc.Cupertino, [email protected]
Andreas C. CangellarisUniv. of IllinoisUrbana, [email protected]
Jo Dale CarothersUniv. of ArizonaTuscon, [email protected]
Mustafa CelikMonterey Design Systems, Inc.Sunnyvale, [email protected]
Krishnendu ChakrabartyDuke Univ.Durham, [email protected]
Henry ChangCadence Design Systems, Inc.San Jose, [email protected]
Eli ChiproutIntel Corp.Chandler, [email protected]
Jason CongUniv. of CaliforniaLos Angeles, [email protected]
Olivier CoudertMonterey Design Systems, Inc.Sunnyvale, [email protected]
Florentin DartuIntel Corp.Hillsboro, [email protected]
Alper DemirCeLight, Inc.Iselin, [email protected]
Anirudh DevganIBM MicroelectronicsAustin, [email protected]
Sujit DeyUniv. of California at San DiegoLa Jolla, [email protected]
Antun DomicSynopsys, Inc.Mountain View, [email protected]
Nikil DuttUniv. of CaliforniaIrvine, [email protected]
Petru ElesLinköping Univ.Linköping, [email protected]
Amir FarrahiIBM Corp. TJ Watson Research Ctr.Yorktown Heights, [email protected]
Tong GaoMonterey Design Systems, Inc.Sunnyvale, [email protected]
Abhijit GhoshSynopsys, Inc.Mountain View, [email protected]
Patrick GroeneveldMagma Design Automation, Inc.Cupertino, [email protected]
Carlo GuardianiPDF Solutions Inc.San Jose, [email protected]
Aarti GuptaNEC USAPrinceton, [email protected]
Rajesh K. GuptaUniv. of CaliforniaIrvine, [email protected]
Ali HajimiriCALTECHPasadena, [email protected]
Alan J. HuUniv. of British ColumbiaVancouver, BC [email protected]
Xiaobo (Sharon) HuUniv. of Notre DameNotre Dame, [email protected]
Makoto IkedaUniv. of TokyoTokyo, [email protected]
Rajeev JayaramanXilinx, Inc.San Jose, [email protected]
Andrew B. KahngUniv. of California at San DiegoLa Jolla, [email protected]
Seiji KajiharaKyushu Institute of Tech.Iizuka, [email protected]
Matton KamonCoventor, Inc.Cambridge, [email protected]
ICCAD-2001 TECHNICAL PROGRAM COMMITTEE
Shinji KimuraNara Institute of Science and Tech.Nara, [email protected]
Cheng-Kok KohPurdue Univ.West Lafayette, [email protected]
Prabhakar KudvaIBM Corp. TJ Watson Research Ctr.Yorktown Heights, [email protected]
Yuji KukimotoSilicon Perspective Corp.Santa Clara, [email protected]
Koen LampaertMindspeed Tech., Inc.Newport Beach, [email protected]
Christian LandraultLIRMMMontpellier, [email protected]
Luciano LavagnoCadence Design Systems, Inc.Berkeley, [email protected]
Jay LawrenceCadence Design Systems, Inc.Chelmsford, [email protected]
John LillisUniv. of IllinoisChicago, [email protected]
David D. LingIBM Corp. TJ Watson Research Ctr.Yorktown Heights, [email protected]
Diana MarculescuCarnegie Mellon Univ.Pittsburgh, [email protected]
Radu MarculescuCarnegie Mellon Univ.Pittsburgh, [email protected]
Malgorzata Marek-SadowskaUniv. of CaliforniaSanta Barbara, [email protected]
Farid NajmUniv. of TorontoToronto, ON, [email protected]
Sridevan ParameswaranThe Univ. of New South WalesKensington, [email protected]
Irith PomeranzPurdue Univ.West Lafayette, [email protected]
Anand RaghunathanNEC USAPrinceton, [email protected]
Salil RajeMonterey Design Systems, Inc.Sunnyvale, [email protected]
Rob A. RutenbarCarnegie Mellon Univ.Pittsburgh, [email protected]
Kewal SalujaUniv. of WisconsinMadison, [email protected]
Sachin S. SapatnekarUniv. of MinnesotaMinneapolis, [email protected]
Majid SarrafzadehUniv. of CaliforniaLos Angeles, [email protected]
Hamid SavojMagma Design Automation, Inc.Cupertino, [email protected]
Patrick SchaumontIMECLeuven, [email protected]
Donatella SciutoPolitecnico di MilanoMilano, [email protected]
Carl SechenUniv. of WashingtonSeattle, [email protected]
Kenneth L. ShepardColumbia Univ.New York, [email protected]
Fabio SomenziUniv. of ColoradoBoulder, [email protected]
Mandayam SrivasRealChip CommunicationsSunnyvale, [email protected]
Dennis SylvesterUniv. of MichiganAnn Arbor, [email protected]
Lothar ThieleSwiss Federal Institute of Tech.Zurich, [email protected]
Frank VahidUniv. of CaliforniaRiverside, [email protected]
Diederik VerkestIMECLeuven, [email protected]
Tiziano VillaParades Labs.Rome, [email protected]
Bapiraju VinnakotaUniv. of MinnesotaMinneapolis, [email protected]
Kazutohsi WakabayashiNEC Corp.Kawasaki, [email protected]
Wayne WolfMediaworks Tech.Schaumberg, [email protected]
Yervant ZorianLogicVision Inc.San Jose, [email protected]
ICCAD-2001 TECHNICAL PROGRAM COMMITTEE
Miron Abramovici
Bhavna Agrawal
Christoph Albrecht
Charles J. Alpert
Krishnan Anandh
Jason Anderson
Cyrille Artho
Florence Azais
Ana Azevedo
Xiaoliang Bai
Felice Balarin
Peter Beerel
Jeff Bell
Reinaldo Bergamaschi
Michel Berkelaar
Subhrajit Bhattacharya
Armin Biere
Jesse Bingham
Partha Biswas
Manjit Borah
Pradip Bose
Elaheh Bozorgzadeh
Daniel Brand
Carlo Brandolese
Erik Brockmeyer
Premal Buch
Mihai Budiu
Tim Burks
Andreas C. Cangellaris
Yu Cao
Jo Dale Carothers
Giorgio Casinovi
Francky Catthoor
Mustafa Celik
Krishnendu Chakrabarty
Supratik Chakraborty
Rajit Chandrasekhar
Ram Chandrasekhar
Chih-Wei Chang
Chin-Chih Chang
Henry Chang
Shih-Chieh Chang
Samit Chaudhuri
Charlie Chung-Ping Chen
Deming Chen
Gang Chen
Kaiyu Chen
Li Chen
Eli Chiprout
Chris Chu
Maciej Ciesielski
Valentina Ciriani
Jason Cong
Radu Cornea
Jordi Cortadella
Olivier Coudert
Paolo d'Alberto
Koen Danckaert
Florentin Dartu
Aurobindo Dasgupta
Keshav Datta
Arlindo de Oliveira
Alper Demir
Denis Deschacht
Anirudh Devgan
Suijit Dey
Marco Di Natale
Antun Domic
Frederic Doucet
Tony Drumm
Nikil Dutt
Petru Eles
Abe Elfadel
Roger Embree
Amir H. Farrahi
Fabrizio Ferrandi
William Fornaciari
Dinesh Gaitonde
Malay Ganai
Tong Gao
Piyush Garg
Grigor Gasparyan
Werner Geurts
Vasu Ghanti
Abhijit Ghosh
Paolo Giusto
Eugene Goldberg
Evguenii Goldberg
Gert Goossens
Eric Grimme
Patrick Groeneveld
Peter Grun
Carlo Guardiani
David Guillou
Aarti Gupta
Rajesh Gupta
Satrajit Gupta
Sumit Gupta
Yajun Ha
ICCAD-2001 REVIEWERS
Ali Hajimiri
Ashok Halambi
Joerg Henkel
Stefaan Himpe
Emerson Hsiao
Ming-Fu (Emerson) Hsiao
Harry Hsieh
Alan J. Hu
Bo Hu
Sharon Hu
Hao-Ming Huang
Xuejue Huang
Ed Huijbregts
Yean-Yow Hwang
Makoto Ikeda
Ilya Issenin
Vikram Iyengar
Anoop Iyer
Hans Jacobson
Geert Jannsen
Rajeev Jayaraman
Ahmed Jerraya
Seiji Kajihara
Timothy Kam
Hirokazu Kami
Mattan Kamon
Srirang K. Karandikar
Ryan Kastner
Andrew B. Khang
Shinji Kimura
Desmond Kirkpatrick
David Knol
Cheng-Kok Koh
Tianming Kong
Aneesh Koorapaty
Victor Kravets
Alexei Kudriavtsev
Prabhakar Kudva
Yuji Kukimoto
Wolfgang Kunz
Gauthier Lafruit
Kanishka Lahiri
Marcello Lajolo
Koen Lampaert
Christian Landrault
Dirk Lanneer
Luciano Lavagno
Jay Lawrence
Mihai Lazarescu
Haris Lekastas
Archie Li
Steven Li
Yanbing Li
John Lillis
David D. Ling
Paul Lippens
Bao Liu
Hongchao Liu
Nikos Liveris
Ruibing Lu
Yuan Lu
Patrick H. Madden
Mahesh Mamidipaka
Soumendra Mandal
Ion Mandoiu
Leonardo Mangeruca
Diana Marculescu
Radu Marculescu
Malgorzata Marek-Sadowska
Igor L. Markov
Joas Marques-Silva
Grant Martin
Theodore Masceaux
Mohiuddin Mazumder
Bingfeng Mei
Noel Menezes
Jean Yves Mignolet
Shin-ichi Minato
Prabhat Mishra
Sundararajarao Mohan
Janett Mohnke
Mohamed Abdel Moneum
Akira Mukaiyama
Arindam Mukherjee
Rajeev Murgai
Sudip Nag
Farid Najm
Jagannathan Narasimhan
Amit Narayan
Tuyen Nguyen
Dan Nicolaescu
Pascal Nouet
Steve Nowick
Seda Ogrenci
Zhigang (David) Pan
Phiroze Parakh
Sridevan Parameswaran
Youngchul Park
Robert Pasko
ICCAD-2001 REVIEWERS
Priyadarsan Patra
Christiano Pereira
Irith Pomeranz
Gang Quan
Anand Raghunathan
Vijay Raghunathan
Salil Raje
Kavita Ravi
Srivaths Ravi
Lakshmi Reddy
Leonardo Reyneri
Michael Riepe
Gordon Roberts
Michail Romesis
Albert Ruehli
Rob A. Rutenbar
Ali Sadigh
Fabio Salice
Kewel Saluja
Sachin Sapatnekar
Majid Sarrafzadeh
Peter Saviz
Nick Savoiu
Hamid Savoj
Patrick Schaumont
Tobias Schuele
Viktor Schuppan
Donatella Sciuto
Carl Sechen
Ellen M. Sentovich
Jeegar Shah
Rupesh S. Shelar
Kenneth Shepard
Aviral Shrivastava
Sandeep K. Shukla
Cristina Silvano
Sunder Silvaprakasam
Amit Singh
Raminderpal Singh
Subarnarekha Sinha
Vivek Sinha
Victor Slonim
Fabio Somenzi
P. V. Srinivas
Srikanth Srinivasan
Mandayam Srivas
Ankur Srivatsava
Richard Stahl
Guenter Stenz
Ken Stevens
Leon Stok
Andrew Sullivan
Ramnath Sundararaman
Dennis Sylvester
Osamu Takahashi
Wataru Takahashi
Takashi Takenaka
Weiyu Tang
Feroze Taraporevala
Lothar Thiele
Minoru Tomobe
Louise Trevillyan
Albert Chung-Wen Tsao
Frank Vahid
Arnout Van De Capelle
Liesbet Van Der Perre
Koen Van Eijk
Geert Vanmeerbeeck
Miroslav Velev
Diederik Verkest
Frederik Vermeulen
Tiziano Villa
Bapi Vinnakota
Chandramouli Visweswariah
Kazutoshi Wakabayashi
Yosinori Watanabe
Hua Wen
Jacob White
Wayne Wolf
Chun Wong
Chang Wu
Tong Xiao
Shigeru Yamashita
Peng Yang
Xioajian Yang
David Yeh
Nina Yevtushenko
Tak Young
Qingjian Yu
Xin Yuan
Vittorio Zaccaria
Alex Zelikovsky
Yumin Zhang
Yi Zhao
Guoan Zhong
Yunshan Zhu
Yervant Zorian
ICCAD-2001 REVIEWERS
Thomas N. TheisDirector, Physical Sciences
IBM Corp. TJ Watson Research Ctr.Yorktown Heights, NY
NANOTECHNOLOGY AND THE INFORMATION AGE
Description: The history of information technology can be viewed as a quest to make "bits" smaller andsmaller. There is no obvious and hard physical limit to the minimum size of logical devices that processinformation or the marks that store information. Indeed, quantum physics is being recast as a theory ofinformation, and even a single atom can no longer be seen as the ultimate limit to the minimum size of abit. Yet the smallest logical devices being manufactured today contain billions of atoms, and the smallestmagnetic bits on commercial hard drives contain millions of atoms. Optimistically assuming continuedexponential improvement in our ability to pattern matter at ever-smaller dimensions, in perhaps 35 yearswe will have the capability to design and control the structure of an object on all length scales from theatomic to the macroscopic -- in other words, the beginnings of a mature nanotechnology. Progress alongthis road will depend not only on the continued extension of lithographic patterning techniques, but onincreasing use of processes of natural pattern formation, commonly referred to as self-assembly.Continued evolutionary progress in silicon microelectronics and magnetic storage seems assured for atleast another decade. Potential nanoscale successors, such as scanning-probe storage and carbon-nanotube electronics are under active investigation and suggest the possibility of continued exponentialprogress in information technology for decades to come.
Biography: Thomas Theis received a B.S. degree in Physics from Rensselaer Polytechnic Institute in1972, and M.S. and Ph.D. degrees from Brown University in 1974 and 1978, respectively. A portion of hisPh.D. research was done at the Technical University of Munich, where he completed a postdoctoral yearbefore joining IBM Research in 1979.
ICCAD-2001 KEYNOTE
TUTORIAL 1
ELECTRICAL-INTEGRITY DESIGN AND VERIFICATIONFOR DIGITAL AND MIXED-SIGNAL SYSTEMS-ON-A-CHIP
Speakers:
Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI
Kenneth L. Shepard - Columbia Univ., New York, NY
Background: With rising clock rates and scaling technology, it is becoming increasingly necessary to designand model a very complex on chip electrical environment dominated by wires. In this tutorial, we describe thelatest design and analysis approaches to ensuring the electrical integrity of today's systems-on-a-chip, tacklingemerging problems such as inductance, substrate coupling, and power-supply integrity. This tutorial is designedfor a target audience consisting of VLSI designers, managers, CAD tool developers, R&D engineers, andacademic researchers. The goal is to enable attendees to address key interconnect-centric issues including allaspects of signal integrity, inductive effects, and high-performance clock and power distribution.
Description: We begin by describing the design and analysis techniques for signal integrity in deepsubmicron designs. We introduce the overall design flow and fundamental theories and concepts ofRC/RLC interconnect analysis. We discuss the effects of capacitive and inductive coupling on line delayand noise. Design techniques to minimize capacitance and inductance effects are explored. We also focuson inductance estimation, extraction, and analysis.
The impact of environmental factors including variations in power supply voltage, temperature, andphysical factors due to process variations also affect the cycle time and design robustness. Large die sizesand higher operating frequencies, coupled with large on-die variations at reduced device geometries, callfor special consideration of this type of "noise".
We then consider power supply integrity analysis for systems-on-a-chip, including IR and Ldi/dt analysiswith full consideration of decoupling capacitance, switching activity, and package models. Powerdistribution methodologies will be discussed. Substrate coupling is also becoming an important new designand analysis concern for mixed-signal designs. Substrate effects will be considered in the context ofsubstrate noise analysis, latch-up and ESD analysis, and high-frequency interconnect analysis. In additionto analysis, we will also consider design techniques for limiting all of these coupling interactions.
We will survey various clock distribution approaches and the applicability for large SoC designs. We willcompare approaches such as H-tree, mesh, grid for a typical design in terms of requirements includinglocal/global skew, jitter, slew rates, power, buffer area, clock wiring resources, and shielding area. Wewill review the latest approaches for clock distribution networks including usage of de-skew units toreduce the clock skew.
Throughout the tutorial we will consider measurement techniques and structures for calibrating andcharacterizing the on-chip electrical environment with an emphasis on interconnect and substrate effects.This is important for technology characterization, yield analysis, and modeling validation.
TUTORIAL 2
BOOLEAN SATISFIABILITY SOLVING AND ITS APPLICATION IN EQUIVALENCE AND MODEL CHECKING
Speakers:
Joao Marques-Silva - Technical Univ. of Lisbon, Lisboa, PortugalPer Bjesse - Prover Tech., Portland, ORWolfgang Kunz - Univ. of Frankfurt, Frankfurt, Germany
Background: This tutorial covers the most recent work in Boolean Satisfiability algorithms and itsapplication in two key Design Automation applications: Equivalence Checking and Model Checking. Thetarget audience consists of circuit designers interested in a better understanding of SAT technology, CADengineers, and academic researchers working on SAT or on applications of SAT.
Description: The first section reviews the basic definitions for Boolean Satisfiability (SAT), surveys themore well-known applications of SAT in Electronic Design Automation (EDA), and introduces basic SATalgorithms and techniques.
The second section addresses state-of-the-art algorithms for SAT, covering the most well-known and usedsearch techniques: non-chronological backtracking, clause recording, randomization, and restarts.Moreover, this section details the techniques recently proposed for fast implementation of SAT solvers.In addition, this section surveys recent research work in SAT, highlighting the techniques that showpromise for the near future.
The third section focuses on algorithms and data structures for applying SAT in synthesis andcombinational verification. In this application domain, SAT algorithms operate on CNF formulasrepresenting circuits. This can be taken into account by specific heuristics. In this context we also discussalgorithms of automatic test pattern generation (ATPG) and compare them with related SAT algorithms.
The fourth section describes the application of SAT-algorithms in equivalence checking. We give anintroduction to state-of-the-art equivalence checking algorithms, and focus on the role of SAT inequivalence checking.
The fifth section focuses on how SAT methods can be used to check properties of sequential circuits. Wefirst demonstrate how to model synchronous gate-level circuits and safety properties. After this, weintroduce a technique called bounded model checking. Given a circuit and a safety property, this analysisuses SAT algorithms to search for paths leading to a state where the safety property is violated.
Finally, in the sixth section, we continue our investigation of SAT-based model checking. A troublesomeaspect of bounded model checking is that although it excels at finding failures, it is not a practical methodfor proving that a given system is safe. We therefore demonstrate how bounded model checking can begeneralized to SAT-based induction---a complete proof method for safety properties. Finally, we concludeby discussing SAT-based reachability analysis.
TUTORIAL 3
LOW-POWER/LOW-ENERGYEMBEDDED SOFTWARE: WHAT, WHY AND HOW?
Speakers:
Luca Benini - DEIS Univ. di Bologna, Bologna, ItalyNikil Dutt - Univ. of California, Irvine, COPeter Marwedel - Univ. of Dortmund, Dortmund, Germany
Background: Power and energy issues have become important, if not primary constraints for manyembedded systems. With the increasing importance and content of software in contemporary embeddedsystems, designers need to understand how software issues can affect power dissipation. Recently severalresearch efforts have addressed software energy and power issues, and there is growing industrial interestin understanding the interaction between software and power/energy.
Description: With a focus on programmable embedded systems, this tutorial will:
- survey the interaction of architecture, operating systems, compilers and memories from a power/energyfocus,
- present specific contributors of each part to power and energy, and
- outline software techniques for minimization of power/energy.
In the first section, an introduction to embedded processors and energy consumption of embeddedsoftware is provided.
Next, architectures of embedded systems are presented. The focus is on programmable embedded systemsand their memory organization. Differences between different types of memories are explained and theirimpact on the resultant energy consumption are highlighted.
In the next section, energy-saving compiler optimizations are considered. These are based on models ofthe energy consumption of processor-based systems. For most systems, a major portion of the energy isconsumed by memory references. This energy can be reduced by exploiting memory hierarchies. Thepotential of standard compiler optimizations for saving energy is also considered in this section of thetutorial.
The final section describes system software and real-time operating system (RTOS) issues. This willinclude hardware for RTOS-based power management, software support for power management, power-aware process scheduling and power-aware device management. Exploitation of application-specificinformation and power management of distributed systems will also be covered.
TUTORIAL 4
OPTIMIZATION STRATEGIESFOR PHYSICAL SYNTHESIS AND TIMING CLOSURE
Speakers:
Charles J. Alpert - IBM Corp., Austin, TXSachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MNSalil Raje - Monterey Design Systems, Inc., Sunnyvale, CA
Background: This tutorial overviews various optimization techniques that can be utilized within aphysical synthesis tool and/or achieve timing closure. The target audience consists of circuit designers whoutilize these techniques, CAD engineers, and academic researchers. Familiarity with basic concepts inphysical design is assumed.
Description: The first part of the tutorial discusses strategies for buffer insertion and wire sizing for agiven net, focusing on the two stage methodology of first constructing a Steiner tree, then applyingdynamic programming optimization. We show how to manage capacitance, polarity, and slew constraintswhile also performing blockage-aware routing. We also discuss different approaches to interconnectplanning and physical resource allocation.
The second part describes optimizations that may be made at the gate and transistor levels. We will primarilyfocus on optimizations for transistor and gate sizing and local resynthesis. Additionally, issues related totransistor level optimization under dual threshold voltages will be addressed.
The third part is related to the consideration of signal integrity issues in design. One aspect relates to thedesign of supply networks to provide reliable voltage levels. We show the potential dangers that unreliablesupply networks can have on timing closure and routability. A methodology to deal with the reliability ofsupply voltages in the design planning process will be put forward.
The fourth part will integrate all the techniques discussed into a physical synthesis methodology. Severalplacement techniques will be reviewed. Pros and cons of each in light of physical synthesis for designclosure will be discussed. Factors that affect design closure include Congestion, Scan, Clocking, andPower Topology; each will be addressed using a coherent flow that will achieve the right trade-offs.
ICCAD 2002
AGAIN THIS YEAR: ICCAD submissions must be madeelectronically, in PDF format through the ICCAD web site. Referencethe ICCAD WEB page for instructions on electronic submissions:http://www.iccad.com.
Please submit the following in PDF format:• 1 page abstract should state clearly and precisely what is new
and point out the significant results. The IMPACT, or potentialimpact, of the contribution will play a major role in the evaluation.
• 1 paper of no more than 8 pages using proceedings format ,double columned, 9pt or 10pt fonts including figures, tables andreferences. (in the proceedings, four pages are free of charge andeach page beyond four pages is charged $100.00 per page).
• Papers in the wrong format, exceeding the eight pagelimit, or identifying the authors or their affiliations willbe rejected immediately.- Previously published papers will not be considered: this
includes papers appearing in published workshopproceedings. Papers presented only orally, or only availablethrough informal distribution, will be considered.
- Authors should clearly address the significance of theircontribution as part of the paper.
AUTHOR’S SCHEDULE
Deadline for submissions: April 17, 2002Notification of acceptance: June 28, 2002Deadline for final version: August 9, 2002
Papers will not be accepted for submission after 5:00 PMMountain Daylight Time, April 17, 2002 . This deadline is firmand inflexible. No exceptions will be made.
Please direct all correspondence to:
ICCAD Publications Department
MP Associates, Inc. Telephone: (303) 530-45625305 Spine Rd., Suite A Fax: (303) 530-4334Boulder, CO 80301 Email: [email protected]
ICCAD Home Page:http://www.iccad.com
AREAS OF INTERESTOriginal technical papers on (but not limited to) thefollowing topics are invited:
The INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - 2002ICCAD is oriented towards Electrical Engineering CAD professionals,
concentrating on CAD for Electronic Circuit Design.
IEEE CIRCUITS &SYSTEMS SOCIETY®
®
special interest group on
des ign au tomat ion
DESIGN AUTOMATIONTECHNICAL COMMITTEE
CALL FOR PAPERS
DOUBLETREE HOTELSAN JOSE, CA
1) PHYSICAL DESIGN AND TEST
1.1 Placement and floorplanning techniques. RTL area estimation.Partitioning for layout.
1.2 Timing-driven and noise avoidance routing. Automatic special netrouting. Layout for manufacturability. Routing estimation.
1.3 Module generation and layout synthesis. Layout migration.Symbolic design & compaction. Physical design planning. Layoutverification.
1.4 Analog, RF, and mixed signal circuit synthesis, optimization andlayout. Analog, RF and mixed signal simulation techniques. Mixedtechnology design simulation (thermal, packaging,micromechanical).
1.5 Testing. Yield and manufacturability analysis. Fault modeling,delay test, analog and mixed signal test. Fault simulation. ATPG.BIST and DFT. Memory, core and system test.
2)SYNTHESIS AND SYSTEM DESIGN
2.1 Combinational and sequential logic synthesis. Optimization forarea, timing, power. FPGA optimization. Interaction betweenlayout and logic synthesis. Technology mapping. Asynchronouscircuit design.
2.2 High-Level Synthesis. Datapath and control synthesis. Synthesiswith IP libraries and reuse. Estimation and analysis in high-levelsynthesis. Memory system synthesis and optimization. HWinterface synthesis.
2.3 HW/SW co-synthesis. System synthesis. Hardware platformsynthesis and optimization. ASIP synthesis. Core based design.Embedded software synthesis. HW and SW estimation andanalysis. Interface synthesis.
2.4 Specification, modeling and validation of embedded systems.Real-time software and RTOS. System level reuse techniques.Embedded systems engineering Rapid system prototyping.
3)VERIFICATION, MODELING AND SIMULATION
3.1 Interconnect parameter extraction and circuit modelgeneration. Interconnect level analysis. Noise analysis.
3.2 Gate, switch, and circuit level timing and power analysis.
3.3 Formal Verification techniques. Switch, logic and high-levelsimulation and design validation. HW/SW co-simulation.Combinational and sequential equivalence checking. Modelchecking. Theorem proving.
Proposals for Panel Sessions and Tutorials are also invited.Panel Proposals should be sent to the Vice Chair.Tutorial Proposals should be sent to the Tutorial Chair.
ASSOCIATION FOR COMPUTING MACHINERY/SIGDA
THE IEEE COMPUTER SOCIETY
Sponsored by: In cooperation with:
NOVEMBER 5-9, 2002
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AUTHOR INFORMATION AND FORMAT
®IEEE CIRCUITS &SYSTEMS SOCIETY®
CONFERENCE CHAIRLawrence PileggiCarnegie Mellon [email protected]
PROGRAM CHAIRAndreas KuehlmannCadence Berkeley [email protected]
PROGRAM VICE CHAIRHidetoshi OnoderaKyoto [email protected]
PAST CHAIRRolf ErnstTech. Univ. of [email protected]