nemi cost analysis: optical versus copper...

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NEMI Cost Analysis: Optical Versus Copper

Backplanes

Presented on behalf of project members by Adam Singer

ECWC / APEXFebruary 22, 2005

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OE TIG ProjectsOE TIG Projects

Optoelectronics Substrates Project

Leader: Jack Fisher (consultant)[email protected]

Sub-groups

PCB cost model: Adam [email protected]

Optical system: Peter [email protected]

Optical materials: Bruce [email protected]

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AgendaAgenda

• Background / reason for iNEMI project• Updated goal• Status report

– Cost modeling– System descriptions– Optical connector challenges– Optical waveguide technologies

• Conclusions

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OE Trends & DriversOE Trends & Drivers

• Starting to see OE equipment revenue growth, e.g. access & FTTP,PONs

• Traffic continues to grow 50-100% pa, triple play (data, VoIP, video), retail, file swapping...

• Distributed systems (1000s servers) require high speed interconnects• Copper can support up to 10G over 1m, 40G in some cases, at

increased cost: mtrls, line spacing, signal conditioning...• Emerging OE technologies: reconfigurable/active systems, polymer

waveguides & substrates, Si optical emission & modulation (Intel), optical band gaps...

• Although fiber interconnects will be continue to be used, optical functions, initially transmission, will co-exist with electrical in the printed wiring board

• COST reduction of pkg, assembly & test, remains significant driver

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Market StatusMarket Status

Courtesy of Prismark, September 2002

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Current Interconnect BottleneckCurrent Interconnect Bottleneck

• Increasing chip-performance leads to problems with conventional electrical intrasystem interconnection technologies (Siemens SBS C-LAB, 2002):

– Increasing electromagnetic radiation– Limited bandwidth due to high frequency skin effect– High pin-count through limited bandwidth– Increasing signal integrity and timing problems– Increased data rate leads to disproportional increased costs per

bit• Transmission speeds reach their physical limits when power

consumption is increased and there is no obvious increase in thepropagation speed

• It is the ability of optical interconnections to operate at high data rates (>2.5 GHz) with superior signal integrity that makes them an exploitable alternative

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JIEP Optical Packaging RoadmapJIEP Optical Packaging Roadmap

Source: Japan Institute of Electronics Packaging & SEMI

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Copper RoadmapCopper Roadmap

Teradyne connectors HDM VHDM & VHDM L-series VHDM-HSD Gbk GBx

ERNI connectors ERmet Ermet Ermet ZD ERmetZD Ermet Zero XT

Tyco connectors HM-ZD Z-Pack HM-ZD Z-Pack HM-ZD

MultiGig RT-1 MultiGig RT-2 MultiGig RT-3

FCI Metral 2000 AirMax VS AirMax VS AirMax VS AirMax

Metral 4000

Fujitsu FCN-261Z00x FCN260D

Winchester Xcell SIP-1000 I platform

Molex Molex is a Teradyne licensee

Taps required

Velio GigaCore2

Shared Bus ?Point to Point ?Multi point ? Sub type?

Generic Copper Backplane Bandwidth Technology Roadmap

PTFE / Ceramic, Df = 0.002 - 0.0009FR-4, Df = 0.020 PPO / CE, Df = 0.015-0.008

BT / APPE, Df = 0.010

PTFE, Df = 0.009 - 0.003

1 Gbps ─ 2.5 GBPS ─ 3.125 Gbps ─ 4.0 Gbps ─ 6.125 Gbps ─ 10 Gbps - 40Gbps

Materials

PCB Technology

Connector Launch Design

Transmission Line Design

Differential pair, length, type (Surface microstrip, embedded microstrip, stripline, edge coupled, broadside coupled), location in stack Single transmission line, Length management

Processes Standard processes Backdrilling ─ Dual density drilling?

Bus Architecture

Receiver / Transmitter Signal Conditioning Chip

Set

Pad in via or PTH, micro vias, buried vias

Decrease PTH diameter, Remove non-functional pads, Increase anti-pad diameter (Clearance ring)

Connector Technology

Via Design

GigaCore

None Required One Two Multiple

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Optoelectronics ConceptsOptoelectronics Concepts

Photons• Zero Rest mass• FxD > 1014 Hz x 100km• Boson => Mult. Signals• OE Conversion needed

Best for long distance,high speed

Electrons• 9.11 x 10-31kg• FxD > 1010 Hz x 0.001km• Fermion: One Signal• No OE Conversion

Best for very short distance(<5 meters) at moderate tohigh speed

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Optoelectronics Substrates ProjectOptoelectronics Substrates Project

Original Purpose Statements:• This purpose of this group is to addresses the implementation of

optical and optoelectronic technologies in printed wiring boards(PWB’s) used for packaging, or for other applications.

The areas to be addressed include:• An understanding of the drivers and the constraints of producing

optoelectronic PWB’s including cost analysis and tradeoffs.• Design considerations for materials used for PWB fabrication and

assembly, including material properties• Manufacturability of waveguides and the integration of waveguides in

PWB’s• Component mounting and interconnecting structures• Performance and testing of waveguides and connector attachments

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Optical Optical BackplaneBackplane CostCost

Cost-performance is the key driver; we need an industry metricto compare optical vs. Cu-based, e.g. $/(Gb/s/channel/m)

Crossover zone:changeover will not be

immediate, but will rangedepending on issues includingcost sensitivity, reliability, and

design limitations

Bandwidth x Distance

Rel

ativ

e C

ost Copper

PCB

Optical PCB

20042000

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Current Statement:• Initial investigation (2002) indicated that the OEMs were not planning

to use optoelectronics in their next generation machines• The OEMs were all working on internal analysis of optoelectronic

solutions and were all interested in participating in a NEMI technology analysis activity

• There are numerous estimates of how far copper can be pushed to increase data rates. The estimates range from 2.5 Gb/s to 40 Gb/s.

• It was decided to do a business analysis of copper vs. optoelectronics

• The product to be analyzed will be a communications industry backplane, e.g. Terabit router

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• Project Objectives:– Develop cost models, including assembly and test, of a high

performance “product” (black box emulator)– Copper and optical backplane versions– Run cost models for various speeds and system configurations,

using appropriate sets of components and technologies

• Project Benefits:– Information exchange between suppliers (component, technology..),

assemblers and system OEMs– Define industry relevant cost-performance metric(s)– Identify technology gaps and barriers to implementation – Roadmaps and cost models will be available for industry use

• Meeting Objectives:– Report work-in-progress– Promote awareness, attract new participants

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• Project started in June 2003, in open/forming stage• Bi-weekly telecons• Very good participation

– Several OEMs, fabricators, CMs, material suppliers• First pass output of copper backplane model run and validated by

3 fabricators• Draft electrical technology road map,1-10(40) Gbps, includes

connectors, signal conditioning, chip-sets and high performance substrates

• Starting to develop connector input to the model• Discussing the optoelectronic technology alternatives

– Fiber, Waveguide, Polymer• Developing list of optical attributes and performance issues• Draft optical roadmap by June

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Cost Modeling MethodCost Modeling Method

• Based on Technical Cost Modeling, as developed by IBIS Associates / MIT

• Activities Based Costing, plus engineering relationships– Assembly cycle time = f(design, mtrls, equipment)

Design

Materials Processing

Design

Materials

Machine Limits

Cycle Time Calculation

Equipment & Related

Inputs Cost output

Labor

Building

Utilities

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Electrical Backplane Cost ModelElectrical Backplane Cost Model

Context• North American facility• Equipment assumes max 24 inch width conveyors• Yields reflective of 8 mil line / space• Drilling reflects 20 mil minimum diameter• Medium throughput (350Ksqft/yr top surface)

Product• 32 metal layers, no buried vias• FR-4, 24x20 inch panel, 20x18 inch finished board• 5,000 drilled holes per board• ~1-3 Gbps performance

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Back Plane Cost ModelBack Plane Cost Model

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Strategy for System Cost ModelsStrategy for System Cost Models

• Seek input from relevant experts:– Technology and hardware selection, identify gaps (white paper)– Issues & concerns, e.g. manufacturing yield, reliability– Requirements for performance, application, future system

(IP, confidentiality issues)• Define detailed sets of attributes, electrical & optical• Draft roadmaps: understand which and how the attributes change

with performance• Define 1st generation black box system (top down approach)• Choose logical set(s) of the key attributes (80/20)• Obtain cost data, build initial cost model• Verify and improve model with actual costs, expert input• Run what if sensitivities: speed, no. lines, hardware variation,

yields, …• Repeat for 2nd generation system

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Electrical Backplane Attributes 1Electrical Backplane Attributes 1--40G 40G (Partial)(Partial)

• Receiver/Transmitter signal conditioning chip set:– Bus type: multipoint, point-to-point– Signaling: single-ended, differential, CML NRZ, 4PAM– Standard: DDR2/3/4, LVDS, XAUI, CEI-6G-SR/LR, CEI-11G-SR– Equalisation: 400 mV emphasis, DFE 5/8 tap, duobinary

• PCB Technology:– Materials: FR4, PPO/CE, FR4013, BT/APPE, PTFE– Loss: Df = 0.02 - 0.002– Processes: standard, backdrilling, dual density drilling– Transmission line: single-ended, loosely coupled, broadside– Distance: up to 1m– Via/connector launch: PTH, pad in via, micro, buried, differential anti-

pad

• Connector Technology:– Several vendor types

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Optical Backplane Attributes 1Optical Backplane Attributes 1--40G 40G (Partial)(Partial)

• Receiver/Transmitter:– Link loss budget: 0.5 dB per channel– Source/modulation: < 5G VCSEL, <10G F-P(int), >10G DFB (ext)– Channel density: transceivers, VCSEL / PD arrays– Multiplex: serial (TDM), parallel (12-72 channels), CWDM

• Light coupling:– Type: butt coupled, index matched, lens, mirror/grating, free-space

• Optical carrier technology: – Fiber: single, ribbon, flex/laminated (shuffle), MM or SM– Waveguide: surface, embedded, organic, silica, PLC– Impact on PCB design rules, electrical layer reduction

• Connector:– Coupling losses: tolerance, cleanliness (contamination has critical impact

on yield & costs, but hard to quantify)

• Assembly & Test

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ETHERNET (Layer2/3 Switch)ETHERNET (Layer2/3 Switch)WB #1 Electrical, XAUI over the backplaneWB #1 Electrical, XAUI over the backplane

Electrical Line Card

BP Interface connector C

XFP 10 Gb/s

Ethernet MACNP/TM PHY

10 Gb/s

XFI

3.125 Gb/s

XAUI

622 Mb/s

SPI4.2

3.125 Gb/s

XAUI

Switch Card

BP Interface connector C

Layer 2/3 Switch Fabric

3.125 Gb/s

XAUI

FIC: Fabric Interface ChipNP/TM: Network Processor/Traffic ManagerMAC: Medium Access Controller .PHY: Physical Interface

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ETHERNET (Layer2/3 Switch)ETHERNET (Layer2/3 Switch)WB #1 Electrical, 10G Native over the backplaneWB #1 Electrical, 10G Native over the backplane


BP Interface connector B

XFP 10 Gb/s


10 Gb/s

XFI

Nom 10 Gb/s

10GbE

622 Mb/s

SPI4.2

Nom 10 Gb/s

10GbE

Switch Card

BP Interface connector B


Nom 10 Gb/s

10GbE

FIC: Fabric Interface ChipNP/TM: Network Processor/Traffic ManagerMAC: Medium Access ControllerPHY: Physical Interface

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ETHERNET (Layer2/3 Switch)ETHERNET (Layer2/3 Switch)BB #1 Optical, XAUI rate over the backplaneBB #1 Optical, XAUI rate over the backplane


SNAP-12 or POP-4

XFP 10 Gb/s


10 Gb/s

XFI

3.125 Gb/s

XAUI

622 Mb/s

SPI4.2

3.125 Gb/s

XAUI

Switch Card

SNAP-12 or POP-4


3.125 Gb/s

XAUI

FIC: Fabric Interface ChipNP/TM: Network Processor/Traffic ManagerMAC: Medium Access Controller .PHY: Physical Interface

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ETHERNET (Layer2/3 Switch)ETHERNET (Layer2/3 Switch)BB #1 Optical, 10G Native over the backplaneBB #1 Optical, 10G Native over the backplane

Electrical Line CardBP Interface SNAP-12 or POP-4 (10G)

XFP 10 Gb/s


10 Gb/s

XFI

Nom 10 Gb/s

10GbE

622 Mb/s

SPI4.2

Nom 10 Gb/s

10GbE?

Switch Card


Nom 10 Gb/s

10GbE?BP Interface SNAP-12 or POP-4 (10G)

FIC: Fabric Interface ChipNP/TM: Network Processor/Traffic ManagerMAC: Medium Access ControllerPHY: Physical Interface

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Future Optical Black BoxesFuture Optical Black Boxes

• Optical Black Box #2:– 40G implementation of BB#1, and/or fully populated

frame (3 ATCA shelves, 16 cards per shelf), and/or full mesh system (high channel count) TBD

– Fiber based– Possibly use CWDM optical multiplexed signals within

the fabric to overcome space restrictions• Optical Black Box #3:

– Fiber Flexplane version of BB#2 (TBD)• Optical Black Box #4:

– Organic embedded waveguide in backplane, version of BB#2

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OECB Technology ChallengesOECB Technology Challenges

n x 4 flipchip VCSEL array Optical layer, with

embedded MM waveguides

Optical

underfill

Optical via Multi-layer FR4 board Optical edge

connectorChoice of Glass or Polymer optical layers

Choice of embedded or overlaid waveguides

45o mirror

Choice of assembled or integrated mirrors

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Coupling ChallengeCoupling Challenge

Ideal process route is to combine mirror into

board during PCB fabrication, for direct active

component attach.

Limited alignment tolerance stack-up.

Low cost assembly achievable.

Source: Siemens SBS C-Labs

VCSEL

Mirror

Integrated Mirror ?

Several research avenues involving the insertion

of mirrors or carriers.

Large alignment tolerance stack-up.

High cost issues due to small parts, and tight

alignment tolerances.

Assembled Mirror ?

VCSELMirror

Carrier

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Optical Material CharacteristicsOptical Material CharacteristicsCoupling Applications Producer Status

Methods (3)Optical WaveguidesPolymer

Deposited Fiber + Free Space Backplanes, General interconnect R&D

Photoimaged

Direct fiber/component, I/O mirror arrays, Array connectors,

single/stacked layers

Stand alone flex or board/substrate interconnects-chip, component, functions, links, fully connectorized,

stacked or single layer. Optical CrossLinks

Custom Prototying & Production

Embossed Press Fiber + Surface (4) WDM, Splitters, Couplers, ADM OptoFoil - Fraunhofer Institute Production Roll Fiber + Surface (4) Ribbon Cables, Backplanes 3M, Promerus Production

Trench & Fill Fiber + Surface DWDM, VOA, ADM, Splitters, Couplers Shipley, DuPont Photonics, NTT, Neophotonics R&D

Micromolded Fiber/F.S./Surface (4) Light Pipes, Backplanes, Passive Interconnect Promerus Production

Molded Fiber + Free Space Light Pipes, Backplanes ?

Inorganic

Silica on Silicon Fiber end DWDM, ADM, AWG Neophotonics, Symmorphics Production

Polysilicon Fiber end Chip Switches, Modulators Intel Research

Hybrids (6) Fiber end VOA, ADM Lightwave Microsystems, Neophotonics Production

Optical FiberEmbedded Fiber Glass Fiber + Surface Backplanes, Lightpipes Hitachi Chemical (Wire Wrap) R&D Polymer Fiber + Surface Backplanes, Lightpipes Northrup-Grunman R&D

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Optical Material Characteristics (2)Optical Material Characteristics (2)Field Size WG Mode Waveguide NRE Cost Cost

in. 830 nm 1550 nm Type Structure Pitch (2) $/Layer (5) $/ft2/Layer (5)Optical WaveguidesPolymer

Deposited 12 X 18 0.1 0.5 Rib Multimode Coarse 1K 5 - 10

Photoimaged

12 X 18, 13" reel to

reel 0.08 0.7 Rib & EmbeddedSingle Mode &

Multimode Hyperfine 100 to~2500 30-50

Embossed Press Wafer (1) 0.1 0.1 Embedded Single/Multi Fine 10K 1,500 Roll 36 X 36 0.1 0.3 Rib & Embedded Single/Multi Fine 20K 5 - 10

Trench & Fill Wafer 0.1 0.1 Embedded Single/Multi Fine 10K 1,500

Micromolded 36 X 36 0.1 0.3 Rib & Embedded Single/Multi Fine 12K 10

Molded 24 X 24 0.1 0.5 Rib Multimode Coarse >50K 5

Inorganic

Silica on Silicon Wafer < 0.1 < 0.1 Rib & Embedded Single/Multi Fine 10K 1,500

Polysilicon Wafer ? ? Embedded Single Mode Fine 15K 3000

Hybrids (6) Wafer < 0.1 < 0.1 Rib & Embedded Single Fine 15K 1,700

Optical FiberEmbedded Fiber Glass 18 X 24 < 0.1 < 0.1 Embedded Single/Multi Coarse 5K 50 Polymer 18 X 24 < 0.1 < 0.1 Embedded Multimode Coarse 5K 30

Attenuation, dB/cm

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Next StepsNext Steps

• Run multiple copper sensitivities– Materials, via qty. and types,– Layers counts, etc.

• Develop connector data base– Cost, type, application

• Add signal conditioning, bus chip-sets, ASICs– May need resource assistance

• Complete optical attributes and optical technology roadmap• Determine the copper / opto architectures to be modeled for high

performance– Difficult because it is often proprietary information

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ConclusionsConclusions

• Performance of copper backplanes will continue to improve, at increased cost to achieve signal integrity

• Benefits of optical outweigh cost for critical applications, e,g, avionics, clock distribution in high perf systems

• Future generation, high bandwidth telecom/office systems likely to have optical distribution

• The problems of assembling and handling fiber/connectors are drivers for integrating optical waveguides in the PWB

• Improved coupling and light-turning technologies are required• The initial choices of optical technology and component set have major

impact on overall costs • Cost-performance models of emulator systems are useful way to

understand the (relative) costs, test different choices• Immediate need for practical cost-performance metric(s), e.g. $/bit,

$/(Gbps/m/channel)

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ContactsContacts

Leader: Jack Fisher (consultant)[email protected]

PCB cost model: Adam [email protected]

Optical system: Peter [email protected]

Optical materials: Bruce [email protected]

Thank YouThank YouOptoelectronics Substrates Optoelectronics Substrates

ProjectProject

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www.inemi.orgwww.inemi.orgEmail contacts:Email contacts:

Jim McElroy Jim McElroy

[email protected]@inemi.org

Bob PfahlBob Pfahl

[email protected]@inemi.org

nemi cost analysis: optical versus copper...

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