ncp1652 - controller, pfc, high efficiency, single stage

© Semiconductor Components Industries, LLC, 2010

April, 2010 − Rev. 31 Publication Order Number:

NCP1652/D

NCP1652, NCP1652A

Controller, PFC, High Efficiency, Single Stage

The NCP1652 is a highly integrated controller for implementing power factor correction (PFC) and isolated step down ac−dc power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for notebook adapters, battery chargers and other off−line applications with power requirements between 75 W and 150 W. The single stage is based on the flyback converter and it is designed to operate in continuous conduction (CCM) or discontinuous conduction (DCM) modes.

The NCP1652 increases the system efficiency by incorporating a secondary driver with adjustable nonoverlap delay for controlling a synchronous rectifier switch in the secondary side, an active clamp switch in the primary or both. In addition, the controller features a proprietary Soft−Skip™ to reduce acoustic noise at light loads. Other features found in the NCP1652 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier.

Features

• Dual Control Outputs with Adjustable Non Overlap Delay forDriving a Synchronous Rectifier Switch, an Active Clamp Switch orBoth

• Voltage Feedforward Improves Loop Response

• Frequency Jittering Reduces EMI Signature

• Proprietary Soft−Skip™ at Light Loads Reduces Acoustic Noise

• Brown Out Detector

• Internal 150 ms Fault Timer

• Independent Latch−Off Input Facilitates Implementation ofOvervoltage and Overtemperature Fault Detectors

• Single Stage PFC and Isolated Step Down Converter

• Continuous or Discontinuous Conduction Mode Operation

• Average Current Mode Control (ACMC), Fixed Frequency Operation

• High Accuracy Multiplier Reduces Input Line Harmonics

• Adjustable Operating Frequency from 20 kHz to 250 kHz

• These are Pb−Free Devices

Typical Applications

• Notebook Adapter

• High Current Battery Chargers

• Front Ends for Distributed Power Systems

• High Power Solid State Lighting

SO−20 WBDW SUFFIXCASE 751D

MARKINGDIAGRAMS

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20

1

NCP1652AWLYYWWG

A = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package

SOIC−16D SUFFIX

CASE 751B

NCP1652GAWLYWW

See detailed ordering and shipping information in the packagedimensions section on page 32 of this data sheet.

ORDERING INFORMATION

NCP1652AGAWLYWW

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17

18

16

15

14

13

12

4

3

5

6

7

8

9

1110

19

20

2

1CT

Ramp Comp

AC IN

FB

VFF

CM

NC

NC

AC COMP

Latch−Off

Startup

NC

NC

GND

Out B

Out A

VCC

Ispos

Iavg

Rdelay

1

2

3

4

5

6

7

8

16

12

11

10

9

(Top View)

VFF

CT

Ramp Comp

AC IN

FB

CM

AC COMP

Latch−Off

Startup

VCC

Ispos

Rdelay

Iavg

13 OUT A

15

14

GND

OUT B

SO−20 WB SOIC−16

Figure 1. Pin Connections

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AC COMP

AC IN

Startup

Ispos

Dual HVstart−upcurrent source

VCCManagement

HV currentVCC(off)

VDD

Reset

StartVCC OK

Reset

VDD

GND

VCC

Latch−Off

S

RQ

tLatch(delay)

blanking

Reset

Latch

−+

Vlatch(high)

−+

Vlatch(low)

VDD

Vlatch(clamp)

OVP Comparator

OTP Comparator

Ilatch(shdn)

OUTB

OUTA

Iavg

Rdelay

CM

VFF

FB

CT

RampComp

Oscillator

DC MaxSawtooth

JitterAdj.

S

RQ

DelayAdj.

−+

gm

ReferenceGenerator

−+ V−to−I

+ inverter−

+

−

+

21.33k�

21.33k�

tLEB

Blanking

tLEB

Blanking

V−to−I

V−to−I

4V

−+

+

VSSKIP

tSSKIPStart

Soft−skip Ramp

Delay

−+

+

VSSKIP(TLD)

Terminate

−

+

+

VSSKIP(sync)

Ramp Comp

Inst. current B

Inst.current B

Inst. current A

Jitter

Ramp. Comp.

Adj.

Ramp Comp

Clock

DC Max

Clock

DC Max

Delay

Delay

FB

−+

+

VOVLD

tOVLDEnable

OverloadTimer

RFB

VDD

FB

S

RQ OVLD

x 2counter

Enable

Reset−+

+

VBO

VFF

BO

Out

VCCOK

BOOVLD

Latch

AC errorAmplifier

Current senseamplifier

PWMcomparator

PWM SkipComparator

AC In skipcomparator

FB skipComparator

Transient Load DetectComparator

FB overloadcomparator

VFF Brown−OutComparator

Ilatch(clamp)

OutputDriver

OutputDriver

gm

+

+

+

Figure 2. Detailed Block Diagram

VFF

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PIN FUNCTION DESCRIPTION

Pin

Symbol Description16 Pin 20 Pin

1 1 CT An external timing capacitor (CT) sets the oscillator frequency. A sawtooth between 0.2 V and 4V sets the oscillator frequency and the gain of the multiplier.

2 2 RAMP COMP A resistor (RRC) between this pin and ground adjust the amount of ramp compensation that isadded to the current signal. Ramp compensation is required to prevent subharmonic oscilla-tions. This pin should not be left open.

3 3 AC IN The scaled version of the full wave rectified input ac wave is connected to this pin by means ofa resistive voltage divider. The line voltage information is used by the multiplier.

4 4 FB An error signal from an external error amplifier circuit is fed to this pin via an optocoupler orother isolation circuit. The FB voltage is a proportional of the load of the converter. If the voltageon the FB pin drops below VSSKIP the controller enters Soft−Skip™ to reduce acoustic noise.

5 5 VFF Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of aresistive divider and an averaging capacitor. The information is used by the Reference Generat-or to regulate the controller.

6 6 CM Multiplier output. A capacitor is connected between this pin and ground to filter the modulatedoutput of the multiplier.

7 NC

8 NC

7 9 AC COMP Sets the pole for the ac reference amplifier. The reference amplifier compares the low fre-quency component of the input current to the ac reference signal. The response must be slowenough to filter out most of the high frequency content of the current signal that is injected fromthe current sense amplifier, but fast enough to cause minimal distortion to the line frequencyinformation. The pin should not be left open.

8 10 Latch Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latchesthe controller. This input can be used to implement an overvoltage detector, an overtemperaturedetector or both. Refer to Figure 69 for a typical implementation.

9 11 Rdelay A resistor between this pin and ground sets the non−overlap time delay between OUTA andOUTB. The delay is adjusted to prevent cross conduction between the primary MOSFET andsynchronous rectification MOSFET or optimize the resonant transition in an active clamp stage.

10 12 IAVG An external resistor and capacitor connected from this terminal to ground, to set and stabilizesthe gain of the current sense amplifier output that drives the ac error amplifier.

11 13 ISpos Positive current sense input. Connects to the positive side of the current sense resistor.

12 14 VCC Positive input supply. This pin connects to an external capacitor for energy storage. An internalcurrent source supplies current from the STARTUP pin VCC. Once the voltage on VCC reachesapproximately 15.3 V, the current source turns off and the outputs are enabled. The drivers aredisabled once VCC reaches approximately 10.3 V. If VCC drops below 0.85 V (typical), the star-tup current is reduced to less than 500 �A.

13 15 OUTA Drive output for the main flyback power MOSFET or IGBT. OUTA has a source resistance of13 � (typical) and a sink resistance of 8 � (typical).

14 16 OUTB Secondary output of the PWM Controller. It can be used to drive synchronous rectifier, andactive clamp switch, or both. OUTB has source and sink resistances of 22 � (typical) and 11(typical), respectively.

15 17 GND Ground reference for the circuit.

18 NC

19 NC

16 20 HV Connect the rectified input line voltage directly to this pin to enable the internal startup regulator.A constant current source supplies current from this pin to the capacitor connected to the VCCpin, eliminating the need for a startup resistor. The charge current is typically 5.5 mA. Maximuminput voltage is 500 V.

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MAXIMUM RATINGS (Notes 1 and 2)

Rating Symbol Value Unit

Start_up Input VoltageStart_up Input Current

VHVIHV

−0.3 to 500�100

VmA

Power Supply Input VoltagePower Supply Input Current

VCCICC

−0.3 to 20�100

VmA

Latch Input VoltageLatch Input Current

VLatchILatch

−0.3 to 10�100

VmA

OUTA Pin VoltageOUTA Pin Current

VoutAIoutA

−0.3 to 20�1.0

VA

OUTB Pin VoltageOUTB Pin Current

VoutBIoutB

−0.3 to 20�600

VmA

All Other Pins VoltageAll Other Pins Current

−0.3 to 6.5�100

VmA

Thermal Resistance, Junction−to−Air0.1 in” Copper0.5 in” Copper

�JA130110

°C/W

Thermal Resistance, Junction−to−Lead RΘJL 50 °C/W

Maximum Power Dissipation @ TA = 25°C PMAX 0.77 W

Operating Temperature Range TJ −40 to 125 °C

Storage Temperature Range TSTG −55 to 150 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. This device series contains ESD protection and exceeds the following tests:

16 pin package:Pin 1−15: Human Body Model 2000 V per JEDEC standard JESD22, Method A114.

Machine Model 200 V per JEDEC standard JESD22, Method A115.Pin 16 is the high voltage startup of the device and is rated to the maximum rating of the part, 500 V.

20 pin package:Pin 1−19: Human Body Model 2000 V per JEDEC standard JESD22, Method A114.

Machine Model 200 V per JEDEC standard JESD22, Method A115.Pin 20 is the high voltage startup of the device and it is rated to the maximumrating of the part, or 500 V.

2. This device contains Latchup protection and exceeds ±100 mA per JEDEC Standard JESD78.

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Figure 3. Typical Application Schematic

CT

Ramp Comp

AC IN

FB

VFF

CM

AC COMP

LATCH

HV

GND

OUTB

OUTA

VCC

Ispos

Iavg

Rdelay

NCP1652

EMI Filter

NTC

Latch

VCC

FB

FB

Latch

VCC

1

10 11

+

_

+ +

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ELECTRICAL CHARACTERISTICS (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV,COUTA = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 k�, Rdelay = 49.9 k�,COUTB = 330 pF, RRC = 43 k�, For typical Value TJ = 25°C, for min/max values TJ = −40°C to 125°C, unless otherwise noted)

Parameter Test Condition Symbol Min Typ Max Unit

OSCILLATOR

Frequency fosc 90 100 110 kHz

Frequency Modulation in Percentageof fOSC

– 6.8 – %

Frequency Modulation Period – 6.8 – ms

Ramp Peak Voltage VCT(peak) – 4.0 – V

Ramp Valley Voltage VCT(valley) – 0.10 – V

Maximum Duty Ratio Rdelay = open D 94 − – %

Ramp Compensation Peak Voltage VRCOMP(peak) – 4 – V

AC ERROR AMPLIFIER

Input Offset Voltage (Note 3) Ramp IAVG, VFB = 0 V ACVIO 40 – mV

Error Amplifier Transconductance gm – 100 – �S

Source Current VAC COMP = 2.0 V, VAC IN = 2.0 V, VFF = 1.0 V

IEA(source) 25 70 – �A

Sink Current VAC COMP = 2.0 V, VA C_IN = 2.0 V, VFF = 5.0 V

IEA(sink) −25 −70 – �A

CURRENT AMPLIFIER

Input Bias Current VISPOS = 0 V CAIbias 40 53 80 �A

Input Offset Voltage VAC COMP = 5.0 V, VISpos = 0 V CAVIO −20 0 20 mV

Current Limit Threshold force OUTA high, VAC COMP = 3.0 V,ramp VISPOS, VRamp_Comp = open

VILIM 0.695 0.74 0.77 V

Leading Edge Blanking Duration tLEB – 200 – ns

Bandwidth – 1.5 – MHz

PWM Output Voltage GainPWMk �

4

(VILIM � CAVIO)

PWMk 4.0 5.3 6.0 V/V

Current Limit Voltage Gain (SeeCurrent Sense Section) ISVK �

V(AVG)

VISPOS

ISVk 15.4 18.5 23 V/V

REFERENCE GENERATOR

Reference Generator Gain

k �VAC_REF � VFF

2

VFB � VAC_IN

k – 0.55 – V

Reference Generator output voltage(low input ac line and full load)

VAC IN = 1.2 V, VFF = 0.765 V,VFB = 4 V

RGout1 3.61 4.36 4.94 Vpk

Reference Generator output voltage(high input ac line and full load)

VAC IN = 3.75 V, VFF = 2.39 V,VFB = 4.0 V

RGout2 1.16 1.35 1.61 Vpk

Reference Generator output Voltage(low input as line and minimum load)

VAC IN = 1.2 V, VFF = 0.765 V,VFB = 2.0 V

RGout3 1.85 2.18 2.58 Vpk

Reference Generator output voltage(high input ac line and minimum load)

VAC IN = 3.75 V, VFF = 2.39 V,VFB = 2.0 V

RGout4 0.55 0.65 0.78 Vpk

Reference Generator output offsetvoltage

RGoffset −100 – 100 mV

3. Guaranteed by Design

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Parameter UnitMaxTypMinSymbolTest Condition

AC INPUT

Input Bias Current Into ReferenceMultiplier & Current CompensationAmplifier

IAC IN(IB) – 0.01 – �A

DRIVE OUTPUTS A and B

Drive Resistance (Thermally Limited)OUTA SinkOUTA Source

OUTB SinkOUTB Source

VOUTA = 1 VIOUTA = 100 mA

VOUTB = 1 VIOUTB = 100 mA

RSNK1RSRC1

RSNK2RSRC2

––

––

810.8

1021

1824

2244

�

Rise Time (10% to 90%)OUTAOUTB

tr1tr2

––

4025

––

ns

Fall Time (90% to 10%)OUTAOUTB

tf1tf2

––

2010

––

ns

DRV Low VoltageOUTAOUTB

IOUTA = 100 �AIOUTB = 100 �A

VOUTA(low)VOUTB(low)

––

1.01.0

100100

mV

Non−Overlap Adjustable Delay Range(Note 3)

tdelay(range) 0.08 – 2.8 �s

Non−Overlap Adjustable Delay

LeadingTrailing

Measured at 50% of VOUT, COUTA = COUTB = 100 pF

OUTA Rising to OUTB fallingOUTB Rising to OUTA falling

tdelay(lead)tdelay(trail)

250250

450420

550550

ns

Non−Overlap Adjustable DelayMatching

OUTA Rising to OUTB Falling or OUTBRising to OUTA Falling

tdelay(match) – – 55 %

Soft−Skip�

Skip Synchronization to ac LineVoltage Threshold

VACIN Increasing, VFB = 1.5 V VSSKIP(SYNC) 210 267 325 mV

Skip Synchronization to ac LineVoltage Threshold Hysteresis

VACIN Decreasing VSSKIP(SYNCHYS)

– 40 – mV

Skip Ramp Period (Note 3) tSSKIP − 2.5 – ms

Skip Voltage ThresholdNCP1652NCP1652A

VSSKIP1.040.36

1.240.41

1.560.46

V

Skip Voltage Hysteresis VSSKIP(HYS) 45 90 140 mV

Skip Transient Load Detect Threshold(Note 3)

VSSKIP(TLD) = VSSKIP +0.55 V VSSKIP(TLD) − 1.75 − V

FEEDBACK INPUT

Pull−Up Current Source VFB= 0.5 V IFB 600 750 920 �A

Pull−Up Resistor RFB – 6.7 – k�

Open Circuit Voltage VFB(open) 5.3 5.7 6.3 V

STARTUP AND SUPPLY CIRCUITS

Supply VoltageStartup ThresholdMinimum Operating VoltageLogic Reset Voltage

VCC IncreasingVCC DecreasingVCC Decreasing

VCC(on)VCC(off)

VCC(reset)

14.39.3–

15.410.27.0

16.311.3

–

V

Inhibit Threshold Voltage VHV = 40 V, Iinhibit = 500 �A Vinhibit − 0.83 1.15 V


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Parameter UnitMaxTypMinSymbolTest Condition

STARTUP AND SUPPLY CIRCUITS

Inhibit Bias Current VHV = 40 V, VCC = 0.8 * Vinhibit Iinhibit 40 - 500 �A

Minimum Startup Voltage Istart = 0.5 mA, VCC = VCC(on) – 0.5 V Vstart(min) – – 40 V

Startup Current VCC = VCC(on) – 0.5 V, VFB = Open Istart 3.0 5.62 8.0 mA

Off−State Leakage Current VHV = 400 V, TJ = 25°CTJ = −40°C to 125°C

IHV(off)––

1715

4080

�A

Supply CurrentDevice Disabled (Overload)Device Switching

VFB = OpenfOSC � 100 kHz

ICC1ICC2

––

0.726.25

1.27.2

mA

FAULT PROTECTION

Overload Timer tOVLD 120 162 360 ms

Overload Detect Threshold VOVLD 4.7 4.9 5.2 V

Brown−Out Detect Threshold (enteringfault mode)

VFF Decreasing, VFB = 2.5 V,VAC IN = 2.0 V

VBO(low) 0.41 0.45 0.49 V

Brown−Out Exit Threshold (exitingfault mode)

VFF Increasing, VFB = 2.5 V,VAC IN = 2.0 V

VBO(high) 0.57 0.63 0.69 V

Brown−Out Hysteresis VBO(HYS) − 174 − mV

LATCH INPUT

Pull−Down Latch Voltage Threshold VLatch Decreasing Vlatch(low) 0.9 0.98 1.1 V

Pull−Up Latch Voltage Threshold VLatch Increasing Vlatch(high) 5.6 7.0 8.4 V

Latch Propagation Delay VLatch = Vlatch(high) tlatch(delay) 30 56 90 �s

Latch Clamp Current (Going Out) VLatch = 1.5 V Ilatch(clamp) 42 51 58 �A

Latch Clamp Voltage (ILatch Going In) ILatch = 50 �A Vlatch(clamp) 2.5 3.27 4.5 V

Latch−Off Current Shutdown(Going In)

VLatch Increasing Ilatch(shdn) − 95 − �A


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Figure 4. Oscillator Frequency (fOSC) vs.Junction Temperature

6.0

6.5

7.0

7.5

8.0

−50 −25 0 25 50 75 100 125 150

Figure 5. Oscillator Frequency Modulation inPercentage of fOSC vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

6.0

6.5

7.0

7.5

8.0

−50 −25 0 25 50 75 100 125 150


Figure 6. Oscillator Frequency ModulationPeriod vs. Junction Temperature

3.8

3.85

3.9

3.95

4.0

4.05

4.1

−50 −25 0 25 50 75 100 125 150


Figure 7. Ramp Peak Voltage vs. JunctionTemperature

VC

T(p

eak)

, OS

CIL

LAT

OR

RA

MP

PE

AK

VO

LTA

GE

(V

)

90

92

94

96

98

100

−50 −25 0 25 50 75 100 125 150

D, M

AX

IMU

M D

UT

Y R

AT

IO (

%)

Figure 8. Maximum Duty Ratio vs. JunctionTemperature


−50 −25 0 25 50 75 100 125 1503.8

3.85

3.9

3.95

4.0

4.05

4.1


VC

OM

P(p

eak)

, RA

MP

CO

MP

PE

AK

VO

LTA

GE

(V

)

Figure 9. Ramp Compensation Peak Voltagevs. Junction Temperature

90

95

100

105

110

−50 −25 0 25 50 75 100 125 150


f OS

C, O

SC

ILLA

TO

R F

RE

QU

EN

CY

(kH

z)O

SC

ILLA

TO

R F

RE

QU

EN

CY

MO

DU

LAT

ION

PE

RIO

D (

ms)

OS

CIL

LAT

OR

FR

EQ

UE

NC

YM

OD

ULA

TIO

N (

%)

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50

55

60

65

70

75

80

85

90

−50 −25 0 25 50 75 100 125 150


I EA

(SO

UR

CE

), E

RR

OR

AM

PLI

FIE

RS

OU

RC

E C

UR

RE

NT

(�A

)

Figure 10. Error Amplifier Source Current vs.Junction Temperature

50

55

60

65

70

75

80

85

90

−50 −25 0 25 50 75 100 125 150

Figure 11. Error Amplifier Sink Current vs.Junction Temperature


I EA

(SIN

K),

ER

RO

R A

MP

LIF

IER

SIN

KC

UR

RE

NT

(�A

)

40.0

42.5

45.0

47.5

50.0

52.5

55.0

57.5

60.0

−50 −25 0 25 50 75 100 125 150

Figure 12. Current Amplifier Input BiasCurrent vs. Junction Temperature


CA

VB

IAS, C

UR

RE

NT

AM

PLI

FIE

RIN

PU

T B

IAS

CU

RR

EN

T (�A

)

700

710

720

730

740

750

760

770

−50 −25 0 25 50 75 100 125 150


Figure 13. Current Limit Threshold vs.Junction Temperature

VIL

IM, C

UR

RE

NT

LIM

IT T

HR

ES

HO

LD(m

V)

5.0

5.2

5.4

5.6

5.8

6.0

−50 −25 0 25 50 75 100 125 150


PW

Mk,

PW

M V

OLT

AG

E G

AIN

(V

/V)

Figure 14. PWM Output Voltage Gain vs.Junction Temperature

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Figure 15. Oscillator CS Limit Voltage Gain vs.Junction Temperature

16

17

18

19

20

21

22

−50 −25 0 25 50 75 100 125 150


ISV

k, C

UR

RE

NT

LIM

IT V

OLT

AG

EG

AIN

(V

/V)

0.25

0.75

1.25

1.75

2.25

2.75

3.25

3.75

4.25

4.75

5.25

−50 −25 0 25 50 75 100 125 150


Figure 16. Oscillator Reference GeneratorOutput Voltage vs. Junction Temperature

RG

out,

RE

FE

RE

NC

E G

EN

ER

AT

OR

OU

TP

UT

VO

LTA

GE

(V

)

RGout1

RGout3

RGout2

RGout4

4.0

6.0

8.0

10

12

14

−50 −25 0 25 50 75 100 125 150


RS

NK

1, O

UTA

SIN

K D

RIV

ER

ES

ISTA

NC

E (�

)

Figure 17. OUTA Sink Resistance vs. JunctionTemperature

6.0

8.0

10

12

14

16

−50 −25 0 25 50 75 100 125 150

Figure 18. OUTA Source Drive Resistance vs.Junction Temperature


RS

RC

1, O

UTA

SO

UR

CE

RE

SIS

TAN

CE

(�

)

6.0

8.0

10

12

14

16

−50 −25 0 25 50 75 100 125 150

Figure 19. OUTB Sink Resistance vs.Junction Temperature


RS

NK

2, O

UT

B S

INK

DR

IVE

RE

SIS

TAN

CE

(�

)

VCC = 15 V

14

16

18

20

22

24

26

28

30

32

−50 −25 0 25 50 75 100 125 150


RS

RC

2, O

UT

B S

OU

RC

ER

ES

ISTA

NC

E (�

)

VCC = 15 VCI = 100 pF

Figure 20. OUTB Source Drive Resistance vs.Junction Temperature

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VO

UTA

(low

), O

UTA

LO

W V

OLT

AG

E(m

V)

Figure 21. OUTA Low Voltage vs. JunctionTemperature

60

80

100

120

140

160

−50 −25 0 25 50 75 100 125 150TJ, JUNCTION TEMPERATURE (°C)

Figure 22. OUTB Low Voltage vs. JunctionTemperature

VO

UT

B(L

OW

), O

UT

B L

OW

VO

LTA

GE

(mV

)

300

350

400

450

500

550

600

−50 −25 0 25 50 75 100 125 150

Figure 23. Non−Overlap Adjustable Delay vs.Junction Temperature


t del

ay, N

ON−

OV

ER

LAP

AD

JUS

TAB

LED

ELA

Y (

ns)

OUTB Rising to OUTA Falling

OUTA Rising to OUTB Falling

1

3

5

7

9

−50 −25 0 25 50 75 100 125 150

Figure 24. Non−Overlap Adjustable DelayMatching vs. Junction Temperature


t del

ay, N

ON−

OV

ER

LAP

AD

JUS

TAB

LED

ELA

Y M

AT

CH

ING

(%

)

200

220

240

260

280

300

−50 −25 0 25 50 75 100 125 150

Figure 25. Skip Synchronization to ac LineVoltage Threshold vs. Junction Temperature


VS

SK

IP(S

YN

C),

SK

IP S

YN

C T

O A

CLI

NE

VO

LTA

GE

TH

RE

SH

OLD

(m

V)

1.20

1.21

1.22

1.23

1.24

1.25

−50 −25 0 25 50 75 100 125 150


VS

SK

IP, S

KIP

VO

LTA

GE

TH

RE

SH

OLD

(V)

Figure 26. Skip Voltage Threshold vs. JunctionTemperature

30

50

70

90

110

130

−50 −25 0 25 50 75 100 125 150

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80

85

90

95

100

−50 −25 0 25 50 75 100 125 150

Figure 27. Skip Voltage Hysteresis vs.Junction Temperature


VS

SK

IP, S

KIP

VO

LTA

GE

HY

ST

ER

ES

IS(m

V)

680

705

730

755

780

−50 −25 0 25 50 75 100 125 150


I FB, F

EE

DB

AC

K P

ULL−

UP

CU

RR

EN

TS

OU

RC

E (�A

)

Figure 28. Feedback Pull−Up Current Sourcevs. Junction Temperature

5.2

5.4

5.6

5.8

6.0

6.2

−50 −25 0 25 50 75 100 125 150

VF

B(o

pen)

, FE

ED

BA

CK

OP

EN

CIR

CU

IT V

OLT

AG

E (

V)


Figure 29. Feedback Open Circuit Voltage vs.Junction Temperature

14.75

14.95

15.15

15.35

15.55

15.75

−50 −25 0 25 50 75 100 125 150


VC

C(o

n), S

TAR

TU

P T

HR

ES

HO

LD (

V)

Figure 30. Startup Threshold vs. JunctionTemperature

9.5

9.7

9.9

10.1

10.3

10.5

−50 −25 0 25 50 75 100 125 150

Figure 31. Minimum Operating Voltage vs.Junction Temperature

VC

C(o

ff), M

INIM

UM

OP

ER

AT

ING

VO

LTA

GE

(V

)


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Figure 32. Inhibit Threshold Voltage vs.Junction Temperature

650

700

750

800

850

900

950

1000

−50 −25 0 25 50 75 100 125 150


Vin

hibi

t, IN

HIB

IT T

HR

ES

HO

LDV

OLT

AG

E (

V)

250

270

290

310

330

350

−50 −25 0 25 50 75 100 125 150

I inhi

bit,

INH

IBIT

BIA

S C

UR

RE

NT

(�A

)


Figure 33. Inhibit Bias Current vs. JunctionTemperature

22.0

22.5

23.0

23.5

24.0

24.5

25.0

−50 −25 0 25 50 75 100 125 150

Vst

artu

p(m

in),

MIN

IMU

M S

TAR

TU

PV

OLT

AG

E (

V)


Figure 34. Minimum Startup Voltage vs.Junction Temperature

VCC = VCC − 0.5 VIstart = 0.5 mA

5.0

5.2

5.4

5.6

5.8

6.0

−50 −25 0 25 50 75 100 125 150


I sta

rt, S

TAR

TU

P C

UR

RE

NT

(m

A)

Figure 35. Startup Current vs. JunctionTemperature

10

15

20

25

30

−50 −25 0 25 50 75 100 125 150

Figure 36. Off−State Leakage Current vs.Junction Temperature


I HV

(off)

, OF

F−

STA

TE

LE

AK

AG

EC

UR

RE

NT

(�A

)

650

675

700

725

750

775

800

825

850

−50 −25 0 25 50 75 100 125 150


Figure 37. Supply Current Device Disabled(Overload) vs. Junction Temperature

I CC

1, S

UP

PLY

CU

RR

EN

T D

EV

ICE

DIS

AB

LED

(�A

)

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5.75

5.95

6.15

6.35

6.55

6.75

−50 −25 0 25 50 75 100 125 150


I CC

2, S

UP

PLY

CU

RR

EN

T D

EV

ICE

SW

ITC

HIN

G (

mA

)

Figure 38. Supply Current Device Switchingvs. Junction Temperature

100

120

140

160

180

200

−50 −25 0 25 50 75 100 125 150

Figure 39. Overload Timer vs. JunctionTemperature


t OV

LD, O

VE

RLO

AD

TIM

ER

(m

s)

4.5

4.7

4.9

5.1

5.3

5.5

−50 −25 0 25 50 75 100 125 150


VO

VLD

, OV

ER

LOA

D D

ET

EC

TT

HR

ES

HO

LD (

V)

Figure 40. Overload Detect Threshold vs.Junction Temperature

400

420

440

460

480

500

−50 −25 0 25 50 75 100 125 150

Figure 41. Brown−Out Detect Threshold vs.Junction Temperature


VB

O(lo

w),

BR

OW

N−

OU

T D

ET

EC

TT

HR

ES

HO

LD (

mV

)

600

610

620

630

640

650

−50 −25 0 25 50 75 100 125 150

VB

O(h

igh)

, BR

OW

N−

OU

T E

XIT

TH

RE

SH

OLD

(m

V)

Figure 42. Brown−Out Exit Threshold vs.Junction Temperature


160

165

170

175

180

−50 −25 0 25 50 75 100 125 150


VB

O(H

YS

), B

RO

WN−

OU

TH

YS

TE

RE

SIS

(m

V)

Figure 43. Brown−Out Hysteresis vs. JunctionTemperature

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900

920

940

960

980

1000

−50 −25 0 25 50 75 100 125 150

VLA

TC

H(lo

w),

LAT

CH

PU

LL−

DO

WN

VO

LTA

GE

TH

RE

SH

OLD

(m

V)

Figure 44. Latch Pull−Down Voltage Thresholdvs. Junction Temperature


VCC

−50 −25 0 25 50 75 100 125 1506.5

6.7

6.9

7.1

7.3

7.5


VLA

TC

H(lo

w_H

YS

), LA

TC

H P

ULL−

UP

TH

RE

SH

OLD

(V

)

Figure 45. Latch Pull−Up Threshold vs.Junction Temperature

6.5

6.7

6.9

7.1

7.3

7.5

−50 −25 0 25 50 75 100 125 150

Figure 46. Latch Pull−Up Voltage Thresholdvs. Junction Temperature


VLA

TC

H(lh

igh)

, LA

TC

H P

ULL−

UP

VO

LTA

GE

TH

RE

SH

OLD

(V

)

50

52

54

56

58

60

−50 −25 0 25 50 75 100 125 150


VLA

TC

H(d

elay

), LA

TC

H P

RO

PA

GA

TIO

ND

ELA

Y (�s)

Figure 47. Latch Propagation Delay vs.Junction Temperature

50

51

52

53

54

55

−50 −25 0 25 50 75 100 125 150

Figure 48. Latch Clamp Current vs. JunctionTemperature


I LA

TC

H(c

lam

p), L

AT

CH

CLA

MP

CU

RR

EN

T (�A

)

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3.0

3.1

3.2

3.3

3.4

3.5

−50 −25 0 25 50 75 100 125 150


VLA

TC

H(c

lam

p), L

AT

CH

CLA

MP

VO

LTA

GE

(V

)

Figure 49. Latch Clamp Voltage vs. JunctionTemperature

90

92

94

96

98

100

−50 −25 0 25 50 75 100 125 150


VLA

TC

H(s

hdn)

, LA

TC

H−

OF

F C

UR

RE

NT

SH

UT

DO

WN

(�A

)

Figure 50. Latch−Off Current Shutdown vs.Junction Temperature

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DETAILED DEVICE DESCRIPTION

IntroductionThe NCP1652 is a highly integrated controller combining

PFC and an isolated step down ac−dc power conversion ina single stage, resulting in a lower cost and reduced partcount solution. This controller is ideal for notebookadapters, battery chargers and other off−line applicationswith power requirements between 75 W and 150 W with anoutput voltage greater than 12 V. The single stage is basedon the flyback converter and it is designed to operate in CCMor DCM modes.

Power Factor Correction (PFC) IntroductionPower factor correction shapes the input current of

off−line power supplies to maximize the real poweravailable from the mains. Ideally, the electrical applianceshould present a load that emulates a pure resistor, in whichcase the reactive power drawn by the device is zero. Inherentin this scenario is the freedom from input current harmonics.The current is a perfect replica of the input voltage (usuallya sine wave) and is exactly in phase with it. In this case thecurrent drawn from the mains is at a minimum for the realpower required to perform the needed work, and thisminimizes losses and costs associated not only with thedistribution of the power, but also with the generation of thepower and the capital equipment involved in the process.The freedom from harmonics also minimizes interferencewith other devices being powered from the same source.

Another reason to employ PFC in many of today’s powersupplies is to comply with regulatory requirements. Today,electrical equipment in Europe must comply with theEuropean Norm EN61000−3−2. This requirement applies tomost electrical appliances with input power of 75 W orgreater, and it specifies the maximum amplitude ofline−frequency harmonics up to and including the 39th

harmonic. While this requirement is not yet in place in theUS, power supply manufacturers attempting to sell productsworldwide are designing for compliance with thisrequirement.

Typical Power Supply with PFCA typical power supply consists of a boost PFC

preregulator creating an intermediate �400 V bus and anisolated dc−dc converter producing the desired outputvoltage as shown in Figure 51. This architecture has twopower stages.

Figure 51. Typical Two Stage Power Converter

Rectifier&

Filter

PFCPreregulator

DC−DCConverter

with isolator

ACInput Vout

A two stage architecture allows optimization of eachindividual power stage. It is commonly used because of

designer familiarity and a vast range of availablecomponents. But, because it processes the power twice, thesearch is always on for a more compact and power efficientsolution.

The NCP1652 controller offers the convenience ofshrinking the front−end converter (PFC preregulator) andthe dc−dc converter into a single power processing stage asshown in Figure 52.

Figure 52. Single Stage Power Converter

Rectifier&

Filter

NCP1652 BasedSingle−Stage

Flyback Converter

ACInput Vout

This approach significantly reduces the component count.The NCP1652 based solution requires only one each ofMOSFET, magnetic element, output rectifier (low voltage)and output capacitor (low voltage). In contrast, the 2−stagesolution requires two or more of the above−listedcomponents. Elimination of certain high−voltagecomponents (e.g. high voltage capacitor and high voltagePFC diode) has significant impact on the system design. Theresultant cost savings and reliability improvement are oftenworth the effort of designing a new converter.

Single PFC StageWhile the single stage offers certain benefits, it is

important to recognize that it is not a recommended solutionfor all requirements. The following three limitations applyto the single stage approach:• The output voltage ripple will have a 2x line frequency

component (120 Hz for North American applications)that can not be eliminated easily. The cause of thisripple is the elimination of the energy storage elementthat is typically the boost output capacitor in the2−stage solution. The only way to reduce the ripple is toincrease the output filter capacitance. The requiredvalue of capacitance is inversely proportional to theoutput voltage – hence this approach is notrecommended for low voltage outputs such as 3.3 V or5 V. However, if there is a follow−on dc−dc converterstage or a battery after the single stage converter, thelow frequency ripple should not cause any concerns.

• The hold−up time will not be as good as the 2−stageapproach – again due to the lack of an intermediateenergy storage element.

• In a single stage converter, one FET processes all thepower – that is both a benefit and a limitation as thestress on that main MOSFET is relatively higher.Similarly, the magnetic component (flybacktransformer/inductor) can not be optimized as well as in

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the 2−stage solution. As a result, potentially higherleakage inductance induces higher voltage spikes (likethe one shown in Figure 53) on the MOSFET drain.This may require a MOSFET with a higher voltagerating compared to similar dc−input flybackapplications.

Figure 53. Typical Drain Voltage Waveform of aFlyback Main Switch

There are a few methods to clamp the voltage spike on themain switch, a resistor−capacitor−diode (RCD) clamp, atransient voltage suppressor (TVS) or an active clamp usinga MOSFET and capacitor can be used as shown inFigures 54 to 56.

R

RCDClamp

Vout

Figure 54. RCD Clamp

Vin

CD

TVS

TVSClamp

Vout

Figure 55. TVS Clamp

Vin

ActiveClamp

Vout

Figure 56. Active Clamp

Vin

The first two methods result in dissipation of the leakageenergy in the clamping circuits – the dissipation isproportional to LI2 where L is the leakage inductance of thetransformer and I is the peak of the switch current atturn−off. An RDC snubber is simple and has the lowest cost,but constantly dissipates power. A TVS provides goodvoltage clamping at a slightly higher cost and dissipatespower only when the drain voltage exceeds the voltagerating of the TVS.

The active clamp circuit provides an intriguing alternativeto the other methods. It requires addition of a MOSFET anda high voltage capacitor as part of the active clamp circuit,thus adding complexity, but it results in a complete reuse ofthe leakage inductance energy. As a result, the transformerconstruction is no longer critical and one can use cheapercost solution. Also, the active clamp circuit reduces thevoltage stress on the primary switch and that can lead tousage of lower cost or lower on resistance (RDS(on))MOSFET. Finally, the turn−on switching losses areeliminated because the active clamp circuit allows thedischarge of the MOSFET COSS capacitance prior to theturn−on. The energy stored in the leakage inductance isutilized for this transition.

In many applications, the added complexity of the activeclamp circuit may not be justified. However, the OUTB ofthe NCP1652 is also usable for another purpose,synchronous rectification control. Synchronousrectification for flyback converters is an emergingrequirement for flyback converters. The OUTB signal fromNCP1652 is ideal for interfacing with a secondary sidesynchronous rectifier controller such as NCP4303 as shownin Figure 57. As shown in Figure 57, using the OUTB(coupled through pulse transformer or Y−capacitor) as atrigger for the NCP4303 allows guaranteed turn−off of thesecondary side synchronous MOSFET prior to turn−on ofthe primary switch. In any CCM flyback converter, this is acritical requirement to prevent cross−conduction andNCP1652 and NCP4303 combination is the first suchchipset that guarantees the operation withoutcross−conduction.

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NCP4303TRIG

NCP1652

OUTB

OUTA

DRV

Figure 57. NCP1652 and NCP4302 based single stage PFC with synchronous rectification.

VIN VOUT

The NCP1652 incorporates a secondary driver, OUTB,with adjustable non overlap delay for controlling asynchronous rectifier switch in the secondary side, an activeclamp switch in the primary or both. In addition, thecontroller features a proprietary Soft−Skip™ to reduceacoustic noise at light loads. Other features found in theNCP1652 include a high voltage startup circuit, voltagefeedforward, brown out detector, internal overload timer,latch input and a high accuracy multiplier.

NCP1652 PFC LoopThe NCP1652 incorporates a modified version of average

current mode control used for achieving the unity powerfactor. The PFC section includes a variable referencegenerator, a low frequency voltage regulation erroramplifier (AC error AMP), ramp compensation (RampComp) and current shaping network. These blocks areshown in the lower portion of the bock diagram (Figure 51).

The inputs to the reference generator include feedbacksignal (FB), scaled AC input signal (AC_IN) andfeedforward input (VFF). The output of the referencegenerator is a rectified version of the input sine−wave scaledby the FB and VFF values. The reference amplitude isproportional to the FB and inversely proportional to thesquare of the VFF. This, for higher load levels and/or lowerinput voltage, the signal would be higher.

The function of the AC error amp is to force the averagecurrent output of the current sense amplifier to match thereference generator output. The output of the AC erroramplifier is compensated to prevent response to fast events.This output (Verror) is fed into the PWM comparator througha reference buffer. The PWM comparator sums the Verror andthe instantaneous current and compares it to a 4.0 Vthreshold to provide the desired duty cycle control. Ramp

compensation is also added to the input signal to allow CCMoperation above 50% duty cycle.

High Voltage Startup CircuitThe NCP1652 internal high voltage startup circuit

eliminates the need for external startup components andprovides a faster startup time compared to an externalstartup resistor. The startup circuit consists of a constantcurrent source that supplies current from the HV pin to thesupply capacitor on the VCC pin (CCC). The startup current(Istart) is typically 5.5 mA.

The OUTA and OUTB drivers are enabled and the startupcurrent source is disabled once the VCC voltage reachesVCC(on), typically 15.3 V. The controller is then biased bythe VCC capacitor. The drivers are disabled if VCC decays toits minimum operating threshold (VCC(off)) typically 10.3 V.Upon reaching VCC(off) the gate drivers are disabled. TheVCC capacitor should be sized such VCC is kept aboveVCC(off) while the auxiliary voltage is building up.Otherwise, the system will not start.

The controller operates in double hiccup mode while inoverload or VCC(off). A double hiccup fault disables thedrivers, sets the controller in a low current mode and allowsVCC to discharge to VCC(off). This cycle is repeated twice tominimize power dissipation in external components duringa fault event. Figure 58 shows double hiccup modeoperation. A soft−start sequence is initiated the second timeVCC reaches VCC(on). If the controller is latched uponreaching VCC(on), the controller stays in hiccup mode.During this mode, VCC never drops below VCC(reset), thecontroller logic reset level. This prevents latched faults to becleared unless power to the controller is completelyremoved (i.e. unplugging the supply from the AC line).

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Figure 58. VCC Double Hiccup Operation with a Fault Occurring while the Startup Circuit is Disabled

Fault Timer(internal)

OUTA

Overloadapplied

t

t

ttOVLD

VCC(off)

VCC(on)

VCC

An internal supervisory circuit monitors the VCC voltageto prevent the controller from dissipating excessive powerif the VCC pin is accidentally grounded. A lower levelcurrent source (Iinhibit) charges CCC from 0 V to Vinhibit,

typically 0.85 V. Once VCC exceeds Vinhibit, the startupcurrent source is enabled. This behavior is illustrated inFigure 59. This slightly increases the total time to chargeVCC, but it is generally not noticeable.

Figure 59. Startup Current at Various VCC Levels

The rectified ac line voltage is provided to the power stageto achieve accurate PFC. Filtering the rectified ac linevoltage with a large bulk capacitor distorts the PFC in asingle stage PFC converter. A peak charger is needed to bias

the HV pin as shown in Figure 60. Otherwise, the HV pinfollows the ac line and the startup circuit is disabled everytime the ac line voltage approaches 0 V. The VCC capacitoris sized to bias the controller during power up.

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NCP1652

HVOUTA

Peak Charger

Figure 60. Peak charger

VINVOUT

The startup circuit is rated at a maximum voltage of 500 V.Power dissipation should be controlled to avoid exceedingthe maximum power dissipation of the controller. Ifdissipation on the controller is excessive, a resistor can beplaced in series with the HV pin. This will reduce powerdissipation on the controller and transfer it to the seriesresistor.

Drive OutputsThe NCP1652 has out off phase output drivers with an

adjustable non−overlap delay (tD). The main output, OUTA,drives the primary MOSFET. The secondary output, OUTB,is designed to provide a logic signal used to control asynchronous rectification switch in the secondary side, anactive clamp switch in the primary or both. The outputs arebiased directly from VCC and their high state voltage isapproximately VCC.

OUTA has a source resistance of 13 � (typical) and a sinkresistance of 8.0 � (typical) OUTB has a source resistance22 � (typical) and a sink resistance of 10 � (typical). OUTBis a purposely sized smaller than OUTA because the gatecharge of an active switch or logic used with synchronousrectification is usually less than that of the primaryMOSFET. If a higher drive capability is required, an externaldiscrete driver can be used.

The drivers are enabled once VCC reaches VCC(on) andthere are no faults present. They are disabled once VCCdischarges to VCC(off). OUTB is always the last pulsegenerated when the outputs are disabled due to a fault(latch−off, VCC(off), overload, or brown−out). The last pulseterminates at the end of the clock cycle. This ensures theactive clamp capacitor is reset.

The high current drive capability of OUTA and OUTBmay generate voltage spikes during switch transitions due toparasitic board inductance. Shortening the connectionlength between the drivers and their loads and using widerconnections will reduce inductance−induce spikes.

Adjustable Dead TimeOUTA and OUTB have an adjustable dead time between

transitions to prevent simultaneous conduction of the mainand synchronous rectifier or active clamp MOSFETs. Thedelay is also used to optimize the turn−off transition of theactive clamp switch to achieve zero−volt switching of themain switch in an active clamp topology. Figure 61 showsthe timing relationship between OUTA and OUTB.

Figure 61. Timing relationship between OUTA andOUTB.

tdelay(lead)

OUTA

OUTB

tdelay(trail)

The dead time between OUTA and OUTB is adjusted byconnecting a resistor, RD, from the RD pin to ground. Theoverlap delay is proportional to RD. The delay time can beset between 80 ns and 1.8 �s using the formula:

tdelay(in ns) � 8.0 � Rdelay(in k�) with

Rdelay varying between 10 k� and 230 k�

AC Error Amplifier and BufferThe AC error amplifier (EA) shapes the input current into

a high quality sine wave by forcing the filtered input currentto follow the output of the reference generator. The outputof the reference generator is a full wave rectified ac signaland it is applied to the non inverting input of the EA. Thefiltered input current, Iin, is the current sense signal at the

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ISpos pin multiplied by the current sense amplifier gain. Itis applied to the inverting input of the AC EA.

The AC EA is a transconductance amplifier. Atransconductance amplifier generates an output currentproportional to its differential input voltage. This amplifierhas a nominal gain of 100 �S (or 0.0001 A/V). That is, aninput voltage difference of 10 mV causes the output currentto change by 1.0 �A. The AC EA has typical source and sinkcurrents of 70 �A.

The filtered input current is a high frequency signal. A lowfrequency pole forces the average input current to follow the

reference generator output. A pole-zero pair is created byplacing a (RCOMP) and capacitor (CCOMP) seriescombination at the output of the AC EA. The AC COMP pinprovides access to the AC EA output.

The output of the AC EA is inverted and converted into acurrent using a second transconductance amplifier. Theoutput of the inverting transconductance amplifier isVACEA(buffer). Figure 62 shows the circuit schematic of theAC EA buffer. The AC EA buffer output current, IACEA(out),is given by Equation 1.

AC COMP

AC erroramplifier

gm

−

+

−

+

37.33k�

−

+

VDD

21.33k�

x 4

2.8V

+To PWM

comparator

gm = 100�S

Figure 62. AC EA Buffer Amplifier

VAC_REF

RIAVG

IAVG

RAC_COMP

IACEA(out)

IACEA(out) � 2.8 � VACEA

37.33k � 4 (eq. 1)

The voltage at the PWN non-inverting input is determinedby IACEA(out), the instantaneous switch current along and theramp compensation current. OUTA is terminated once thevoltage at the PWM non-inverting input reaches 4 V.

Current Sense AmplifierA voltage proportional to the main switch current is

applied to the current sense input, ISPOS. The current sense

amplifier is a wide bandwidth amplifier with a differentialinput. The current sense amplifier has two outputs, PWMOutput and IAVG Output. The PWM Output is theinstantaneous switch current which is filtered by the internalleading edge blanking (LEB) circuitry prior to applying it tothe PWM Comparator non inverting input. The secondoutput is a filtered current signal resembling the averagevalue of the input current. Figure 63 shows the internalarchitecture of the current sense amplifier.

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−

+tLEB

blanking

tLEB

blanking Inst. current B

Inst. current A

Current senseamplifier

gm = 250�STo PWM

comparator

To PWM skip

comparator

To AC error

amplifier

Figure 63. Current Sense Amplifier

VIAVG

RIAVG

RCS

gm

IAVG

Ispos

Ip

Caution should be exercised when designing a filterbetween the current sense resistor and the ISPOS input, dueto the low impedance of this amplifier. Any series resistancedue to a filter creates a voltage offset (VOS) due to its inputbias current, CAIbias. The input bias current is typically60 �A. The voltage offset is given by Equation 2.

VOS � CAIbias � Rexternal (eq. 2)

The offset adds a positive offset to the current sense signal.The ac error amplifier will then try to compensate for theaverage output current which appears never to go to zero andcause additional zero crossing distortion.

A voltage proportional to the main switch current isapplied to the ISPOS pin. The ISPOS pin voltage is convertedinto a current, i1, and internally mirrored. Two internalcurrents are generated, ICS and IAVG. ICS is a high frequencysignal which is a replica of the instantaneous switch current.IAVG is a low frequency signal. The relationship betweenVISPOS and ICS and IAVG is given by Equation 3.

ICS � IIN �VISPOS

4k(eq. 3)

The PWM Output delivers current to the positive input ofthe PWM input where it is added to the AC EA and rampcompensation signal.

The IAVG Output generates a voltage signal to a bufferamplifier. This voltage signal is the product of IAVG and anexternal RIAVG resistor filtered by the capacitor on the IAVGpin, CIAVG. The pole frequency, fP, set by CIAVG should besignificantly below the switching frequency to remove thehigh frequency content. But, high enough to not to causesignificant distortion to the input full wave rectifiedsinewave waveform. A properly filtered average currentsignal has twice the line frequency. Equation 4 shows therelationship between CIAVG (in nF) and fP (in kHz).

CIAVG �1

2 � � � RIAVG � fP(eq. 4)

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The gain of the low frequency current buffer is set by theresistor at the IAVG pin, RIAVG. RIAVG sets the scaling factorbetween the primary peak and primary average currents.The gain of the current sense amplifier, ACA, is given byEquation 5.

ACA �RIAVG

4k(eq. 5)

The current sense signal is prone to leading edge spikesduring the main switch turn on due to parasitic capacitanceand inductance. This spike may cause incorrect operation ofthe PWM Comparator. Filtering the current sense signal willinevitably change the shape of the current pulse. TheNCP1652 incorporates LEB circuitry to block the first200 ns (typical) of each current pulse. This removes theleading edge spikes without altering the current signalwaveform.

OscillatorThe oscillator controls the switching frequency, f, the jitter

frequency and the gain of the multiplier. The oscillator rampis generated by charging the timing capacitor on the CT Pin,CT, with a 200 �A current source. This current source istightly controlled during manufacturing to achieve acontrolled and repeatable oscillator frequency. The currentsource turns off and CT is immediately discharged with apull down transistor once the oscillator ramp reaches its peakvoltage, VCT(peak), typically 4.0 V. The pull down transistorturns off and the charging current source turns on once theoscillator ramp reaches its valley voltage, VCT(valley).Figure 64 shows the resulting oscillator ramp and controlcircuitry.

−

+

To PWM

comparator

To PWM skip

comparator

VDD

VDD

x 1.2

4.0 V / 0.1 V

+

− +

Oscillator

Figure 64. Oscillator Ramp and Control Circuitry

IAVG

RIAVG

CT

CT

The relationship between the oscillator frequency in kHzand timing capacitor in pF is given by Equation 6.

CT �47000

f (eq. 6)

A low frequency oscillator modulates the switchingfrequency, reducing the controller EMI signature andallowing the use of a smaller EMI filter. The frequencymodulation or jitter is typically ±5% of the oscillatorfrequency.

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Output OverloadThe Feedback Voltage, VFB, is directly proportional to the

output power of the converter. An internal 6.7 k� resistorpulls−up the FB voltage to the internal 6.5 V reference. Anexternal optocoupler pulls down the FB voltage to regulatethe output voltage of the system. The optocoupler is offduring power up and output overload conditions allowingthe FB voltage to reach its maximum level.

The NCP1652 monitors the FB voltage to detect anoverload condition. A typical startup time of a single PFCstage converter is around 100 ms. If the converter is out ofregulation (FB voltage exceeds 5.0 V) for more that 150 ms(typical) the drivers are disabled and the controller enters thedouble hiccup mode to reduce the average powerdissipation. A new startup sequence is initiated after thedouble hiccup is complete. This protection feature is criticalto reduce power during an output short condition.

Soft−Skip™ Cycle ModeThe FB voltage reduces as the output power demand of the

converter reduces. Once VFB drops below the skipthreshold, VSSKIP, 1.30 V (typical) the drivers are disabled.The skip comparator hysteresis is typically 180 mV.

The converter output voltage starts to decay because noadditional output power is delivered. As the output voltagedecreases the feedback voltage increases to maintain theoutput voltage in regulation. This mode of operation isknown as skip mode. The skip mode frequency is dependentof load loop gain and output capacitance and can createaudible noise due to mechanical resonance in thetransformer and snubber capacitor. A proprietarySoft−Skip™ mode reduces audible noise by slowlyincreasing the primary peak current until it reaches itsmaximum value. The minimum skip ramp period, tSSKIP, is2.5 ms. Figure 65 shows the relationship between VFB,VSSKIP and the primary current.

Figure 65. Soft−Skip� operation.

Skip mode operation is synchronous of the ac line voltage.The NCP1652 disables Soft−Skip™ when the rectified acline voltage drops to its valley level. This ensures theprimary current always ramp up reducing audible noise. Askip event occurring as the ac line voltage is decreasing,causes the primary peak current to ramp down instead oframp up. Once the skip period is over the primary current isonly determined by the ac line voltage. A Soft−Skip™ eventterminates once the AC−IN pin voltage decreases below

260 mV. A new Soft−Skip™ period starts once the voltageon the AC−IN pin increases to 260 mV.

An increase in output load current terminates aSoft−Skip™ event. A transient load detector terminates aSoft−Skip™ period once VFB voltage exceeds VSSKIP bymore than 550 mV. This ensures the required output poweris delivered during a load transient and the output voltagedoes not fall out of regulation. Figure 66 shows therelationship between Soft−Skip™ and the transient loaddetector.

Figure 66. Load transient during Soft−Skip�

VSSKIP

VFB

The output of the Soft−Skip™ Comparator is or−ed withthe PWM Comparator output to control the duty ratio. TheSoft−Skip™ Comparator controls the duty ratio in skipmode and the PWM Comparator controls the duty cycleduring normal operation. In skip mode, the non−invertinginput of the Soft−Skip™ Comparator exceeds 4 V, disablingthe drivers. As the FB voltage increases, the voltage at thenon−inverting input is ramp down from 4 V to 0.2 V toenable the drivers.

Multiplier and Reference GeneratorThe NCP1652 uses a multiplier to regulate the average

output power of the converter. This controller uses aproprietary concept for the multiplier used within thereference generator. This innovative design allows greatlyimproved accuracy compared to a conventional linearanalog multiplier. The multiplier uses a PWM switchingcircuit to create a scalable output signal, with a very welldefined gain.

The output of the multiplier is the ac-reference signal. Theac-reference signal is used to shape the input current. Themultiplier has three inputs, the error signal from an externalerror amplifier (VFB), the full wave rectified ac input(AC_IN) and the feedforward input (VFF).

The FB signal from an external error amplifier circuit isapplied to the VFB pin via an optocoupler or other isolationcircuit. The FB voltage is converted to a current with a V-I

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converter. There is no error in the output signal due to theseries rectifier as shown in Figure 67.

The scaled version of the full wave rectified input ac waveis applied to the AC_IN pin by means of a resistive voltagedivider. The multiplier ramp is generated by comparing thescaled line voltage to the oscillator ramp with the AC_INComparator. The current signal from the V-I converter is

factored by the AC_IN comparator output. The resultingsignal is filtered by the low pass R-C filter on the CM pin.The low pass filter removes the high frequency content. Thegain of the multiplier is determined by the V-I converter, theresistor on the CM pin, and the peak and valley voltages ofthe oscillator sawtooth ramp.

AC IN

−

+

Multiplier

V−to−I

FB

CM

Square

Divide AC_REF

Oscillator

Figure 67. Reference Generator

VAC_REF � k �

VFB � VAC_IN

VFF2

VFF2

VFF

The third input to the reference generator is the VFF signal.The VFF signal is a dc voltage proportional to the ac linevoltage. A resistive voltage divider attenuates the full waverectified line voltage between 0.7 and 5.0 V. The full waverectified line is then averaged with a capacitor. The acaverage voltage must be constant over each half cycle of theline. Line voltage ripple (120 Hz or 100 Hz) ripple on theVFF signal adds ripple to the output of the multiplier. Thiswill distort the ac reference signal and reduce the powerfactor and increase the line current distortion. Excessivefiltering delays the feedforward signal reducing the linetransient response. A good starting point is to set the filtertime constant to one cycle of the line voltage. The user canthen optimize the filter for line transient response versuspower factor. The average voltage on the VFF pin is:

VFF �2�

Vac 2��(eq. 7)

Where, � is the voltage divider ratio, normally 0.01.

VAC_REF �VFB � VAC_IN

VFF2

� k(eq. 8)

The multiplier transfer function is given by Equation 8.The output of the multiplier is the AC_REF. It connects tothe AC Error Amplifier.

where, k is the reference generator gain, typically 0.55. Theoutput of the reference generator is clamped at 4.5 V to limitthe maximum output power.

Feedforward maintains a constant input powerindependent of the line voltage. That is, for a given FBvoltage, if the line voltage doubles (AC_IN), thefeedforward term quadruples and reduces the output of theerror amplifier in half to maintain the same input power.

AC Error Amplifier CompensationA pole-zero pair is created by placing a series combination

of RCOMP and CCOMP at the output of the AC error amplifier(EA). The value of the compensation components is

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dependent of the average input current and the instantaneousswitch current. The gain of the average input current or slowloop is given by Equation 9.

ALF � RIAVG

4k � gm � RAC_COMP

� (2.286) (eq. 9)

The low frequency gain is the product of the current senseaveraging circuit, the transconductance amplifier and thegain of the AC error amplifier.

A current proportional to the instantaneous current isgenerated using a 4 k� resistor in the current sense amplifierinput. This proportional current is applied to a 21.33 k� atthe PWM comparator input to generate a current sensevoltage signal. The high frequency or fast loop gain, AHF, iscalculated using Equation 10.

AHF �21.33k

4k� 5.333

(eq. 10)

Equation 11 shows system stability requirements. That is,the low frequency gain has to be less than one half of the highfrequency gain.

RIAVG

4k � gm � RAC_COMP

� (2.286) �5.333

2(eq. 11)

Equation 12 is obtained by re-arranging Equation 11 forRAC_COMP. This equation provides the maximum value forRAC_COMP.

RAC_COMP �4666

RIAVG � gm(eq. 12)

The control loop zero, fZ, is calculated using Equation 13.The control loop zero should be set at approximately at1/10th of the oscillator frequency, fOSC. The compensationcapacitor is calculated using Equation 14.

fz �1

2� � CAC_COMP � RAC_COMP

(eq. 13)

CAC_COMP �1

2� �fOSC

10� RAC_COMP

(eq. 14)

Current Sense ResistorThe PFC stage has two control loops. The first loop

controls the average input current and the second loopcontrols the instantaneous current across the main switch.The current sense signal affects both loops. The currentsense signal is fed into the positive input of the erroramplifier to control the average input current. In addition,the current sense information together with the rampcompensation and error amplifier signal control theinstantaneous primary peak current.

The primary peak current, IPK, is calculated usingEquation 15,

IPK �2� � Pout

� � Vin(LL) � D

Vin(LL) � ton

0.88 � 2 � LP

(eq. 15)

where, Vin(LL) is the low line ac input voltage, D is the dutyratio, Pout is the output power, Pin is the input power, � is theefficiency, LP is the primary inductance and ton is the ontime. Typical efficiency for this topology is around 88%.

The current sense resistor is selected to achieve maximumsignal resolution at the input of the ac reference amplifier.The maximum voltage input of the ac reference amplifier toprevent saturation is 4.5 V. This together with theinstantaneous peak current is used to calculate the currentsense resistor, RCS, using Equation 16.

RCS � 4.54k � Vin(LL) � D

RIAVG � Pin � 2�(eq. 16)

Ramp CompensationSubharmonic oscillations are observed in peak

current-mode controllers operating in continuousconduction mode with a duty ratio greater than 50%.Injecting a compensation ramp on the current sense signaleliminates the subharmonic oscillations. The amount ofcompensation is system dependent and it is determined bythe inductor falling di/dt.

The NCP1652 has built in ramp compensation to facilitatesystem design. The amount of ramp compensation is set bythe user with a resistor, RRCOMP, between the Ramp Comppin and ground. The Ramp Comp pin buffers the oscillatorramp generated on the CT pin. The current across RRCOMPis internally mirrored with a 1:1.2 ratio. The inverted ac erroramplifier and the instantaneous switch current signals areadded to the ramp compensation mirrored current. Theresulting current signal is applied to an internal 21.33 k�between the PWM Comparator non inverting input andground as shown in Figure 64.

The maximum voltage contribution of the rampcompensation signal to the error signal, VRCOMP, is given byEquation 17.

VRCOMP �(1.2) � VCT(peak)

� (21.33k)

RRCOMP

�102.38k

RRCOMP

(eq. 17)

where, VCT(peak) is the oscillator ramp peak voltage,typically 4.0 V.

For proper ramp compensation, the ramp signal shouldmatch the falling di/dt (which has been converted to a dv/dt)of the inductor at 50% duty cycle. Both the falling di/dt andoutput voltage need to be reflected by the transformer turnsratio to the primary side. Equations 18 through 23 assist inthe derivation of equations for RCS and RCOMP.

di

dtsecondary

�Vout

LS

�Vout

LP

� NP

NS

2

(eq. 18)

di

dtprimary

�di

dtsecondary

�NS

NP

�Vout

LP

NP

NS

(eq. 19)

NCP1652, NCP1652A

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VRCOMP �di

dtprimary

� T � RCS � AHF(eq. 20)

RCS �NS

NP

�LP � 102.38k

T � AHF � Vout � RRCOMP

(eq. 21)

At low line and full load, the output of the ac erroramplifier output is nearly saturated in a low state. While theac error amplifier output is saturated, IACEA is zero and doesnot contribute to the voltage across the internal 21.33 k�resistor on the PWM comparator non-inverting input. In thisoperation mode, the voltage across the 21.33 k� resistor isdetermined solely by the ramp compensation and theinstantaneous switch current as given by Equation 22.

Vref(PWM) � VRCOMP �ton

T VINST

(eq. 22)

The voltage reference of the PWM Comparator,VREF(PWM), is 4 V. For these calculations, 3.8 V is used toprovide some margin. The maximum instantaneous switchcurrent voltage contribution, VINST, is given byEquation 23.

VINST � IPK � RCS � AHF (eq. 23)

Substituting Equation 23 in Equation 22, settingVREF(PWM) at 3.8 V (provides margin) and solving forRRCOMP, Equation 24 is obtained.

RRCOMP �102.38k

3.8 � 5.333 � IPK � RCS�

ton

T(eq. 24)

Replacing Equation 24 in Equation 21 we obtain:

RCS �3.8

NPNS

�AHF�Vout�ton

LP 5.333 IPK

(eq. 25)

PWM LogicThe PWM and logic circuits are comprised of a PWM

comparator, an RS flip-flop (latch) and an OR gate. The

latch is Set dominant which means that if both R and S arehigh the S signal will dominate and Q will be high, whichwill hold the power switch off.

The NCP1652 uses a pulse width modulation schemebased on a fixed frequency oscillator. The oscillatorgenerates a voltage ramp as well as a pulse in sync with thefalling edge of the ramp. The pulse is an input to the PWMLogic and Driver block. While the oscillator pulse is present,the latch is reset, and the output drive is in its low state. Onthe falling edge of the pulse, the OUTA goes high and thepower switch begins conduction.

The instantaneous inductor current is summed with acurrent proportional to the ac error amplifier output voltage.This complex waveform is compared to the 4 V referencesignal on the PWM comparator inverting input. When thesignal at the non-inverting input to the PWM comparatorexceeds 4 V, the output of the PWM comparator toggles toa high state which drives the Set input of the latch and turnsthe power switch off until the next clock cycle.

Brown−OutThe NCP1652 incorporates a brown−out detection circuit

to prevent the controller operate at low ac line voltages andreduce stress in power components. A scaled version of therectified line voltage is applied to the VFF Pin by means ofa resistor divider. This voltage is used by the brown outdetector.

A brown−out condition exists if the feedforward voltageis below the brown−out exit threshold, VBO(high), typically0.45 V. The brown−out detector has 180 mV hysteresis. Thecontroller is enabled once VFF is above 0.63 V and VCCreaches VCC(on). OUTB is the last drive pulse. Figure 68shows the relationship between the brown−out, VCC, OUTAand OUTB signals.

NCP1652, NCP1652A

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t

t

t

t

OUTA

OUTB

VBO(low)

VBO(high)

VCC(off)

VCC(on)

VCC

VFF

Brown−Out

Last OUTB Pulase

Figure 68. Relationship Between the Brown−Out, VCC, OUTA and OUTB

Latch−Off

S

RQ

blanking

Reset

Latch

−

+

Vlatch(high)

−

+

VDD OVP comparator

OTP comparator

I latch(shdn)

Ilatch(clamp)

+

+

Vaux or VCC

NTC

Figure 69.

tlatch(delay)

Vlatch(low)

Vlatch(clamp)

Latch InputThe NCP1652 has a dedicated latch input to easily latch

the controller during overtemperature and overvoltagefaults (See Figure 69). The controller is latched if theLatch−Off pin voltage is pulled below 1 V or above 6.5 V.

Once the controller is latched, OUTA is disabled and OUTBgenerates a final pulse that ends with the oscillator period.No more pulses are generated after OUTB is terminated.Figure 70 shows the relationship between the Latch−Off,VCC, OUTA and OUTB signals.

NCP1652, NCP1652A

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t

t

t

t

Figure 70. Relationship Between the Latch−Off, VCC, OUTA and OUTB

OUTA

OUTB

Vlatch(high)

Vlatch(low)

VCC(off)

VCC(on)

VCC

Latch−Off

Latch−Off

Last OUTB Pulase

Latch−Off

The Latch−Off pin is clamped at 3.5 V. A 50 �A (typical)pull−up current source is always on and a 100 �A (typical)pull−down current source is enabled once the Latch−Off pinvoltage reaches 3.5 V (typical). This effectively clamps theLatch−Off pin voltage at 3.5 V. A minimum pull−up orpull−down current of 50 �A is required to overcome theinternal current sources and latch the controller. The

Latch−Off input features a 50 �s (typical) filter to preventlatching the controller due to noise or a line surge event.

The startup circuit continues to cycle VCC betweenVCC(on) and VCC(off) while the controller is in latch mode.The controller exits the latch mode once power to the systemis removed and VCC drops below VCC(reset).

APPLICATION INFORMATION

ON Semiconductor provides an electronic design tool,facilitate design of the NCP1652 and reduce developmentcycle time. The design tool can be downloaded atwww.onsemi.com.

The electronic design tool allows the user to easilydetermine most of the system parameters of a single PFCstage The tool evaluates the power stage as well as thefrequency response of the system.

ORDERING INFORMATION

Device Package Shipping†

NCP1652DWR2G SO−20 WB(Pb−Free)

1000 / Tape & Reel

NCP1652DR2G SO−16(Pb−Free)

2500 / Tape & Reel

NCP1652ADR2G SO−16(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

The products described herein (NCP1652), may be covered by one or more of the following U.S. patents; 6,373,734. There may be other patents pending.

SOIC−16CASE 751B−05

ISSUE KDATE 29 DEC 2006SCALE 1:1

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATINGPLANE

F

JM

R X 45�

G

8 PLP−B−

−A−

M0.25 (0.010) B S

−T−

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019

� � � �

6.40

16X0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

STYLE 1:PIN 1. COLLECTOR

2. BASE3. EMITTER4. NO CONNECTION5. EMITTER6. BASE7. COLLECTOR8. COLLECTOR9. BASE

10. EMITTER11. NO CONNECTION12. EMITTER13. BASE14. COLLECTOR15. EMITTER16. COLLECTOR

STYLE 2:PIN 1. CATHODE

2. ANODE3. NO CONNECTION4. CATHODE5. CATHODE6. NO CONNECTION7. ANODE8. CATHODE9. CATHODE

10. ANODE11. NO CONNECTION12. CATHODE13. CATHODE14. NO CONNECTION15. ANODE16. CATHODE

STYLE 3:PIN 1. COLLECTOR, DYE #1

2. BASE, #13. EMITTER, #14. COLLECTOR, #15. COLLECTOR, #26. BASE, #27. EMITTER, #28. COLLECTOR, #29. COLLECTOR, #3

10. BASE, #311. EMITTER, #312. COLLECTOR, #313. COLLECTOR, #414. BASE, #415. EMITTER, #416. COLLECTOR, #4

STYLE 4:PIN 1. COLLECTOR, DYE #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. COLLECTOR, #36. COLLECTOR, #37. COLLECTOR, #48. COLLECTOR, #49. BASE, #4

10. EMITTER, #411. BASE, #312. EMITTER, #313. BASE, #214. EMITTER, #215. BASE, #116. EMITTER, #1

STYLE 5:PIN 1. DRAIN, DYE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. DRAIN, #36. DRAIN, #37. DRAIN, #48. DRAIN, #49. GATE, #4

10. SOURCE, #411. GATE, #312. SOURCE, #313. GATE, #214. SOURCE, #215. GATE, #116. SOURCE, #1

STYLE 6:PIN 1. CATHODE

2. CATHODE3. CATHODE4. CATHODE5. CATHODE6. CATHODE7. CATHODE8. CATHODE9. ANODE

10. ANODE11. ANODE12. ANODE13. ANODE14. ANODE15. ANODE16. ANODE

STYLE 7:PIN 1. SOURCE N‐CH

2. COMMON DRAIN (OUTPUT)3. COMMON DRAIN (OUTPUT)4. GATE P‐CH5. COMMON DRAIN (OUTPUT)6. COMMON DRAIN (OUTPUT)7. COMMON DRAIN (OUTPUT)8. SOURCE P‐CH9. SOURCE P‐CH

10. COMMON DRAIN (OUTPUT)11. COMMON DRAIN (OUTPUT)12. COMMON DRAIN (OUTPUT)13. GATE N‐CH14. COMMON DRAIN (OUTPUT)15. COMMON DRAIN (OUTPUT)16. SOURCE N‐CH

16

8 9

8X

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42566BDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1SOIC−16

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−20 WBCASE 751D−05

ISSUE HDATE 22 APR 2015

SCALE 1:1

20

1

11

10

b20X

H

cL

18X A1

A

SEATINGPLANE

�

hX

45�

E

D

M0.

25M

B

M0.25 SA SBT

eT

B

A

DIM MIN MAXMILLIMETERS

A 2.35 2.65A1 0.10 0.25b 0.35 0.49c 0.23 0.32D 12.65 12.95E 7.40 7.60e 1.27 BSCH 10.05 10.55h 0.25 0.75L 0.50 0.90� 0 7

NOTES:1. DIMENSIONS ARE IN MILLIMETERS.2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF BDIMENSION AT MAXIMUM MATERIALCONDITION.

� �

XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotYY = YearWW = Work WeekG = Pb−Free Package

GENERICMARKING DIAGRAM*

20

1

XXXXXXXXXXXXXXXXXXXXXX

AWLYYWWG

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.

11.00

20X0.52

20X1.30

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*RECOMMENDED

10

20 11

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42343BDOCUMENT NUMBER:

DESCRIPTION:

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PAGE 1 OF 1SOIC−20 WB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliatesand/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to anyproducts or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its productsand applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications informationprovided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systemsor any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. ShouldBuyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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ncp1652 - controller, pfc, high efficiency, single stage

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