1FEATURES

3

2

4

51NC VCC

Y

A

GND

DBV PACKAGE(TOP VIEW)

DCK PACKAGE(TOP VIEW)

3

2

4

51NC VCC

Y

A

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

A Y2 4

SN74LVC1G17-Q1

www.ti.com ........................................................................................................................................................ SCES663A–MARCH 2006–REVISED APRIL 2008

SINGLE SCHMITT-TRIGGER BUFFER

• Qualified for Automotive Applications • ±24-mA Output Drive at 3.3 V• Supports 5-V VCC Operation • Ioff Supports Partial-Power-Down Mode

Operation• Inputs Accept Voltages to 5.5 V

This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G17-Q1 contains one buffer and performs the Boolean function Y = A. The device functions asan independent buffer, but because of Schmitt action, it may have different input threshold levels forpositive-going (VT+) and negative-going (VT–) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION (1)

TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (3)

SOT (SOT-23) – DBV Reel of 3000 SN74LVC1G17QDBVRQ1 C17_–40°C to 125°C

SOT (SC-70) – DCK Reel of 3000 SN74LVC1G17QDCKRQ1 C7_

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

FUNCTION TABLEINPUT A OUTPUT Y

H HL L

LOGIC DIAGRAM (POSITIVE LOGIC)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2006–2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

Absolute Maximum Ratings (1)

Recommended Operating Conditions (1)

SN74LVC1G17-Q1

SCES663A–MARCH 2006–REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNITVCC Supply voltage range –0.5 6.5 VVI Input voltage range (2) –0.5 6.5 VVO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 VVO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA

Continuous current through VCC or GND ±100 mADBV package 206

θJA Package thermal impedance (4) °C/WDCK package 252

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.

MIN MAX UNITOperating 1.65 5.5

VCC Supply voltage VData retention only 1.5

VI Input voltage 0 5.5 VVO Output voltage 0 VCC V

VCC = 1.65 V –4VCC = 2.3 V –8

IOH High-level output current –16 mAVCC = 3 V

–24VCC = 4.5 V –32VCC = 1.65 V 4VCC = 2.3 V 8

IOL Low-level output current 16 mAVCC = 3 V

24VCC = 4.5 V 32Human-Body Model 2 (H2)

kVESD rating Charged-Device Model 1 (C5)

Machine Model 200 (M3) VTA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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Product Folder Link(s): SN74LVC1G17-Q1

Electrical Characteristics

SN74LVC1G17-Q1

www.ti.com ........................................................................................................................................................ SCES663A–MARCH 2006–REVISED APRIL 2008

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT1.65 V 0.64 1.252.3 V 1 1.68Positive-going

VT+ input threshold 3 V 1.36 2.04 Vvoltage 4.5 V 2.07 2.86

5.5 V 2.53 3.431.65 V 0.23 0.712.3 V 0.44 1.05Negative-going

VT– input threshold 3 V 0.77 1.35 Vvoltage 4.5 V 1.22 2.09

5.5 V 1.73 2.521.65 V 0.26 0.742.3 V 0.33 0.92

HysteresisΔVT 3 V 0.4 0.99 V(VT+ – VT–)4.5 V 0.45 1.285.5 V 0.56 1.32

IOH = –100 µA 1.65 V to 4.5 V VCC – 0.1IOH = –4 mA 1.65 V 1.2IOH = –8 mA 2.3 V 1.9

VOH VIOH = –16 mA 2.4

3 VIOH = –24 mA 2.3IOH = –32 mA 4.5 V 3.8IOL = 100 µA 1.65 V to 4.5 V 0.1IOL = 4 mA 1.65 V 0.45IOL = 8 mA 2.3 V 0.4

VOL VIOL = 16 mA 0.5

3 VIOL = 24 mA 0.7IOL = 32 mA 4.5 V 0.7

II A input VI = 5.5 or GND 0 to 5.5 V ±10 µAIoff VI or VO = 5.5 V 0 ±25 µAICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 20 µAΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µACi VI = VCC or GND 3.3 V 4.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): SN74LVC1G17-Q1

Switching Characteristics

Operating Characteristics

SN74LVC1G17-Q1

SCES663A–MARCH 2006–REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com

over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 1)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 VFROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 VPARAMETER UNIT(INPUT) (OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAXtpd A Y 2.8 14 1 9 1.5 8 0.7 7 ns

TA = 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 VPARAMETER TEST CONDITIONS UNIT

TYP TYP TYP TYPCpd Power dissipaton capacitance f = 10 MHz 20 21 22 26 pF

4 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated

Product Folder Link(s): SN74LVC1G17-Q1

PARAMETER MEASUREMENT INFORMATION

VM

thtsu

From OutputUnder Test

CL(see Note A)

LOAD CIRCUIT

S1VLOAD

Open

GND

RL

RL

Data Input

Timing InputVI

0 V

VI

0 V0 V

tw

Input

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VI

0 VInput

OutputWaveform 1S1 at VLOAD(see Note B)

OutputWaveform 2

S1 at GND(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH − V∆

≈0 V

VI

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHLtPLZ/tPZLtPHZ/tPZH

OpenVLOADGND

TEST S1

NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. tPLH and tPHL are the same as tpd.H. All parameters and waveforms are not applicable to all devices.

OutputControl

VM VM

VM VM

VM VM

VM

VM VM

VM

VM

VM

VI

VM

VM

1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V5 V ± 0.5 V

1 kΩ500 Ω500 Ω500 Ω

VCC RL

2 × VCC2 × VCC

6 V2 × VCC

VLOAD CL

30 pF30 pF50 pF50 pF

0.15 V0.15 V0.3 V0.3 V

V∆

VCCVCC3 VVCC

VI

VCC/2VCC/21.5 VVCC/2

VMtr/tf

≤2 ns≤2 ns

≤2.5 ns≤2.5 ns

INPUTS

SN74LVC1G17-Q1

www.ti.com ........................................................................................................................................................ SCES663A–MARCH 2006–REVISED APRIL 2008

Figure 1. Load Circuit and Voltage Waveforms

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): SN74LVC1G17-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

SN74LVC1G17QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 C17O

SN74LVC1G17QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 C7O

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC1G17-Q1 :

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

• Catalog: SN74LVC1G17

• Enhanced Product: SN74LVC1G17-EP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74LVC1G17QDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

SN74LVC1G17QDCKRQ1 SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC1G17QDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0

SN74LVC1G17QDCKRQ1 SC70 DCK 5 3000 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

TYP0.220.08

0.25

3.02.6

2X 0.95

1.9

1.45 MAX

TYP0.150.00

5X 0.50.3

TYP0.60.3

TYP80

1.9

A

3.052.75

B1.751.45

(1.1)

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.

0.2 C A B

1

34

5

2

INDEX AREAPIN 1

GAGE PLANE

SEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAXARROUND

0.07 MINARROUND

5X (1.1)

5X (0.6)

(2.6)

(1.9)

2X (0.95)

(R0.05) TYP

4214839/C 04/2017

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:15X

PKG

1

3 4

5

2

SOLDER MASKOPENINGMETAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.6)

(1.9)

2X(0.95)

5X (1.1)

5X (0.6)

(R0.05) TYP

SOT-23 - 1.45 mm max heightDBV0005ASMALL OUTLINE TRANSISTOR

4214839/C 04/2017

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:15X

SYMM

PKG

1

3 4

5

2

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