1

Nanometer CMOS: an analog challenge!

IEEE Distinguished LecturesFort Collins May 11, 2006:

Marcel Pelgrom

Philips Research LaboratoriesProf. Holstlaan 4 (HTC-5)

5656 AE Eindhoven, The Netherlandsmarcel.pelgrom@philips.com

1 km21 km2 = 4 months of production=

70.000.000.000 $

2

Wafer Size History

675mm/2021?450mm/2012300mm/2001200mm/1990 -

Small dimensions on large wafers

25 nm

15nm

65 nm

45 nm

90 nm

32 nm

22 nm

IC industry: Quo vadis?

Intel

3

Moore’ law: Cost per IC function

1

10

100p

rice p

er

IC 100 k

1 M

10 M

0.7 0.5 0.35 0.25 0.18 0.12μm 90 65 45nm

Reference point: 30 mm2 in CMOS12,Dataquest: monitor of wafer price per unit area 1998-2005Dataquest mask cost: 1998-2010

Moore’ law: Cost per IC function

Economy dictates large series of products:

memories,

processors,

multi-system ICs, with a multitude of functions

1

10

100

pri

ce p

er

IC 100 k

1 M

10 M

0.7 0.5 0.35 0.25 0.18 0.12μm 90 65 45nm

4

0

1

2

3

4

5

1989 1992 1995 1998 2000 2002 2004 2007 2010 2015Year of production (ITRS)

Volt

0.7 0.5 0.35 0.25 0.18 0.12 90 65 45 32

More on a chip: the power crisis

Power= activity x frequency x capacitance x voltage2

Power crisis:

Need to reduce power supply voltage limited by:

-sub-threshold leakage(can be avoided by switching functional blocks)

- variability

0

1

2

3

4

5

1989 1992 1995 1998 2000 2002 2004 2007 2010 2015Year of production (ITRS)

Volt

5

Outline

• Introduction

• Variability

• Measuring for signal integrity

• Outlook

Variability:

Deterministic effects, but difficult to predict and control:- NBTI- Lithographical deviations- Signal integrity- Stress (by wiring or STI)- Temperature gradient- Substrate noise

Stochastic (random) processes:- Component mismatch- Jitter

6

Courtesy: Boris Ljevar (Philips)

Variability:90 nm CMOSFrequencydistribution offree-runningoscillators16x7 per reticule

reticule

Centerdonut

boundaryRandom deviations

Litho: printability for different pitches

• Deep sub-micron means: working on sub-half wavelength features

• Features cannot be printed in forbidden pitch zones!

00.20.40.60.8

11.21.41.6

100 150 200 250 300 nmPitchP

rintin

g qu

ality

(Cpk

)

NA=1.05NA=1.2

forbidden zone at NA = 1.05forbidden zone at NA = 1.2

7

Trend: fixed-pitch layout

Missing wire and short-circuit fault

• Sub half-wavelength feature printing requires uniformity in layout design

Limits to accuracy

Basic limit to accuracy are the limitsto reproduce exact copies.

8

p-type substrate

S D

n+

n+

gate

TVT

T

V%312001200V

≈∝σ

∝

Δ

Accuracy in 0.25 μm CMOS

Granularity on molecular level is reached:0.25/0.25 transistor = 1200 doping atoms

p-type substrate

S D

n+

n+

gate

Granularity on molecular level is reached:0.1/0.065 transistor = 60-80 doping atomsin depletion region

p-type substrate

S Dn+ n+

gate

p-type substrate

S Dn+ n+

gate

TVT

T

V%118080V

≈∝σ

∝

Δ

Atoms don’t scale in 65 nm CMOS

Intel

9

σΔVTVin Vref

010203040506070

Δ VT [mV]-4.0 -2.0 0.0 2.0 4.0

Count m σ

CMOS matching

W,L

mVinWL

AVTVT =σΔ

Input

mVinVVV 2T1TT −=Δ

The mean variation is a matter of good engineering,The standard deviation is inverse prop to the square root of area.

1TV 2TV

CMOS matching

mVinWL

AVTVT =σ

0

2

4

6

8

0.0 0.2 0.4 0.6 0.8 1.0

σΔVT(mV)

10/0.2510/1

2/1

0.2/4

0.4/10

10/10

1.2 1.4

2/10

2/0.18

0.4/1

1.6 1.8

Ref: M. Pelgrom IEEE JSSC 1989 p. 1433

0.5 μm NMOS

m/1inWL/1 μ

0.18 μm NMOS

10

Matching: CMOS 90nm, W/L=10/5

1.5 volt

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typsnspsnfpfnspfnfp Vn

Vp

10 μA

Vn

Vp

(simulation)

200 Monte Carlo sim

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typ

snsp

snfp

fnsp

fnfp

1.5 volt

Vn

Vp

10 μA

Vn

Vp

Matching: CMOS 90nm, W/L=1/0.5

(simulation)

11

0.50

0.60

0.70

0.80

0.90

0.30 0.40 0.50 0.60 0.70

typ

snsp

snfp

fnsp

fnfp

Vn

Vp 1.5 volt

Vn

Vp

10 μA

Matching: CMOS 90nm, W/L=0.2/0.1

(simulation)

Mismatch dominates process tolerances

clock

C

C

C

C

C

C

C

C

C

C

deco

ding

1.6Gsps 6b ADC 1.6Gsps 6b ADC ScholtensScholtens//Vertegt Vertegt

ISSCC2002ISSCC2002

Yield in full-flash ADCs

0 mV 2 mV 4 mV 6 mV0%

20%

40%

60%

80%

100%

Yield

σcomparator

Probability ofmonotonicity

7-bit8 bit9 bit10 bit

12

Latch

Analog and digital

kT100ACCE

WLCC,LW

A

2VTox

2VTgategate

oxgateVT

VT

≈=σ×=

=×

=σ

Δ

Δ

EgateσΔVT

Vin VrefW,L

Diff pair

Transistor mismatch dominates thermal noise:• Major issue in many analog components• Requires extensive measures in multiplexed systems• Starts bothering digital designers

I

II

VinI VoutII

VinI VoutII

[V]

[V]

SNM

Static Noise Margin: size of “eye” defines robustness

count

SRAM has problems…

SRAM cells now move from 6T to 7,8 and 10T implementations

13

SRAM moving to 10 transistor cell

BL BL

+ + +

write read

Ref: B. Calhoun, MIT, ISSCC2006

WL WL

ΔT1 ΔT2

0.25 μm 0.18 μm 0.13 μm 0.1 μm

16 ps

16 ps

21 ps

16 ps

σΔT2(Cload=50fF)

38 ps 68 ps

σΔT2 (50,35,25,20fF)

22 ps 33 ps

…getting worse for new generations.

Wp=2Wn=8Lmin

14

Variability, random component mismatch:

• Mismatch in analog circuits is a well-known problem,some interesting correction algorithms allow tofight this problem.

• In nanometer CMOS mismatch dominates over process corner variation.

• Memory designers spend more transistors toovercome the problems.

• Stochastic nature requires new approaches andmore analog way of thinking in digital.

Variability:

Deterministic effects, but difficult to predict and control:- NBTI- Lithographical deviations- Signal integrity- Stress (by wiring or STI)- Temperature gradient- Substrate noise

Stochastic (random) processes:- Component mismatch- Jitter

15

propagationH. Veendrick

Substrate Noise:

A designers view

The problem:

0.0000000000001 Wattsensitivity

0.1-5 Watt

16

The problem:

Interference generator:every node of the circuit is contributing, dependingon frequency components, capacitor, undershoot

Interference channel:mostly through substrate, but may take short-cuts!

Interference receiver:every node picks up interference, many (canceling) paths

A simple experiment

Courtesy: AMoS/G.Vogels

N-well

VDD

GND

0.18 um CMOSHigh-ohmic substrate

17

injection through large array of substrate contacts Sensor surrounded by different

guard ring widths:0,1,2 contacts

X

Y

different X and Y spacing

A simple experiment8 variants in x,y, guard ringsilicon compared to simulation

Ignore this area for the moment

Courtesy: AMoS/G.Vogels

A simple experiment

N-well

VDD

GND

0.18 um CMOSHigh-ohmic substrateSubstrate model extractedby commercial tool:5487R’s and 6765 C’s

Zx,y Zring

GND

Courtesy: AMoS/G.Vogels

GND

0.1 V

RGND

18

70 dB between different layout implementations ! (interferer: 1 MHz sine wave at 100 mV amplitude)

A simple experiment8 variants in x,y, guard ringsilicon compared to simulation

-80

-70

-60

-50

-40

-30

-20

-10

0

10

201 2 3 4 5 6 7 8

layout

nois

e [d

b]

measurementssimulations

Courtesy: AMoS/G.Vogels

0.0 1.0 2.0 3.0 4.0 5.0 0.0

10.0m

20.0m

30.0m

40.0m

50.0m

60.0m

70.0m

80.0m

90.0m

-25.0

0.0

25.0

50.0

75.0

100.0

125.0

150.0

175.0

200.0

RGND

MAG(VN(OUT1))

PHA(VN(OUT1))

Power rail R determines net effect!

Zring=10 Ω

19

injection through digital logic

X

Y

A simple experiment!?

Too complex substrate descriptionfor interpretation

Commercial tool:From 456403 into 11 internal nodesCPU 2h:7m:28s !Memory: 1.7GSub circuit spice file: 260MB

Variability, substrate noise:

• Still a problem hardly realized by digital designers.

• Major limitation for integration possibilities forconnectivity.

• Complex due to interaction between power wiringand substrate.

• No real CAD solution available.

20

Variability: What to do?

• Actual values from stochastic distributions cannot be predicted.

• Circumstances can be measured

• More optimum setting can then be achieved

Measuring of analog parameters in VLSI ICs

analogueanalogue

logic logic

memories

memories

memories

memories

Signal Integrity Self Test (SIST) architecture

21

Signal Integrity Architecture Phase 1

Functional block 1

Processorblock 2

IP block 3

IEEE Std. 1149.1 TAP

regi

ster

Monitor 1

register

Monitor 2

regi

ster

Monitor 4

SIST controller

CMOS IC

register

Monitor 3

SIST Monitor Specification• Power Supply Sensor: overshoot, dips, average value

– 20mV resolution @ 100ps pulse width

• Temperature Sensor– 0-150°C with 10°C resolution, untrimmed

• MOS threshold voltage sensor – 10mV resolution

• Timing sensor– Tclock/16 resolution

In design

22

Analog challenges

• No impact on the digital design flow, library and specification

• No additional Vdd and Vss• Matches standard cell layout style• Area penalty around 0.1%• No analog interfaces• Switched off during non monitoring• Control algorithm complies to IEEE 1149.1

std. (keeps compatibility to present test equipment)

RSFF

GND

Vdac

OUT

reset

-

+

DAC

Scan registerDAC SEL reset out pon

VDD

pon

selector

Supply noise monitor: circuit diagram

23

Trend of the usable Beta

yes! ≈3x

no benefit …

NMOS

0

50

100

150

200

250

300

350

400

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Ldrawn [?m]

usab

le β

[][ μ

A/V

2 ]

.18um LSTP90nm LSTP90nm LOP65nm LSTP65nm LOP45nm LSTP

Usable Beta behaviour: background

short channel• high dope level• impaired mobility• threshold variability

long channel• low dope level• better device behaviour • poor output impedance

pocketimplants

24

Supply noise monitor: lay-out

The supply noise monitor in standard-cell style(tiling patterns removed).

Area: 4 pitches high, 124 μm wide

Test set-up

Functional blockActivity programmable Shift register2000 flipflops+25.000 gates

SISTcontroller

TAP

Register/TPR

Monitor 1 Monitor 2

Register/TPR

IN/OUT SIST

25

Test settings:• Switching activity• Vary frequency• Different decap

1483.0 μm

1481.5 μm

Functional Core Layout

technologymonitors

designmonitors

functionalcore

A

B

C

D

Silicon

• Four identical functional cores– A: No decap– B: Half decap– C: Nominal decap 500pF– D: Double decap

• With different test settings

• In 90nm CMOS process

26

1.3

0.0 10.0n 20.0n 30.0n0.9

1.0

1.1

1.2

Vdd

(V)

Time (s)

min Vdd

nominal decap

Simulation Results

Measurements Results

nohalfnominaldouble

DECAP

100%0.6

0.7

0.8

0.9

1.0

1.1

1.2

0% 20% 40% 60% 80%Activity

min

Vdd

(V)

2x

1x

0.5x

0

27

NTR

Temperaturecomparator

+-

×1NRR

Vref=0.8V

Temperature Monitor and Reference

1.05-1.4 V

-

+R

×DN×1

I=PTAT

800804808812

0 50 100 150V ref

in m

V

Temperature in 0C

02468

10

0 50 100 150Temperature in 0C

tem

pera

ture

rang

e

1214

σ=4.5mV

resolution=110C

Measurement Results: temperature sensor 90 nm CMOS

28

Pow

er s

witc

h

SIST Monitor Locations on 65 nm test chip

SIST7

SIST5

SIST1 SIST8

SIST0

SIST6

SIST3

SIST4

SIST2

ARM

CGU

Pow

er s

witc

h

65 nm test chip

29

Measurement Results65 nm

V ref

in m

V

823824825826827828829830831832

-30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120

Temperature

Ref

eren

ce v

olta

ge

0

20

40

60

80

100

120

0 10 20 30 40 50 60 70 80 90 100 110

Actual temperature

Switc

h po

int t

empe

ratu

re sist0sist1sist2sist3sist4sist5sist6sist7sist8

What can be done with SIST info?Phase 1, today:

• Debug, check for local disturbances

• Compare CAD predictions to real life

Phase 2:

• Improve performance based on actual status.

• Switch between power supply levels

• Control refresh cycle of dynamic memory/logic tothe actual temperature (leakage doubles every 6oC)

• Adapt error protection to expected bit-error rate.

• etc.

30

Outlook

• Economical efficiency, (low) power and variabilitywill determine the future choices and options in IC design.

• More digital design decisions will be determined by physical (analog) effects.

• The stochastic nature of variability will force somedramatic changes in design and CAD tools.

• Major adaptations of standard digital cells willbe needed to improve variability sensitivity.

• Measuring effects within the digital cores is thefirst step towards mastering this problem.

Courtesy of Roland Pantel, STM

Thank you!