nand successful as a media for ssd - iczhiku.com

ISSCC 2008 Tutorial T7

NAND successful as a media for SSD

Ken Takeuchi

Graduate School of Frontier Sciences

Dept. of Electronics Engineering

University of Tokyo

E-mail : [email protected]

http://www.lsi.t.u-tokyo.ac.jp

© 2008 IEEE International Solid-State Circuits Conference © 2008 IEEE

Definition of SSD

SSD : Solid State Drive

SSD can be anything.

: MP3 players, Camcorders, PC, USB drive and …

Define SSD as a mass storage for PC application

in this tutorial.

SSD consists of NAND and NAND controller(+RAM)

J. Elliott, WinHEC 2007, SS-S499b_WH07.


Key Design Challenge of SSD

Need to understand of the device especially about

the reliability such as endurance, data retention,

and disturb.

Require co-design of NAND and NAND controllers

to best optimize both NAND and NAND controllers.

Also, SW support such as driver and OS essential.


Outline

NAND Overview

SSD Overview

NAND Circuit Design

NAND Controller Circuit Design

Operating System for SSD

Summary


NAND Overview

NAND Architecture

NAND Density Trend

NAND Performance Trend

NAND Operation Principle


NAND Flash Cell Array

Memory cells are sandwiched by select gates.

Contactless structure : ideal 4F2 cell size

Page : program/read unit

Bitline

Bitline

Bitline

Source-line

2 Select-gate

32 Word-lines

2 Select-gate

32 Word-lines

Block : Erase unit

F.Masuoka, IEDM 1987, pp.552-555.


Top View of NAND Flash Cell Array

Simple structure : High scalability, High yield

Active area

STI

SGDSGD SGS SGSWord-linesContact to bitline Contact to source-line

Source-line

(first metal)Bitline (second metal)

K. Imamiya, ISSCC 1999, pp.112-113.


MLC vs. SLC

SLC : Single-level cell or 1bit/cell

MLC : Multi-level cell or >2bit/cell

2bit/cell : Long production record since 2001

3bit/cell or 4bit/cell : R&D but may be commercialized in

the near future (2008?)

Existing SSD uses SLC but some manufactures

announce to produce MLC based SSD.

Vth

“0” “1” “2” “3”

Number of memory cells

MLC (Multi-level cell)

Vth

“0” “1”


SLC (Single-level cell)


NAND Density Trend

0.01

0.1

1

10

100

1994 1996 1998 2000 2002 2004 2006

Year

Memory density [MB/mm2]

55% growth / year

SLC (Single-level cell) NAND flashMLC (Multi-level cell) NAND flash

ISSCC paper

K. Takeuchi, ISSCC 2006,pp.144-145.


NAND Program Speed Trend

0

2

4

6

8

10

12

1994 1996 1998 2000 2002 2004 2006

Year

Program speed [MB/sec] SLC (Single-level cell) NAND flash

MLC (Multi-level cell) NAND flashISSCC paper

MPEG2 VGA 30fpsMotion JPEG VGA 30fps

4M-pixel 3photos/sec

HDTV 60fps

5M-pixel 5photos/sec

FTTH

MLC performance is comparable with SLC.K. Takeuchi, ISSCC 2006,pp.144-145.


Chip Architecture


56nm 8Gbit NAND Flash Memory


Memory Core Circuit


§ Page buffer

Even & Odd bit-lines share one page

buffer and are alternatively selected.

Contain two latches to store two bit

data for MLC operation.


NAND Operation Principle

Read

Bit-line voltage

Time

“1”

“0”

Selected word-line

(Read voltage : 0V)

Vread (4.5V)

Vread (4.5V)

Bit-line (0.8Vàààà0V)

0V

Vread (4.5V)

Vth

“0” “1”


Read voltage

ü After precharging, bit-lines are discharged through the memory cell.

ü Unselected cells are biased to the pass voltage, Vread.

ü Small cell read current (~1uA) àààà Slow random access (~50us)

ü Serial access : 30-50ns àààà Fast read = 20-30MB/sec


NAND Operation Principle (Cont’)

ü Channel-FN tunneling

ü High reliability

ü Low current consumption

(~pA/cell)

ü Page based parallel program

Typical page size : 2-4kB

Program : Electron injection

Erase : Electron ejection

0V0V

18V

0V

0V

20V

20V 20V

S. Aritome, IEDM 1990, pp.111-114.


NAND Operation Principle (Cont’)

Memory cell array

Page buffer

Page

Row decoder

Program speed = Page size / Programming time

= 8KByte / 800us

= 10MByte/sec (56nm MLC)

All memory cells in a page are

programmed at the same time.

T.Tanaka, Symp. on VLSI

Circuits 1990, pp.105-106.

Page buffer

Bit-line

・・・

Page : 2-4KBytes

Page based parallel programming



Outline

NAND Overview

SSD Overview

NAND Circuit Design



Summary


SSD Overview

SSD Market Projection

SSD Cost Trend

SSD Reliability

SSD Performance

SSD Power Consumption


SSD Market Projection

I. Cohen, Flash Memory Summit 2007.

Gartner Dataquest

PC expected as the next killer application of NAND.


Cost Trend of NAND and HDD

Analyst expectation

NAND will replace HDD in PC in 2009-2012 if the cost

continues decreasing.

Unclear scaling scenario e.g. double exposure vs.

EUV, floating gate vs. MONOS, and 2D vs. 3D cell.

O. Balaban, Flash Memory Summit 2007.


SSD Reliability

SSD is robust.

No mechanical parts.

But need to be careful in PC application

Portable consumer electronics application

(Digital still cameras, MP3 players, Camcorders)

Effective data retention time << 10years

Data quickly transferred to PC or DVD

through USB drive and memory cards.

Most probably data backup in PC

PC application

Higher reliability required w.o. backup

Need longer data retention time : 5-10 years


SSD Reliability (Cont’)

Failure mechanism of NAND

Program disturb

During programming, electrons are injected to

unselected memory cells.

Read disturb

During read, electrons are injected to unselected

memory cells.

Write/Erase endurance & Data retention

As the Write/Erase cycles increase, damage of

the tunnel oxide causes a leakage of stored

charge.



“Classic” program disturb

Both selected and unselected cells suffer from the disturb.

VpassVpassVpassVpass disturb celldisturb celldisturb celldisturb cell10V10V10V10V

DDDD SSSS0V0V0V0V

Vpass

(10V)

Program inhibit

Bitline (Vcc)

Vpgm

(18V)

0V

Vcc

Program

Bitline (0V)

Vcc

Vpass

(10V)

VpgmVpgmVpgmVpgm disturb celldisturb celldisturb celldisturb cell18V18V18V18V

DDDD SSSS～～～～8V8V8V8V

K. D. Suh, ISSCC 1995, pp.128-129.



“Modern” program disturb

Hot carriers generated at the select gate edge inject

into the memory cell causing a Vth shift.

The Vth shift can be reduced by increasing SG-WL

space.

J. D. Lee, NVSMW 2006, pp. 31-33.

K.T.Park, SSDM 2006, pp.298-299.



“Modern” program disturb (Cont’)

The Vth shift can be reduced by adding dummy WL.

K.T.Park, SSDM 2006, pp.298-299.

Select Tr. Dummy Tr. WL0



Read disturb

4.5V

D S0V

Selected word-line

(0V)

Vread (4.5V)

Vread (4.5V)

Bitline (0.8Vàààà0V)

0V

Vread (4.5V)

Weak program bias condition

Unselected word-lines suffer

from the read disturb.



Program disturb and read

disturb is a “bit error” not a

“burst error”.Two bits in MLC are assigned to

different pages.

Even if one MLC cell fails, one bit in

two pages fails.

ECC(Error correcting code)

effectively corrects the bit error.Existing ECC corrects 4-8bit errors per

512Byte sector.

Program disturb and read disturb summary

X1

X2

2-level cell

X1

X2

4-level cell

K. Takeuchi, Symp. on VLSI Circuits

1997, pp. 67-68.

Page assignment of MLC



Write/Erase Endurance & Data Retention

K. Prall, NVSMW 2007, pp. 5-10.

Endurance : how many times data are written

Data retention : how long the data remains valid

Clear correlation between endurance and data

retention

Damages to the tunnel oxide during write and

erase cause the data retention problems.

Traps are generated during write and erase.

The unlucky cell with traps results in a leakage

path, causing the charge transfer.

The leakage current is called SILC (Stress

Induced Leakage Current).

To guarantee data retention, Write/Erase cycles

are limited to 100K (SLC) or 10K (MLC).



100K (SLC) or 10K(MLC) W/E cycles acceptable?

W/E cycles estimation

32GB SSD

Usage scenario : 2~5GB/day (#)

Service for 5years

100% efficient wear leveling

(365 days/year) x 5years / (32GB / 2~5GB/day)

= 114~285 W/E cycles

114~285 cycles are far below the NAND limitation

of 100K for SLC or 10K for MLC.

Actual W/E cycles are higher for the file

management such as garbage collection.(#) W.Akin, IDF 2007_4, MEMS003.

Y.Kim, Flash Memory Summit 2007.


SSD Performance

Random access

OS changes such as

directory entry and file

system metadata

Application S/W change

50% of data is < 4KB.

Random access mainly

decides the performance

of PC.

Sequential accessBoot

Hibernation

K.Grimsrud, IDF2006, MEMS004.

[Data transfer size in PC application]


SSD Performance (Cont’)

Read Write Erase

NAND (SLC) 25us 300us 1ms

NAND (MLC) 50us 800us 1ms

HDD 3ms 3ms N.A.

Random access

Read : SSD with SLC and MLD has a great advantage over HDD.

Write : SSD still has a performance advantage. But the write

performance can be an issue in the future if the NAND

performance degrades by scaling the memory cell or increasing

the number of bits per cell.

Erase are hidden by operating the erase during the idle period.



NAND : Single chip operation NAND : 4 chip interleaving

Read Write Read Write

NAND (SLC) 25MB/sec 20MB/sec 100MB/sec 80MB/sec

NAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/sec

HDD 80MB/sec 80MB/sec - -

Sequential access

SSD (SLC) : Comparable read and

write performance with HDD.

SSD (MLC) : Comparable read

performance. By introducing 8chip

interleaving, the write performance

can be comparable with HDD.

[Block diagram of SSD w. interleaving function]

C. Park, NVSMW 2006, pp.17-20.



Actual performance results

SSD (SLC) has superior performance over HDD.C. Park, NVSMW 2006, pp.17-20.

[PC-mark05]

[Bootvis]

[Sandra]


SSD Power Consumption

Power consumption

Actual Power Consumption

NAND : Single chip operation NAND : 4 chip interleaving

Read Write Read Write

NAND (SLC) 20mA 20mA 80mA 80mA

NAND (MLC) 20mA 20mA 80mA 80mA

HDD >300mA >300mA - -

In SSD, additional current (~100mA) are consumed in the

NAND controller, RAM and IO.


In all modes, the power consumption of SSD is smaller

than HDD.


Outline

NAND Overview

SSD Overview

NAND Circuit Design



Summary


NAND Circuit Design

Random Access

High Speed Programming

High Speed Read

Sequential Access

High Speed Programming

High Speed Read


Random Access : High Speed Programming

Bit-by-bit Program Verify Scheme

T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.

During the verify-read, the program data in the page buffer

is updated so that the program pulse is applied ONLY to

insufficiently programmed cells.

FN tunneling

Program pulse

18V

0V0V

0V

Page buffer

Bit-line

・・・

PageAll cells programmed ?

End

Data load

Verify-read

Program pulse

Yes

No

Program Algorithm


Random Access : High Speed Programming (Cont’)

Incremental Program Voltage Scheme

G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.

K. D. Suh, ISSCC 1995, pp.128-129.

Achieve both fast

programming and

precise Vth control.

⊿⊿⊿⊿Vth0Npulse

(Time)

(⊿⊿⊿⊿Vth0/⊿⊿⊿⊿Vpgm) cycles

Verify

voltage

Fastest cellSlowest cell

VthNpulse = ⊿⊿⊿⊿Vth0/⊿⊿⊿⊿Vpgm

Program characteristics

Program voltage, Vpgm

increases by ⊿⊿⊿⊿Vpgm.

Constant electric field

across the tunnel oxide.

Vth shift is constant at ⊿⊿⊿⊿Vpgm.

Verify read

Program pulse

Tpulse Tvfy

1 cycle

# of program pulses: Npulse cycles

⊿⊿⊿⊿Vpgm

Programming time, Tprog = (Tpulse+Tvfy)×Npulse

Word-line waveform

Constant tunnel current.



Problems of MLC programming

Two bits in a cell are assigned

to two column addresses.

3 operations (“1”-, “2”- and

“3”-program) required.

Long programming.

Vth

“0” “1” “2” “3”


MLC

“1”-program

& ”1”verify

“2”-program

& ”2”verify

“3”-program

& ”3”verify

“1”-program

& ”1”verify

SLC

Y1 Y2 Y1 Y24-level cell2-level cell



Solution : Multi-page Cell Architecture

K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

Two bits in a cell are

assigned to two row

addresses.

In average, 1.5 operations.

Twice faster than

conventional scheme.


Vth

“0” “1”

1st page data : “1” “0”

1st page program1st page program

2nd page program2nd page program

2nd page data : “1” “0”

Vth

“0” “1” “2” “3”Number of memory cells

1st page data : “1” “0” “0” “1”

X1

X2

2-level cell

X1

X2

4-level cell



Program Voltage Optimization

T. Hara, ISSCC 2005, pp. 44-45.

WL0, 31 : Higher capacitive coupling with word-lines.

Initial program voltage is set lower.

Optimized program voltage accelerates the programming.



Problems : FG-FG interference

J.D. Lee, EDL 2002, pp. 264-266.

M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90.

FG-FG coupling shifts the Vth of a memory cell as the

neighboring cell are programmed.

To tighten the Vth distribution, ⊿⊿⊿⊿Vpgm is decreased,

causing a slow programming.

The Vth modulation becomes significant as the memory

cell is scaled down.



Solution : FG-FG Coupling Compensation

N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.

FG-FG coupling is suppressed by 90%.

Large ⊿⊿⊿⊿Vpgm enables a fast programming.

[3-step programming] [Programming order]

Step 1

Step2

Step3

Step 1. The memory cell is ROUGHLY programmed.

Cells are programmed BELOW the target Vth.

Step 2. Neighboring cells are programmed.

Step 3. The memory cell is PRECISELY programmed.


Random Access : High Speed Read

Problems of MLC read

Two bits in a cell are assigned

to two column addresses.

3 operations (“1”-, “2”- and

“3”-read) required.

Long random read.

Vth

“0” “1” “2” “3”


Y1 Y2 Y1 Y24-level cell2-level cell

MLC

“1”-read

“2”-read

“3”-read

“1”-read

SLC

①①①① ②②②② ③③③③


Random Access : High Speed Read (Cont’)

Solution : Multi-page Cell Architecture

K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

S. Lee, ISSCC 2004, pp.52-53.

Two bits in a cell are

assigned to two row

addresses.

In average, 1.5 operations.

Twice faster than

conventional scheme.

X1

X2

2-level cell

X1

X2

4-level cell

Vth

“0” “1” “2” “3”


1st page read : ②②②②, ③③③③ àààà EXOR

2nd page read : ①①①①

2nd page data : “1” “0”

1st page data : “1” “0” “0” “1”

①①①①②②②② ③③③③


Sequential Access : High Speed Programming

Parallel Operation

Increase page size

Multi-page operation

Multi-chip operation (Interleaving)To be discussed in “NAND Controller Circuit Design” section

Pipeline Operation

Write/Read Cache

Cache Page Copy


Parallel Operation : Increase Page Size

Page size trend

By increasing the word-line length, the page size has been

extended to increase the write and read throughput.

But, the large page size also causes problems.

Noise issue due to the large RC delay of a word-line

Page buffer

Bit-line

・・

・

Page

0

500

1000

1500

2000

2500

3000

3500

4000

4500

0.25um 0.16um 0.13um 90nm 70nm 50nm

Page size (Byte)

Design rule


Problems : SG-WL noise

Selected

WL31

Bit-line

SGD

SGS

WL0

[Conventional read/verify-read]

Bit-line

precharge

Bit-line

discharge

1.5V

SG-WL capacitive coupling

WL bounce

Read failure


Parallel Operation : Increase Page Size (Cont’)




Solution : Raise neighboring SG BEFORE bit-line discharge



Problems : WL-WL noise




Solution



Parallel Operation : Multi-page Operation

Multi-page operation

Operate multi-page simultaneously to increase the write/read

throughput.

K. Imamiya, ISSCC 1999, pp.112-113.

[Multi-page operation] 0.25um 256Mb NAND


Pipeline Operation : Write/Read Cache

Pipelining of data-in/out & cell read/writeImplement data cache in NAND

Input /output data to the data cache during cell read/program

H. Nakamura, ISSCC 2002, pp.106-107.

[Write Cache Example : 0.13um 1Gbit NAND]

Data Cache


Pipeline Operation : Cache Page Copy

System performance degradation of a large block


70nm 8G MLC

(ISSCC2005)

4KB page (max)

32WLs

512KB block

[Frequent block copy]

1MB block

56nm 8G MLC

(This work)

8KB page (max)

32WLs

NAND

controller

Old block

Page buffer

New block

①①①① Cell read

②②②② Data-out,

ECC, Data-in

③③③③ Cell program

Fast block copy required

System performance degradation

Block copy time

= (T_Cell read+T_Data_out+TECC+T_Cell program)

××××(# of pages per block)

= 125ms

(ISSCC2006)


Pipeline Operation : Cache Page Copy (Cont’)

Solution : Fast block copy


NAND

controller

Old block

Page buffer

New blockCell Read

Page i

Data-out

ECC NAND

controller

Old block

Page buffer

New block

NAND

controller

Old block

Page buffer

New block

Page i+1

Cell read

Cell program

NAND

controller

Old block

Page buffer

New block

Data-out

ECC

Step1 Step2 Step3 Step4

Step 4 : Pipelining of programming Page iand data out / ECC of Page i+1.

Fast block copy


Outline

NAND Overview

SSD Overview

NAND Circuit Design



Summary



HW Architecture

SW Architecture

High speed technology

Interleaving

High reliability technology

Wear Leveling

Bad Block Management

ECC

SLC/MLC Combo


HW Architecture

Block diagram (Single channel)


HDD-like architecture : DRAM buffer to hide NAND random access

High power consumption

High cost


HW Architecture (Cont’)

Block diagram (Multi-channel)


DRAM eliminated :

Random access of NAND

is faster than HDD.

Low power consumption

Low cost

Multi-channel

Parallel operation

High bandwidth


SW Architecture

Host and SSD SW structure

FTL (Flash Translation Layer)


Host I/F : SATA, PATA, PCIe,

USB, LBA, BA, SD, MMC…

NAND I/F : Low level driver to

access NAND through NAND

controller.

Main part of SSD.

Address translation from

logical address to physical

address of NAND.

File management such as bad

block management and wear

leveling.


High Speed Technology

Interleaving : Sequential Parallel Write


2-channel 4-way interleaving

Max write throughput : 80MB/sec for MLC.

HW driven automatic operation.


High Reliability Technology (Cont’)

Wear-levelingProblem

Write/Erase cycle of NAND is limited to 100K for SLC and 10K

for MLC.

Solution

Write data to be evenly distributed over the entire storage.

Count # of Write/Erase cycles of each NAND block.

Based on the Write/Erase count, NAND controller re-map

the logical address to the different physical address.

Wear-leveling is done by the NAND controller (FTL), not by

the host system.

Bitline

Bitline

Bitline

Block : Erase unit



Example of wear-leveling

If the block is occupied with old data, data is programmed

to a new block.

If there is no free block, the invalid block are erased.

Block 1Block 2Block 3Block 4Block 5Block 6Block 7Block 8Block 9

Rewrite

old file

New File Write new file to

an empty block

Old file

Empty block

Block 4 à Invalid

Block 1Block 2Block 3Block 4Block 5Block 6Block 7Block 8Block 9



Static data

Data that does not change such as system data

(OS, application SW).

Dynamic data

Data that are rewritten often such as user data.

Dynamic wear-leveling

Wear-level only over empty and dynamic data.

Static wear-leveling

Wear-level over all data including static data.



Dynamic wear-leveling

Write/Erase count

Physical block address

N.Balan, MEMCON2007.

SiliconSystems, SSWP02.

Red : Static data such as system data.

Blue : Dynamic data such as user data

Block with static data is NOT used for wear-leveling.

Write and erase concentrate on the dynamic data block.



Static wear-leveling

Write/Erase count

Physical block address

Red : Static data such as system data.

Blue : Dynamic data such as user data

Wear-level more effectively than dynamic wear-leveling.

Search for the least used physical block and write the data to

the location. If that location

Is empty, the write occurs normally.

Contains static data, the static data moves to a heavily

used block and then the new data is written.N.Balan, MEMCON2007.

SiliconSystems, SSWP02.



Bad Block Management

Program/Erase characteristics vs. endurance

As the Write/Erase cycles increases, erase failure occurs,

resulting in a bad block.

The NAND controller detects and isolates the bad block.

Y.R. Kim, Flash Memory Summit 2007.



ECC (Error Correcting Code)

To overcome read disturb,

program disturb and data

retention failure, ECC have to

be applied.

Since failure pattern is

random, BCH is sufficient.

Existing NAND controller

can correct 4-8bit error per

512Byte sector.

NAND with embedded ECC is

also published. R. Micheloni, ISSCC2006, pp.142-143.


MLC/SLC Combo

Future Direction : Hybrid SSD with SLC and MLCConcept : Right device for the right use.

Enjoy the Benefit of both SLC and MLC.

SLC : Fast and highly reliable but low capacity.

Use SLC as a cache or system data storage.

MLC : Large capacity but slow. Use MLC as user data storage.

2006 20102007 2008 2009

PATA4/8/16/32GB

SATA-I8/16/32/48/64GB

SATA-II8/16/32/48/64GB

MLC(Multi Level Cell)

Combo

(SLC+MLC)

SLC(Single Level Cell)

SATA-II16/32/64/96/128GB

SATA-III56/112/224/336/448GB

SATA-II14/28/56/84/112GB

SATA-III32/64/128/192/256GB

SATA-II16/32/48/64/96/128GB

SATA-II32/48/64/128/256GB

SATA-II28/56/112/168/224GB

57/32 64/45 100/80 160/160 800/800 1300/1300R/W Speed:

SATA-III 48/64/128/256/512GB

Samsung Combo SSD J. Elliott, WinHEC2007.

Toshiba LBA-NAND

http://www1.toshiba.com/taec/index.jsp

Spansion MirroBit Eclipse

http://www.spansion.com/products/MirrorBit_Eclipse.html


Outline

NAND Overview

SSD Overview

NAND Circuit Design



Summary



Performance Optimization

Sector Size Optimization

Reliability Optimization

EWF (Enhanced Write Filter)

SMART (Self-Monitoring, Analysis and

Reporting Technology)


Future Perspective

Motivation

Existing OS is optimized for magnetic drives.

Current SSD based PC uses the conventional

OS and just replace HDD with SSD.

To achieve the best performance and

reliability of SSD, OS especially file system

should be optimized.


Performance Optimization

Sector size optimizationMinimum write/read unit of NAND is a page.

Typical page size is 4-8KByte.

A page is written only ONCE to avoid the

program disturbance.

With current OS having 512Byte sector , one

sector write wastes >80% of data in a page.

LBD(Long Block Data) sector standard :

4KByte sector size fits better with SSD.

Considering the page size increases as NAND

is shrinking, larger sector size such as

16KByte or 32KByte is preferred.

Page

1 sector

write

・・・

Remaining portion

becomes garbage.


Reliability Optimization

Enhanced Write Filter (Windows Embedded)

Control the file allocation to store frequently rewritten file in

DRAM and not to access NAND.

Decrease write/erase cycles of NAND, extending the NAND

lifetime.

Enhanced Write Filter (EWF) is located between file system

and low level driver interfacing with SSD.

http://msdn2.microsoft.com/en-us/library/ms912909.aspx

Enhance

Write Filter

File System

Application

Low-level Driver


Reliability Optimization (Cont’)

SMART

(Self-Monitoring, Analysis and Reporting Technology)

Monitor the storage and report/predict the failure.

SMART for HDD is NOT smart because it is very difficult to

predict the mechanical failure.(Google report, http://209.85.163.132/papers/disk_failures.pdf)

SMART for SSD can be really smart.

Product lifetime can be predicted because the failure rate is

highly correlated with the write/erase cycles.

Predict the SSD lifetime by monitoring the write/erase

cycles and replace SSD before the fatal failure occurs.

http://www.tdk.co.jp/tefe02/ew_007.pdf


Outline

NAND Overview

SSD Overview

NAND Circuit Design



Summary


Summary

Market & Cost : NAND will replace HDD in PC in 2009-2012.

Key issue : Is scaling sustainable?

Unclear scaling scenario e.g. double exposure vs. EUV,

floating gate vs. MONOS, and 2D vs. 3D cell.

MLC is a MUST for the cost reduction.

Existing 2bit/cell satisfies performance, reliability and power

consumption requirements.

>2bit/cell or scaled MLC may face performance/reliability

challenges.

Key breakthrough of NAND circuit or NAND controller circuit

such as SLC/MLC Combo required.

Optimization of OS will also help.


Thank you!

E-mail : [email protected]

http://www.lsi.t.u-tokyo.ac.jp


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