nand and nor implementation

7/23/2019 NAND and NOR implementation

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Dr Oday A.L.A Ridha 29

NAND and NOR implementation

Digital circuits are more frequently construct with NAND or NOR

gates than with AND and OR gates. NAND and NOR gates are easier tofabricate with electronic components and are the basic gates used in all IC

digital logic families.

Not equivalent

OR equivalent

AND equivalent

Example: implement the following logic circuit using NAND gates only




Solution:

Step 1:

Step 2:

Properties of exclusive OR and Equivalence

Exclusive-OR and equivalence, denoted by ⊕ and Θ , respectively.

The two operations are complements of each other. Each is

commutative and associative.

C B AC B AC B A ⊕⊕=⊕⊕=⊕⊕ )()(

An n-variable XOR expression is equal to the Boolean function with

2/2n

minterms whose equivalent binary numbers have an odd

numbers of 1’s.

An n-variable equivalence is equal to the Boolean function with 2/2n

minterms whose equivalent binary numbers have an even numbers of

0’s.

When the number of variables in a function is odd the minterms withan even number of 0’s are the same as the minterms with odd number




of 1’s, therefore an XOR expression is equal to Equivalence

expression when both have the same odd number of variables.

C B AC B A ΘΘ=⊕⊕

When the minterms of a function with an odd number of variables

have an even number of 1’s (or equivalently, an odd number of 0’s),

the function can be expressed as the complement of either an

exclusive-OR or an equivalence expression.

C B AC B AC B A ⊕Θ=Θ⊕=′⊕⊕ )(

C B AC B AC B A Θ⊕=⊕Θ=′ΘΘ )(

Complement one of the inputs of XOR or equivalence function isequal to complement the same function. (Prove that ).

Exclusive-OR and Equivalence functions very useful in system

requiring error-detection and error-correction codes. Parity bit is a

scheme for detecting errors during transmission of binary information. A

parity bit is an extra bit included with a binary message to make the

number of 1’s either odd or even. The message included the parity bit, is

transmitted and then checked at receiving end for error.

Example: design a 3-bit odd parity generator

3-bit

message Parity bit

GeneratedPA B C

0 0 0 1

0 0 1 0

0 1 0 00 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

BC

A 00 01 11 10

0 1 1

1 1 1

C B AC B AP Θ⊕=′⊕⊕= )(




Example: design an odd parity checker for 4-bit pattern

Parallel adder

4-bit parallel binary adder

4-bit message Check

EA B C P

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 10 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 0

1 1 1 0 01 1 1 1 1

AB

CP 00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

PC B A E ΘΘΘ=

FA4

A4 B4

S4

C4 FA1

A1 B1

S1

C1 FA2

A2 B2

S2

C2 FA3

A3 B3

S3

C3 C5




Carry propagation

Time required to propagate a carry from C1 to Cn+1 in an n-bit parallel

adder is equal to 2n times propagation delay time of one gate.

Look-ahead Carry

The carry propagation time is a limiting factor on the speed with

which two numbers are added in parallel. There are several techniques for

reducing the carry propagation time in a parallel adder. The most widely

used technique employs the principle of look-ahead carry.

Consider the full-adder shown in the figure below. If we define two

new binary variables:

i B AP ii ⊕=

iii B AG =

S2

C3

Sn

Cn+1

HAHA

FA 1

A1 B1

C1 S1

C2

HAHA

FA 2

A2 B2

C2

HAHA

FA n

An Bn

Cn




The output sum and carry can be expresses as:

iC PS ii ⊕=

iC PGC iii +=+1

Now we can write the Boolean function for the carry output of eachstage and substitute for each its value from the previous equations:

1112 C PGC +=

112122111222223 )( C PPGPGC PGPGC PGC ++=++=+=

11231232333334 C PPPGPPGPGC PGC +++=+=

Since the Boolean function for each output carry is expressed in sum

of products, each function can be implemented with one level of AND gates

follows by an OR gate. Note that Cn does not have to wait for Cn-1, Cn-2, ...,

and C1 to propagate; in fact, Cn is propagated at the same time as C1, and C2.

BCD adder

Is a circuit that adds two BCD digits with a possible carry from previous

stage, in parallel, and produces a sum digit also in BCD. Since each input

digit doesn’t exceed 9, the output sum cannot be greater 19, (9+9+1).

Suppose we apply two BCD digits to a 4-bit binary adder. The adder

will form the sum in binary and produce a result which may range from 0 to

19. These binary numbers are listed in the table below and are labeled by

symbols K, Z8, Z4, Z2, Z1. K is the carry, and subscripts under the letter Z

represent the weights that can be assigned to the four bits in the BCD code.

The first column in the table lists the binary sums as they appear in the

outputs of a 4-bit binary adder. The output sum of two decimal digits must

P1

G1

A1 B1

G2

A2 B2

P3A3 B3

P4

G4

A4 B4

C1

P1

P2

P3

P4

S1

S2

S3

S4

C5

C4

C3

Look-

ahead carry

generator

C5

C1

C2P2

G3




be represented in BCD and should appear in the form listed in the second

column of the table.

Binary sum BCD sumDecimalK Z8 Z4 Z2 Z1 C S8 S4 S2 S1

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 0 0 0 1 0 0 4

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 110 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18

1 0 0 1 1 1 1 0 0 1 19

In examination the contents of the table, it is apparent that when the sum is

equal or less than 9, the corresponding BCD number is identical, andtherefore no conversion is needed. When the binary sum is greater than 9,

we obtain a nonvalid BCD representation. The addition of 6 to the binary

sum converts it to the correct BCD representation and also produces an

output carry as required.

The logic circuit that detects the necessary correction can be derived from

the table entries. It obvious that correction is needed when the binary sum

has an output carry K=1. The other six combinations from 1010 to 1111 that

need a correction have a 1 in position Z8. To distinguish them from binary

1000 and 1001 which also have a 1 in position Z8, we specify further that

either Z4 or Z2 must have a 1. The condition for a correction and an outputcarry can be expressed by the Boolean function:

2848 Z Z Z Z K C ++=

When C=1, it is necessary to add 6 to the binary sum and provide an output

carry for next stage.




Magnitude Comparator

The comparison of two numbers is an operation that determines if one

number is greater than, less than, or equal to the other number. A magnitude

comparator is a combinational circuit that compares two numbers, A and B,and determines their relative magnitude. The outcome of the comparison is

specified by three binary variables that indicate whether A>B, A=B, or A<B.

If

0123 A A A A A =

0123 B B B B B =

We define

iiiii B A B A x ′′+= i=0, 1, 2, 3

Then

0123)( x x x x B A ==

00123112322333)( B A x x x B A x x B A x B A B A ′+′+′+′=>

00123112322333)( B A x x x B A x x B A x B A B A ′+′+′+′=<

Exercise: draw the logic circuit of 3-bit magnitude binary comparator

4-bit binary adder

Z8 Z4 Z2 Z1

Carry in

K

4-bit binary adder

S8 S4 S2 S1

0

Output Carry

Addend Augend




Decoders

Discrete quantities of information are represented in digital system with

binary codes. A binary code of n bits is capable of representing up 2n distinct

elements of the coded information. Decoder is a combinational circuit thatconverts binary information from n input lines to a maximum of 2n unique

output lines. If n-bit decoded information has unused or don’t-care

conditions, the output decoder will have less than 2n output. The name

decoder is also used in conjunction with some code converters such as BCD-

to-seven-segment decoder.

Inputs Outputs

X Y Z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Truth table of 3-to-8 lined decoder

Observe that the output variables are mutually exclusive because only one

output can be equal to 1 at any time. The output line whose value is equal to1 represents the minterm equivalent of the binary number presently available

in the input lines.

We can construct a more big line decoder using small decoders

Example: construct a 4-to-8 (4×16) line decoder using 3-to-8 decoder.

D0

D2

D1

D3D4

D6

D5

D7En

3×8

Decoder

D8

D2

D9

D11D12

D14

D13

D15En

3×8

Decoder

A

B

C

D




Exercise1: Design BCD-to-decimal decoder.

Exercise2: Design BCD-to-seven-segment decoder.

Exercise3: Implement a full-adder circuit using 3-to-8 decoder.

Encoders

An Encoder is a digital function that produces a reverse operation from that

of decoder.

OutputsInputs

X Y ZD0 D1 D2 D3 D4 D5 D6 D7

0 0 010000000

0 0 101000000

0 1 000100000

0 1 1000100001 0 000001000

1 0 100000100

1 1 000000010

1 1 100000001

Truth table of 8-to-3 encoder

Multiplexers

Multiplexing means transmitting a large number of information units over a

smaller number of channels or lines. A digital multiplexer is a combinational

circuit that selects binary information from one of many input lines anddirects it to single output line. The selection of particular input line is

controlled by a set of selection lines. Normally, there are 2n input lines and n

selection lines whose bit combinations determine which input is selected.

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Boolean function implementation using multiplexers

If we have a Boolean function of n+ 1 variables, we take n of these variables

and connect them to the selection lines of the multiplexer. The remaining

single variable of the function is used for the inputs of the multiplexer. If A

is this single variable, the inputs of the multiplexer are chosen to be either A

or A’ or 1 or 0. By judicious use of these four values for the inputs and by

connecting the other variables to the selection lines, one can implement any

S0 S1

Y

01

2

3

4×1

MUX

I0 I1

I2 I3

OutputInputs

Select




Boolean function with a multiplexer. In this way it is possible to generate

any function of n+1 variables with a 2n –to-1 multiplexer.

Procedure

1)

express the function in its sum of minterms form, Assume that theordered sequence of variables chosen for minterms is ABCD…, where

A is leftmost variable in the ordered sequence of n and BCD… are the

remaining n-1 variables. Connect the n-1 variables to the selection lines

of the multiplexer with B connected to high-order selection line, C to

the next lower selection line and so on down to the last variable.

2) List the inputs of the multiplexer and under them list all the minterms in

two rows. The first row lists all those minterms where A is

complemented, and the second row all the minterms with A

uncomplemented.3)

Circle all the minterms of the function and inspect each column

separately.

a)

If the two minterms in a column are not circled, apply 0 to the

corresponding multiplexer input.

b)

If the two minterms are circled, apply 1 to the corresponding

multiplexer input.

c) If the bottom minterm is circled and the top is not circled, apply

A to the corresponding multiplexer input.

d)

If the top minterm is circled and the bottom is not circled, apply

A’ to the corresponding multiplexer input.

Example: Implement ( )∑= 15,9,8,4,3,1,0),,,( DC B AF with a multiplexer

Solution

I0 I1 I2 I3 I4 I5 I6 I7

A’ 0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

1 1 0 A’ A’ 0 0 A

D

I0

I1

I2 I3

I4

I5

I6

I7

Y F8×1

MUX

0

1

A

BC




Demultiplexers

It is a combinational logic circuit that receives information on a single line

and transmits this information on one of 2n possible output lines. The

selection of a specific output line is controlled by the bit values of nselection lines. A decoder with an enable input can function as a

demultiplexer.

Read-only memory (ROM)We know that a decoder can generate 2n minterms of the n input variables.

By inserting OR gates to sum the minterms of Boolean functions, we were

able to generate any desired combinational circuit. A read-only memory

(ROM) is a device that includes both the decoder and the OR gates within a

single IC package. The connections between the outputs of the decoder and

the inputs of the OR gates can be specified for each particular configuration

by “programming” the ROM. The ROM is very often used to implement a

complex combinational circuit in one IC package and thus eliminate all

interconnecting wires.

Memory size=2n×m

E A B D0 D1 D2 D3

0 X X 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

A B D0 D1 D2 D3

0 0 E 0 0 0

0 1 0 E 0 0

1 0 0 0 E 0

1 1 0 0 0 E

m Outputs

(Data)

n Inputs

(Address)

2n×m

ROM

E

Input

Select

D0

D1

D2

D3

1×4

Demultiplexer

D0

D1

D2

D3

A B

2×4

Decoder

A

B

E

Enable




ROM types

1)

Mask programming ROM

2)

Programmable ROM (PROM)

3)

Erasable Programmable ROM (EPROM)4)

Electrically Erasable Programmable ROM (E2PROM)

Example: Design a combinational circuit that accept a 3-bit number and

generates an output binary number equal to the square of the input number.

Use a minimum ROM size.

Solution:

Inputs Outputs

X Y Z D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 10 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 1 0 1 1 0 0 1

1 1 0 1 0 0 1 0 0

1 1 1 1 1 0 0 0 1

D4

D5

D3

D2

23×4

ROM

D1

D0

Z

Y

X

0

nand and nor implementation

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