Pufall, THIC’05: 1

MRAM: Device Basics and Emerging Technologies

Matthew R. Pufall

National Institute of Standards and Technology325 Broadway, Boulder CO 80305-3337

Phone: +1-303-497-5206 FAX: +1-303-497-7364E-mail: pufall@boulder.nist.gov

Presented at the THIC Meeting at the National Center for Atmospheric Research, 1850 Table Mesa Drive, Boulder CO 80305-5602

July 19-20, 2005

Pufall, THIC’05: 2

Collaborators:

NIST:Bill RippardShehzu KakaSteve RussekTom Silva

Hitachi Global Storage:Jordan Katine

Freescale:Fred MancoffNick Rizzo

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Outline

• What is MRAM? What are its advantages?• When will we see MRAM?• How does MRAM work?

• Spintronics basics: Electron spin and Magnetoresistance• Anatomy of an MRAM bit• Magnetic Switching

• Engineering Challenges: Consistency and Thermal Stability• Freescale’s MRAM solution: “Toggle” MRAM• Big Problems in the Nano-Future: Scaling of bits• Emerging Solutions to Scaling: Spin Torque Switching

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What is MRAM?Magnetic-based Random Access Memory:

Uses small magnetic element to store 1,0 rather than electric charge

(Some) Other types of RAM:Storage Method Virtues

DRAM Charge on capacitor speed, size, costSRAM Multiple transistors speed, size, no refreshFRAM Ferroelectric capacitor nonvolatile, speedFlash Transistor w/ extra nonvolatile, cost, size

isolated gate

…All have advantages/tradeoffs: No “universal” solution

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MRAM advantages:

NonvolatileData don’t need refreshing

• “instant on”, low power• Data retention >10 yrs

FastRead/write symmetric

• 25 ns (10 ns in demo)• byte writeable

Unlimited cycling No “fatigue” after >1016 cycles

Viability Integrated into CMOS process

…If made (very) inexpensive and scalable, a potential “universal” solution

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When (and where) will we see MRAM?

Freescale:Demos out to vendors Shipping product end of 2005/early 2006

Others: IBM—In developmentToshiba/NECCypress, Honeywell: ?

Uses: Replace battery-backed SRAMCell phone/embedded memory

4 Mb chip, 180 nm process

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How does MRAM work?

Mx

y

zHysteresis Loop

-1 0 1Magnetic Field H

My

“1”

“0”-1

1

Field H

Ferromagnets have hysteresis: Information stored in state @H = 0

• Hard disks, tape storage

Magnetic fields used to change direction (state) of M

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How do you sense state of M?Magnetoresistance (MR): Resistance depends on

direction of Mcurrent I

Mfree

Mfixed

Low Resistance High Resistance

How? Electrons also have magnetic moments: Spin

“Spintronics”

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Magnetization Filters e- Spin:Electron spins become spin-polarized in direction of M: Spin filter

Magnetization M1

Transmitted spinsIncident e- current

Nonparallel spins scatter more: Higher resistance

∆R ~ cos(θM)

Sense M by Resistance:0.6x1.2µm bit at 300mV bias

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Mfree

7.5

8

8.5

9

9.5

10

10.5

11

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

MR=37%

7.5

8

8.5

9

9.5

10

10.5

11

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

Field H

7.5

8

8.5

9

9.5

10

10.5

11

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10

Magnetic Field H

RA

(kΩµm

2 )

Mfixed

Current I

State of M determined by electrical measurement:“Magnetic Tunnel Junction” (MTJ)

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Anatomy of an MRAM bitBit Line

Line

BL Program Line

Tunnel Barrier

Pinning Layer

Digit Line

Bit Line

Pinned Ferromagnet

Free Ferromagnetic Layer

Heasy

M

-75 -50 -25 0 25 50 7505

10152025

3035

MR (%)Hhard = 0 Oe

Heasy (Oe)

RA = 10 kΩµm2

Hhard = 40 Oe

Hard axis field decreases Hc

Hhard

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Bit Selection Energetics

Eb

Eb

E

θ

“0” “1”

0 π

Eb

Hhard ≠ 0

(a)

(b)

Heasy≠ 0

Eb

Eb

E

θ

“0” “1”

0 π

Eb

Hhard ≠ 0

(a)

(b) Heasy > 0 orHhard > 0

Heasy = 0Unselected

½-SelectedLower barrier

Heasy≠ 0

(c)Selected (c) Heasy > 0 andHhard > 0

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Bit Addressing Challenges

IhardHhard

Heasy

MRAM bit

X

Programming Probabilityfrom 256k chip

ibit

idigit

Min. Fail bits

ibit

idigit

Min. Fail bits

Operating point

Ihard

IeasyData courtesy Freescale

Bits switched/addressed by two fieldsChallenge: Bit-to-bit variations make choosing

proper currents difficult/impractical

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Freescale’s Solution: “Toggle” MRAM

Bit LineBL Program LineBit LineProgram Line 2

Line

Free Tri-Layer

Tunnel Barrier

Line 1

Pinned Ferromagnet

Pinning Layer

Ferromagnetic layerCoupling LayerFerromagnetic layer

Program Coupled tri-layer programs more repeatably

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How does Toggle work? TimingAnti-parallel-coupled layers respond differently to fields:

HY

HY HY

LowResistance

State

HighResistance

State

HX HX

HX

Figure courtesy Freescale

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What does Toggle do?• Moves “1/2 select” error horizon:

H 2

toggling

toggling

I

IIIII

IV

No disturb

No disturb

No disturb

No disturb

toggling

toggling

I

IIIII

IV

No disturb

No disturb

No disturb

No disturb

i bit

idigit

Operatingregion

0% switching region(no disturbs)

H1

Also increases bit volume (& thermal stability)

4Mb, March 6N Toggle Map

Data courtesy Freescale

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Freescale 4Mb MRAM Layer structure

Program Path: Dashed green lineSense Path: Red line (isolated)

Chip process at 180 nm node: Design ported to 90 nm (May ‘05)

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Future Difficulties: Scaling

2003 2004 2005 2006 2007

DRAM ½ pitch (nm) 100 90 80 70 65MPU Physical Gate Length (nm) 45 37 32 28 25

From ITRS roadmap, 2003

…MRAM must compete with this (aggressive!) scaling to be viable

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Scaling Problem: Thermal StabilityAs bits get smaller: more susceptible to thermal fluctuations

Energy barrier proportional to volume, anisotropy: Must increase anisotropy to keep constant

Eb

E

θ

“0” “1”

0 π

Eb

E

θ

“0” “1”

0 π

But, bigger anisotropy—Need bigger fields to switch bit! Engineering problem…

Thermal fluctuations: Problem in hard disk media, read headsGeneral concern in nanoscale devices!

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Possible Solution: Spin TransferElectron spins become spin-polarized in direction of M: M exerts torque

Transmitted spins

Magnetization M1

Incident e- current

Reverse also happens: polarized spins exert torque on M

Torque

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Spin-Transfer-Driven SwitchingSign of torque depends on direction of current: Causes magnetizationmotion

-4 -2 0 2 4

7.35

7.40

7.45

7.50

7.55

7.60

7.65

dV/d

I (Ω

)

Current (mA)

Current-driven hysteretic switching

Free layer

Polarizer

Electron current

Bistable device: Current throughdevice drives switching

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High Speed ST-Switching

100 1000 10000

0.0

0.5

1.0

Sw

itchi

ng P

roba

bilit

y

Pulse Duration (ps)

7.8 6.2 4.9 3.9 3.1 2.5 2.2 2.0 1.8

Pulse Amplitude Current (mA)

-4 -2 0 2 47.1

7.2

7.3

7.4

7.5

dv/d

I (Ω

)

I (mA)

µ0H = 66.7 mT

30 nm

Katine HGST

0 -1 -2 -3 -4 -5 -6 -7 -8-0 .5

0 .0

0 .5

1 .0

1 .5

2 .0

2 .5

3 .0

3 .5

Q u a s i- s ta t ics w itc h in g c u r re n t

1/τ 95

(ns-1

)

I (m A )

<300 psswitching time!

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Spin Transfer Advantages

IhardHhard

Heasy

MTJ bit

X• Removes X-point field lines—

simpler lithography, two terminal devices

• Becomes more efficient as devices shrink: Scalable

Spin Transfer: ~1/d2Fields: ~1/d

ddd

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Spin-Transfer-Driven Oscillators

Monostable device (high fields): Current-tunable, Coherent, microwave

magnetization precession

applied field H16.00 16.25 16.50

0100200300400500600700800900

100011001200

Pow

er (p

W)

Frequency (GHz)

Cur

rent

(mA

)

8

3

5

µ0H = 0.9 TElectron current

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SummaryMRAM is possible “universal” memory solution

• “Spintronic” device: Uses e- charge and spin• Fast (3-10 ns switching times)• Nonvolatile (magnetic storage)• Low power (no refresh)• Rad-hard (though supporting electronics aren’t!)

Toggle MRAM solves ½-select problemProblem: Must scale competitively with Si technology

• Nanomagnetic elements sensitive to temperature• Complicated lithography

Emerging technology solution: Switching with Spin-polarized electron currents

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A Brief History of MRAM

BIWB Core memory, first disk drive, flat film, bubble, plated wire

1984-86 A. V. Pohm and Honeywell investigating radiation hard memory based on anisotropic magnetoresistance (AMR)

1987 GMR Discovered: Binash, Grunberg et al, PRB B 39, 4828 (1989); Baibich, Fertet al. PRL 61, 2472 (1988).

1989 NVE formed to develop AMR based MRAM

1990 IBM Spin Valve (B. Dieny, V Speriosou, S. S. Parkin, B Gurney et al.)

1994 IBM Spin valve MRAM patent (D. D. Tang et al. IBM)

1995 Magnetic Tunnel Junctions (MTJ) (Modera et al PRL 74, 3273, 1995)

1996 DARPA MRAM program: Honeywell (PSV), Motorola (PSV⇒MTJ) IBM (MTJ)

1999 IBM, Motorola MRAM working demos??

2002 Motorola goes to cladded write lines & tToggle write

2004 Motorola samples 4M MRAM chip

2004/2005 230% TMR in MgO MTJs; Spin transfer switched MRAM

1991 IBM fir

st hard-disk

MR head

1998 IBM intro

duces first

GMR head

1984 IBM fir

st tape M

R head