1

Introduction toCMOS VLSI

Design

MOSFETs Lecture B

Peter KoggeUniversity of Notre Dame

Fall 2015,2018

Based on material fromProf. Jay Brockman, Joseph Nahas: University of Notre Dame

Prof. David Harris, Harvey Mudd Collegehttp://www.cmosvlsi.com/coursematerials.html

CMOS VLSI DesignMOSFETs-B Slide 2

Outline Lecture A

IEEE Notation and IV curves

MOS Gate

Water Model

nMOS Ideal Long Channel I-V Model

Supplementary Material – More Careful Computation

Lecture B Reading the I-V Curves

Sample Technologies

Load Lines and an NMOS Inverter

A CMOS Inverter

Lecture C DC Transfer Curves for an Inverter

Ideal vs Real

Real-World Effects

2

CMOS VLSI Design

Reading the IV Curve

MOSFETs-B Slide 3

CMOS VLSI Design

Summary: Long Channel Model

MOSFETs-B Slide 4

0, Vgs < Vt Cutoff

β(VGT – Vds/2 )*Vds, Vgs > Vt and Vds < Vdsat Linear

βVGT2 / 2, Vds > Vdsat Saturation

Ids =

Where:• Cox = εox / tox

• β = (ox*/tox)*(W/L) = Cox**W/L• VGT = Vgs – Vt

• Vdsat = VGT

William Shockley 1st order transistor models1952 A Unipolar Field Effect Transistor

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9

polysilicongate

3

CMOS VLSI DesignMOSFETs-B

Cutoff

Saturation

Slide 5

CMOS VLSI Design

pMOS Curve is in Opposite Quadrant

MOSFETs-B Slide 6

http://www.physics.csbsju.edu/trace/i/pMOSFET5.plot.gif

4

CMOS VLSI Design

Reading The GraphVgs(V) Vds(V) Ids(uA) Region

?

0.8 0

0.8 0.2

0.8 0.4

0.8 0.6

0.8 1

0.8 650

0.8 110

0.1 0.2

0.1 1

MOSFETs-B Slide 7

0

100

200

300

400

500

600

700

0 0.2 0.4 0.6 0.8 1 1.2

Ids (uA)

Vds (Volts)

NMOS Device 1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

• β = 242• Vt = 0.7

CMOS VLSI DesignMOSFETs-B Slide 8

Understanding The I-V Graph:Fixed Vgs

AMI 600nm example

tox = 100 Å = 10 nm

= 350 cm2/V*s

Vt = 0.7 V

If we fix Vgs, the device looks like a non-linear resistor E.g. Vgs = 4V

In saturated region: ~ 1.25maconstant current

In linear region: ~2.5V/0.00125 ma = 2KΩ 0 1 2 3 4 5

0

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1

Vds

Id

Vgs

(2.5V, 1,25ma)Saturated

5

CMOS VLSI Design

Let’s Check the Equation:Fixed Vgs

MOSFETs-B Slide 9

0, Vgs < Vt Cutoff

β(Vgs – Vt – Vds/2 )*Vds, Vgs > Vt and Vds < Vdsat Linear

= (–β/2)* Vds2 + β(Vgs – Vt) *Vds

= -121*Vds2 + (242Vgs – 169) *Vds

β((Vgs – Vt )2 / 2, Vds > Vdsat Saturation

= a constant

Ids =

CMOS VLSI DesignMOSFETs-B Slide 10

Understanding The I-V Graph:Fixed Vds

Same technology as before

If we fix Vds, then Ids is a function of Vgs

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1

Vds

Id

Vgs

0

200

400

600

800

1000

1200

1400

1600

1800

0 1 2 3 4 5 6

Ids (uA)

Vgs (V)

Vgs (V): 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Ids (uA): 0 0 11 77 204 391 628 870 1111 1353 1595

Interesting Region: almost linear voltage to current conversion

6

CMOS VLSI Design

Let’s Check the Equation:Fixed Vds

MOSFETs-B Slide 11

0, Vgs < Vt Cutoff

β(Vgs – Vt – Vds/2 )*Vds, Vgs > Vt and Vds < Vdsat Linear

= (β *Vds )*Vgs – (Vt + Vds/2 )*Vds

β((Vgs – Vt )2 / 2, Vds > Vdsat Saturation

= (β/2)Vgs2 – (β Vt ) Vgs + (β/2)Vt

2

Ids =

CMOS VLSI Design

Knobs for Designers to Change

Typically logic designer has no control over εox : thin ox permittivity

tox: thickness of oxide

: mobility

Vt : threshold voltage

Only knobs left to change Overall Vdd: but usually selected at system level

L: length – but there is a minimum (2λ)

W: width

MOSFETs-B Slide 12

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

polysilicongate

7

CMOS VLSI Design

Example: Doubling W Approximately Doubles Current

MOSFETs-B Slide 13

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device 5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

W = 2* LengthW = Length

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device 5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

CMOS VLSI Design

SampleTechnologies

MOSFETs-B Slide 14

8

CMOS VLSI Design

Approximating the ND Process L = 2000nm

W/L = 10

tox = 2Å = 20 nm

= 350 cm2/V*s

Vt = 0.5 V

εr = 3.9

MOSFETs-B Slide 15

0

1000

2000

3000

4000

5000

6000

7000

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device 5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

The Model Output Spice Run from Prof. Snider

Real devices seem to have extra “Source Resistance” of about 120 ohms.Explains the difference.

CMOS VLSI DesignMOSFETs-B Slide 16

600nm AMI Semiconductor

tox = 100 Å = 10 nm

= 350 cm2/V*s

Vt = 0.7 V

εr = 3.9

ε0 = 8.85⋅10-14 F/cm

W/L = 4/2

WtoxL

350 3.98.85 1014

10 107

W

L

120

W

L

A

V 2

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

I ds (m

A)

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1

9

CMOS VLSI Design

180 nm NMOS Characteristics

MOSFETs-B Slide 17

SATURATION

2

2

224.0

V

mAVVVVI DS

DSTGSds

Ids(mA)

Vds (V)

Vgs = 5 V

Vgs = 4 V

Vgs = 3 V

Vgs = 2 V

Vgs = 1 V

Vds

Id

Vgs

CMOS VLSI DesignMOSFETs-B Slide 18

180 nm pMOS I-V All dopings and voltages are inverted for pMOS

Mobility p is determined by holes Typically 2-3x lower than that of electrons n

120 cm2/V*s in AMI 0.6 m process

Thus pMOS must be wider to provide same current In this class, assume n / p = 2

Vds

Vgsn5

Vgsn4

Vgsn3

Vgsn2Vgsn1

Vgsp5

Vgsp4

Vgsp3

Vgsp2

Vgsp1

VDD

-VDD

Vdsn

-Vdsp

-Idsp

Idsn

0

NMOS

PMOS

Vds

Id

Vgs

Id

Vgs

10

CMOS VLSI Design

The 65nm Process from p.67

MOSFETs-B Slide 19

tox = 10.5 Å = 1.05 nm

= 80 cm2/V*s;

Vt = 0.3 V

W/L = 2

εr = 3.9

0

20

40

60

80

100

120

140

0 0.2 0.4 0.6 0.8 1 1.2

Ids (uA)

Vds (Volts)

NMOS Device 1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

CMOS VLSI Design

Load Linesand An NMOS Inverter

11

CMOS VLSI Design

An NMOS and a Resistor Basic Resistor: VR = R*IR But in the Circuit:

Id = IR VR = VDD – Vds

Thus: Id = (VDD – Vds )/R

MOSFETs-B Slide 21

Vds

Id

Vgs

VDD

IRVR

Id

Vds

Vdd/R

Vdd

Id, Vds MUST be on this line,Regardless of Vgs

CMOS VLSI Design

Finding The Circuit I-VTo compute how circuit responds:

Overlay resistor on transistor IV

For each Vgs, find intersection

MOSFETs-B Slide 22

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device with R Pullup5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

R

R/4

4R

Vgs Ids (uA) Vds (V)

0 0 5

0.5 0 5

1 11 4.978

1.5 77 4.846

2 204 4.592

2.5 391 4.218

3 639 3.722

3.5 947 3.106

4 1238 2.524

4.5 1400 2.2

5 1550 1.9

R=2000 Ω

R=

2000 Ω

12

CMOS VLSI Design

Plotting The Results

MOSFETs-B Slide 23

0

1

2

3

4

5

6

0 1 2 3 4 5

Vds (V)

Vgs (V)R/4 R 4R

X

What is interesting about Vgs, Vds = 2.5V?

CMOS VLSI Design

Picking a Resistor Value What is Ids when Vds = Vgs = Vdd/2?

R = Vdd/(2Ids)

MOSFETs-B Slide 24

R=6.4K

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device with R Pullup5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

R

R/4

4R391nA.

2.5V/391nA = 6.4KΩ

R=25K

R=1.5K

Vgs Vds

0 5

5 0.7

0.7 5R

13

CMOS VLSI Design

What Is the Vgs = “1” Current?

MOSFETs-B Slide 25

R =

6.4K

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Ids (uA)

Vds (Volts)

NMOS Device with R Pullup5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

R

R/4

4R

~650uA

This represents a static power of ~3mw for just one gate!

Vgs

CMOS VLSI Design

A CMOS Inverter

14

CMOS VLSI Design

Now We Have 2 Transistors:Questions

Do we need load lines to determine output voltages if input is Either “0” (Ground)

Or “1” (Vdd)?

Is there any static power if input is either “0” or “1”?

Why then do we care about size (W/L) of each transistor?

MOSFETs-B Slide 27

VDD

A Y

GND

CMOS VLSI Design

A CMOS Inverter in Context

Downstream circuits look like a capacitor on inverter output All connected transistor gates

Wiring

Other (addressed later)

Thus Y looks like RC circuit With P-type the “pull-up” R

And N-type the “pull-down” R

To make rise and fall times approximately symmetric: Want Idsat of N & P types to be

equal

MOSFETs-B Slide 28

VDD

A Y

GND

15

CMOS VLSI Design

Let’s Look at the Equations

Vdd = Vgsp – Vgsn

Vdd = Vdsn – Vdsp

To make currents equal: Idp = -Idn

MOSFETs-B Slide 29

Vgsn

Vdsn

IdnA

Gnd

b+

− −+

Vgsp

Vdsp

Idp

Vdd

b+

− −+

Y

CMOS VLSI Design

Let’s Connect the N and P I-V Curves

MOSFETs-B Slide 30

Vds

Vgsn5

Vgsn4

Vgsn3

Vgsn2Vgsn1

Vgsp5

Vgsp4

Vgsp3

Vgsp2

Vgsp1

VDD

-VDD

Vdsn

-Vdsp

-Idsp

Idsn

0

NMOS

PMOS

Vds

Id

Vgs

Id

Vgs

Tough to find where equations satisfied.

16

CMOS VLSI Design

To Match Equations:Flip P-type IV and Move Right

MOSFETs-B Slide 31

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Id (uA)

Vds NMOS (Volts)

Inverter

54.543.532.521.510.50

Max Pull down Current

Max Pull Up Current

• Above is for identically sized N and P transistors• Remember: N and P mobility different

CMOS VLSI Design

What If We Make P type Wider by Same Factor as Mobility Difference

MOSFETs-B Slide 32

0

500

1000

1500

2000

2500

0 1 2 3 4 5 6

Id (uA)

Vds NMOS (Volts)

Inverter

54.543.532.521.510.50

Max Pull down CurrentMax Pull Up Current

17

CMOS VLSI Design

Rule of Thumb

To equalize currents, make average Idsat

for Pull-Down and Pull Up networks equal

Average difference in mobility is ~2

Thus for invertor: Make P-type twice as wide as N

MOSFETs-B Slide 33