mos ic amplifiers - archive.ece.cmu.eduee321/spring99/lect/lect24apr21.pdflecture 24-1 mos ic...
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![Page 1: MOS IC Amplifiers - archive.ece.cmu.eduee321/spring99/LECT/lect24apr21.pdfLecture 24-1 MOS IC Amplifiers • MOSFETs are inferior to BJTs for analog design in terms of quality per](https://reader033.vdocuments.us/reader033/viewer/2022042918/5f5ef7b40a21c454ba1bfea9/html5/thumbnails/1.jpg)
Lecture 24-1
MOS IC Amplifiers
• MOSFETs are inferior to BJTs for analog design in terms of quality per silicon area
• But MOS is the technology of choice for digital applications
• Therefore, most analog portions of mixed-signal designs are MOS
• Most MOS amplifiers will be IC amplifiers with “active” loads
• Resistors and decoupling capacitors are too expensive on ICs
Token Ring LAN JSSC 12/89
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Lecture 24-2
NMOS Amplifier --- Active Load
• Natural extension of amplifier with resistor pull-up
• Size M2 and bias M1 so that M1 is in saturation
• This is a digital NMOS logic gate when large input signals are applied
VDD
vi
iD1
vo
M1
M2 iD2
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Lecture 24-3
Load Line View
• “Load line” is nonlinear
M1-NMOSL=2UW=10U
D
S
+ 15VVDD
+
-VO
ID1
ID2
+ VO
M2-NMOS
L=10UW=2U
D
S
- +
3VVC27
0 10 20
0
10
20
mA
ID2 ID1
vo
VGS=3v
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Lecture 24-4
NMOS Amplifier Example
• For a larger dc input bias voltage M1 is no longer in saturation
0 10 20
0
10
20
mA
ID2 ID1
vo
VGS=5v
M1-NMOSL=2UW=10U
D
S
+ 15VVDD
+
-VO
ID1
ID2
+ VO
M2-NMOS
L=10UW=2U
D
S
- +
5VVC27
VGS=3v
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Lecture 24-5
Small Signal Model
• M2 behaves like a resistor in the small signal model
• Why?
gm1vivi ro1 gm2vgs2ro2
VDD
vi
iD1
vo
M1
M2 iD2
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Lecture 24-6
Small Signal Model
gm1vivi ro1 gm2voro2
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Lecture 24-7
NMOS Amplifier Example
• We would tend to lower the “resistance” of the pull-up transistor (increase K2), or decrease the current levels of the amplifier transistor (decrease K1) to keep M1 in saturation
• But these changes tend to lower the gain
0 10 20
0
10
20
mA
ID2 ID1
vo
K1
K1
K2
K2
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Lecture 24-8
NMOS Amplifier Example
• Design objective is to make K1 as large as possible, and K2 as small as possible, to get a reasonable gain
M1-NMOSL=2UW=10U
D
S
+ 15VVDD
+
-VO
ID1
ID2
M26-NMOS
L=10UW=2U
D
S
- +
SINVIN
frequencye2 e3 e4 e5 e6
13
DB(VO)
• Why the deviation from ideal gain?
4.47 v/v
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Lecture 24-9
Body Effect
VB
VGS > Vt
+
n+n+ QB0
VS>0 QI
VDS > 0
• For large signal behavior this is captured by the change in Vt based on the parameter, gamma
Vt Vt0 γ 2φf VSB+ 2φf–( )+=
• For discrete FETs there is no body effect since the source is tied to the body
• For ICs, all of the NFET body nodes are tied to the lowest potential in the ckt
• The source of our load transistor is not at the same potential as the substrate
• Source voltage partially modulates the channel --- back gate effect
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Lecture 24-10
Body Effect
VDD
vi
iDS1
vo
M1
M2
gm2vgs2
G
S
D
vgs2 ro2 gmbvbs2
+
_
vds2
+
_vbs2
+
_
B
M2
• The impact on the small signal model is a function of same parameters
• The change in vo (which is the source voltage) modulates the back gate
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Lecture 24-11
Common Source CMOS Amplifier --- Active Load
• Body effect is not as significant a problem for CMOS
• Current sources are used as pull-ups instead of resistors or load-transistors
• Having complementary types of transistors simplifies the implementation
• Is the body effect a factor for this amplifier?
+vi
_
IREF
+vo
_+
vi_
+vo
_
IREF
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Lecture 24-12
Common Source Small Signal Model
• Load line is now nearly a constant current --- huge gain
• What does the small signal model look like?
IREF +
vi_
+vo
_
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Lecture 24-13
Common Source Small Signal Model
IREF +vi
_
+vo
_
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Lecture 24-14
CMOS High Gain Region
• Input-output relation is very similar to a CMOS inverter
Vt = 1v K=100µA/V2 lamda=0.01
0 1 2 3 4 5
0123456789
1011
M1-NMOSL=10UW=10U
D
S
+ 10VVDD
+
-
VO
IDS
400UAIREF
M3-PMOS1L=10E-6W=10E-6
D
S
M2-PMOS1L=10E-6W=10E-6
D
S
- +
3VVI
VO
VI
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Lecture 24-15
CMOS High Gain Region
• What is the allowable range for vo and vi ?
1 2 3 4
0
1
2
3
4
5
6
7
8
9
10
11
VO
VI
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Lecture 24-16
ac Response
• Using an ac input with a 3 volt offset: Vt = 1v K=100µA/V2 lamda=0.01
frequencye2 e3 e4 e5 e6
30
31
32
33
34
35
36
37
DB(VO)
M1-NMOSL=10UW=10U
D
S
+ 10VVDD
+
-
VO
3.568 V
IDS
414.800 µA
400UAIREF
M3-PMOS1L=10E-6W=10E-6
D
S
M2-PMOS1L=10E-6W=10E-6
D
S
- +
SINVSSIN
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Lecture 24-17
Common Drain (Source Follower) Amplifier
• Source Followers are used for output stages
• Gain less than unity, but provides low output resistance to drive loads
100µA vi
vo
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Lecture 24-18
Common Drain (Source Follower) Amplifier
100µA vi
vo
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Lecture 24-19
Common Drain (Source Follower) Amplifier
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Lecture 24-20
Source Follower
• For an emitter follower, the gain is the voltage division of input resistance and emitter resistance
• But the source follower is somewhat different from an impedance reflection standpoint
VDD
-VSS
RL
vs I
• Small signal impedance looking into the gate appears as an infinite resistor, while that from the perspective of the source is finite
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Lecture 24-21
Small Signal Model
• Assuming that RLis infinite?