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7. Differential and Multistage IC Amplifiers TLT-8016 Basic Analog Circuits 2005/2006 1

7. Differential and Multistage IC Amplifier


7.1 Design Rules for Discrete and Integrated Circuits

Discrete circuits: the elements are manufactured separately and are mounted on a printed circuit board.

Integrated circuit: the elements and their interconnections are manufactured in a single semiconductor crystal.

The elements in an integrated circuit and the interconnections are realized by applying of a sequence of processing steps like : photolithography, doping, diffusion.

Strong restrictions about the values of the available elements in integrated circuit. See table 1.


Components and practical values of discrete circuits compared with those for IC

•Restricted types available•Good matching between devices in a chip

BJTs and FETs•Wide variety of types• Large unit-to-unit parameter variation

• 1nH .. 1µH; large area consuming• Tolerances: max few percents

Inductors•10nH .. 1H•Tolerances ±1% to ±20%

•0.1pF .. 100pF•Tolerances ±20%; good matching between C’s in a chip

•Special types not available

Capacitors•1pF .. 0.1F;•Tolerances ±1% to ±20%

•Low-temperature coefficient types available

•1Ω .. 100kΩ;•Tolerances ±30%; less than ±2% between R’s in a chip

•Special types not available

Resistors:•1Ω .. 20MΩ;•Tolerances ±1% or ±5%

•High power and low-temperature coefficient types available

Integrated CircuitsDiscrete Circuits


Process Complexity Matching of Device ParametersVery good matching between device parameters and characteristics in one chip. Relative variations not more that 2%.

Process: combination of steps for manufacturing of the IC.

More processing steps increase the price of the IC but gives high-quality IC.

Chip Area FETs Versus BJTs

BJT typically provide higher gain.

FET consume less chip area and static power dissipation is very small.

BiCMOS process.

Small chip area ⇒ cheaper IC.

Smallest chip area is consumed from the transistors. Largest area is consumed from inductors and capacitors.

Special circuit design is implemented, which avoids the capacitors and resistors. Inductors are used as exceptions – only in RF oscillators for GHz range.


7.2 IC Biasing with BJTsThe Current Mirror

Figure 7.1 The current mirror.

β/I

II refCC 2121 +

== (7.4)vBE of Q1 = vBE of Q2. Thus

(7.1)21 BB II = (7.5)refCC III ≅= 21

121 BCC III β== (7.2)

RVVI BECC

ref−

= (7.6)

211 BBCref IIII ++= (7.3)


Compliance Range and Dynamic Output Resistance

Figure 7.1 The current mirror.

Compliance range: the range of the voltage in the flat part of the V-A characteristics of the current mirror, in which the current is approximately constant.Dynamic output resistance:

1

2

2

−

∂∂

=CE

Co V

Ir (7.7)


An Example: Biasing of the Emitter Follower

Figure 7.2 Emitter follower with bias current source. The high dynamic resistance of the current mirror gives high input impedance of the emitter follower. The major restriction for the input impedance comes the load resistance RLoad.


Effects of the Transistor Area

11

22 CC I

AAI = (7.8)

Figure 7.4 Doubling the junction area of a BJT is equivalent to connecting two of the original BJTs in

parallel.


Exercise 7.2 Assuming identical npn transistors having equal areas, design a 1mA current mirror. The supply is VCC=15 V.

Solution:

kΩ3.14101

7.0157.0

mA1

31,

1

2,1,

=×−

=−

=

==

−QC

CC

QCQC

IVR

II

Figure 7.13 Answer for Exercise 7.2.


7.2 IC Biasing with FETs

Figure 7.15 NMOS current mirror. Figure 7.14 JFET as a current source. Since the device can operate with zeroVGS, the fixed VGS is achieved by short connection between gate and source.


7.4 Large-Signal Analysis of the Emitter-Coupled Differential PairBasic Operation

Differential and common mode input signals:

21 iiid vvv −=

( )2121

iiicm vvv +=

(7.23)11 CCCCo iRVv −=

(7.24)22 CCCCo iRVv −=

21 oood vvv −= (7.25)

( )12 CCCod iiRv −= (7.26)

Figure 7.22 Basic BJT differential amplifier (emitter-coupled pair).


Operation with Pure Common-Mode Input Signal

Because of the symmetry of the circuit, IEE splits equally between Q1 and Q2:

221 /Iii EEEE == (7.27)

221 /Iii EECC α== (7.28)

( ) 012 =−= CCCod iiRv

Figure 7.23 Basic BJT differential amplifier with waveforms.


Operation with a Pure Differential Input SignalPure differential signal: vi2 = -vi1.When vi1 > 0, vi2 < 0, thus iB1 increases and iB2 decreases.

BC ii β=

Thus iC1 increases and iC2 decreases.

CCCCo

CCCCo

RiVvRiVv

22

11

−=−=

Thus vo1 decreases and vo2 increases.

21 oood vvv −=

The amplitude of vod is doubled amplitude of vo1 and vo2.Detailed small-signal analysis shows that the differential voltage gain of the emitter-coupled pair is equal to the voltage gain of a single CE amplifier having the same BJT and RC.

Figure 7.23 Basic BJT differential amplifier with waveforms.


The Large - Signal Transfer Characteristic

−=

T

idCEEod V

vRIv2

tanhα (7.46)

( )Tid

EEC Vv

Ii/exp12 +

=α (7.44)

( )Tid

EEC Vv

Ii/exp11 −+

=α (7.45)

Figure 7.26 Voltage transfer characteristic of the BJT differential amplifier. Approximately linear dependence

vod(vid) takes place for |vid| < VT (26mV).Figure 7.25 Collector currents versus differential input voltage.


Emitter Degeneration

Figure 7.28 Voltage transfer characteristic with emitter degeneration resistors. REF = 40(VT/IEE). The amplifier is

linear for |vid| < 20VT.

Figure 7.27 Differential amplifier with emitter degeneration resistors.

Emitter degeneration improves the linearity but decreases the gain.


Balanced Versus Single - Ended Output

Figure 7.29 Either a balanced or single-ended output is available from the differential amplifier.

Balanced output requires next stage to be differential too.

Single ended output permits next stage to have a grounded input. The gain of the differential amplifier in this case is twice less.


Common-Mode Rejection Ratio (CMRR)

Accurate analysis shows that the differential emitter-coupled pair has small gain for the common-mode signal.

( )( )( ) EF

EBEF

v

vd

RrRRr

AACMRR

121

cm +++++

==β

β

π

π (7.69)

rπ - from the small-signal equivalent circuit of the BJT;β - common-emitter current gain;REF – emitter degeneration resistors;REB – equivalent dynamic resistance of the current mirror.

Emitter degeneration worsens CMRR.If REF = 0, the common-emitter gain β improves CMRR.The dynamic resistance REB of the current mirror improves CMRR too and must be higher.


7.8 Examples of Multistage IC AmplifiersA BJT Op Amp

Four stage dc coupled amplifier.1st stage: differential pair with balanced output. High input impedance, high gain and high CMRR.2nd stage: differential pair with single-ended output. Collector currents are 5 times more than in the 1st stage. Provides high output amplitude of the signal.3rd stage: CE amplifier with pnp transistor. Small gain (~3.5). High linearity. It restores the dc level at its output to be approximately 0.7V.4th stage: emitter follower. Buffer amplifier, no voltage gain. It provides low output impedance of the whole amplifier. Figure 7.55 A BJT op amp.

7. differential and multistage ic amplifier - tut · differential and multistage ic amplifiers...

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