module & sip thermal mgmt.10/19/2017 qualcomm confidential and proprietary 8 comparison to...
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Module & SiP Thermal Mgmt.Oct 19-20, 2017Shenzhen, China
Nader NikfarPrincipal Engineer/Mgr.Qualcomm Technologies, Inc.
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Agenda
• Module & SiP components
• Thermal management challenges
• Thermal performance of SiP◦ Module level
◦ System level
◦ Comparison to conventional architecture
◦ In mobile platform
• Conclusions
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Most SiPs are sub-systems for mobile devices
Module & SiPs
• SiP consists of
◦ Bare IC die
◦ Packaged IC die (2D/3D)
◦ SMT active and passive components
◦ Integrated passive devices (IPD)
◦ Embedded components
◦ Performance enhancements• Thermal lids
• Materials
◦ Thermal interface materials (TIM)
◦ Higher conductivity
• Shielding
• Stiffeners
Tracking devices
Smartphones
GPS SiPsRunning Monitors
WiFi/Bluetooth SiPsWearables
Tablets
3G/4G SiPsIoT/M2M
AutoUSB Dongles
POS
Examples of SiP
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Thermal mgmt. of SiP is more challenging than SoC
Thermal Mgmt. Challenges
• SoC thermal challenge is still there◦ Heat source non-uniformity
◦ Floor planning
◦ Maintaining max. Tj across various IPs on a small die
• Additionally for SiP◦ High-density integration of components (2/2.5/3D)
◦ More components, smaller XY, thinner Z, high performance and functionality
◦ Higher heat flux density and mutual heating
◦ Cooling budgets mostly based on natural convection
◦ Multiple heat sources within one entity and multiple max. Tjs
• Consequently◦ Thermally-aware design approach “a must” for success
◦ System-level thermal mgmt./solution very critical to success of SiP
Example layout of a SiP
Exploded view of a SiP
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Thermal Performance of SiP
SiP level knobs to improve performance
• Placement of ICs within SiP impacts the max. temp. of components• Proximity of hotter components
• Orientation
• Back to back placement (for double-sided designs)
• For higher-power chips, the conduction path to substrate must be
enhanced
• Enhance thermal conductivity of substrate by maximizing Cu content
along (X,Y,Z) as permitted by mechanical and electrical constraints
-4.0C
-1.3C
115.3C
Optimized placement impacts temp. distribution & magnitude
Enhance conductivity of substrate to maximize thermal performance
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Thermal Performance of SiPSiP level knobs to improve performance
• Encapsulating SiP improves thermal performance
◦ Lower max. Tj values
◦ Extends time-to-throttle
◦ Lower thermal gradient
◦ Creates a single elevation at each side for
coupling to heat sink
◦ Larger effective heat transfer area
25
35
45
55
65
75
85
95
105
115
0 30 60 90 120 150 180 210 240 270 300
tem
pe
ratu
re [c]
time [sec]POWER AMPLIFIER (NO MOLD)
POWER AMPLIFIER (w/ MOLD)
POWER AMPLIFIER (w/ CU-MOLD)
Temperature rise over time for non-molded vs. 2 molded options
Lower max Tj values (left to right: non-molded, conventional mold, highly conductive moldImproved
Conduction
LCD Glass
LCD Module
Backcover
Battery
SiP in a typical smartphone (dual-side heat sinking)
IC 2
PC
B
Single elevation when molded
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System Integration
Comparison to Conventional Architecture
IC 4IC 1
IC 2IC 3
PCB
IC 1PCB PCB
IC 4IC 3 IC 2 IC 1PCB PCB
IC 4IC 3 IC 2
180°
Substrate Substrate
Discrete SiP 1 SiP 2
Display module
Back cover
Screen
Mid-frame
Conventional chipset or SIP
Power distribution of chipset in Smartphone
810/19/2017 Qualcomm Confidential and Proprietary
Comparison to Conventional Architecture
IC 1 IC 2 IC 3 IC 4
Discrete 110.9 78.2 67.1 77.5
Module 1 92.2 65.7 61 73.9
Module 2 110.5 82.6 75.3 91.9
0
20
40
60
80
100
120
Te
mp
era
ture
(C
)
Steady state junction temperature
IC 4IC 1
IC 2IC 3
PCB
IC 1PCB PCB
IC 4IC 3 IC 2 IC 1PCB PCB
IC 4IC 3 IC 2
180°
Substrate Substrate
Conventional SiP 1
110.5
92.2
110.9
SiP 2
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Thermal Performance of SiPTest data in mobile platform
Same phone with
SiP (25x25mm)
Conventional phone
with discrete chips
-10 C
IR scans of conventional vs. SiP solution at same boundary conditions
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• Sip’s thermal performance as a standalone module (not heat sunk) isn’t good compared to conventional solutions
• Maximizing SiP’s thermal performance is a challenging task dependent on various variables:
◦ Components placement within SiP have to be analyzed to assure internal thermal performance of module is optimized
◦ Heat flux out of SiP should be maximized through both sides
◦ Coupling to system level thermal solution from both sides recommended (power dependent)
◦ The system thermal design and the placement of SiP within system impacts performance of SiP
• When above properly designed, SiPs thermal performance is better or equal to conventional solutions
• A thermally-aware design takes into account optimized chip and package-level heat transfer in addition to coupling
the SiP to a proper system level solution
• OEMs integrating SiPs into their platform:
◦ Co-design of system and coupling dynamics of SiP to system is a must for successful thermal performance
◦ Analyze heat transfer from SiP to ambient to assure thermal limits meet
• SiP's thermal performance is as good as system’s thermal solution
Conclusions
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AcknowledgementSpecial thanks to following individuals at Qualcomm Technologies, Inc.
• Yang Zhang
• Ryan Lane
• Bohan Yan
• Damion Gastelum
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