modern vlsi design 4e: chapter 6 copyright 2008 wayne wolf topics buses and networks-on-chips....
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Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Topics
• Buses and networks-on-chips.• Networks-on-chips.• Data paths.• Subsystems as IP.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus-based systems
• A bus is a common connection:
box1 box2 box3
ctrl
data
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus circuits
• Cannot support full connectivity between all data path elements—must choose number of transfers per cycle allowed.
• A bus circuit is a specialized multiplexer circuit.
• Two major choices: pseudo-nMOS, precharged.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Pseudo-nMOS bus circuit
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Precharged bus circuit
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Three-state bus
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Asynchronous timing constraints
• Must satisfy setup, hold times.
adrs
Setup timeHold time
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus system design
• Requirements:– Imposed by the other side of the system.
• Constraints:– Imposed by this side of the system.
a b
requirements
constraints
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
ba
Views of the bus
• Hardware:
D Q D Q
Combinationallogic
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Views of bus system, cont’d.
• Timing diagram:
ba
D Q D Q
Combinationallogic
x
y
x y
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus protocols
• Basic transaction:– four-cycle handshake.
a
b
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Handshake machine
• Each side is an FSM (possibly asynchronous):
a b0 1
Go
ackack
enq
0 1
enq
ack
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Basic protocols
• Handshake transmits data:
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Box 1 logic
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Box 2 logic
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus timing
td1 = d stable
td2 = d not stable
tc1 = c rises
tc2 = c falls
tack1 = ack rises
t1 = tc1 - td1 >= tr
t2 = tack1 - tc1 >= th
t3 = tc2 - tack1 >= th
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Busses and systems
• Microprocessor systems often have several busses running at different rates:
CPU
bridge
mem
I/O
High-speed
Low-speed
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Basic signals in a bus
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus characteristics
• Physical– Connector size, etc.
• Electrical– Voltages, currents, timing.
• Protocol– Sequence of events.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Advanced transactions
• Multi-cycle transfers:– Several values on one handshake.– May use implicit addressing.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PCI bus
• Used for box-level system interconnect.• Two versions:
– 33 MHz.– 66 MHz.
• Supports advanced transactions.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
PCI bus read
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Multi-rate systems
• Logic blocks running at different clock rates may communicate:– Multi-chip.– Single-chip.
» Slow bus connects to fast logic.
Logic 1 Logic 2
100 MHz 33 MHz
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Metastability
• Registers capturing transitioning signals may take an arbitrarily long time to settle.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Resynchronization
• Use cascaded registers to minimize the chance of using a metastable value.
D Q D Qd dout
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Networks-on-chips
• NoC is an on-chip interconnection network.– Bus is simplest case.– Many NoCs have multiple stages.
• Packet-based NoCs:– Nodes connected by links.– Packet may be divided into flits (flits are
always of equal size, packets may not be).
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus electrical model
core i
Length 1
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bus delay
• Major components of delay:– Drivers.– Bus backbone.– Sink capacitive loads.
• Delay formula:
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Crossbar
• Crossbar allows any combination of connections.
• Allows arbitrary multicasting.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Switch-based crossbar
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Mux-based crossbar
2-to-1 mux cell Mux tree
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Crossbar delay
• Switch-based crossbar dominated by buffered transmission line:
• Multiplexer-based crossbar delay:
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Network comparison
Type Delay
Bus O(N2)
Switch-based crossbar
O(sqrt(N))
Mux-based crossbar
O(log N)
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data paths
• A data path is a logical and a physical structure:– bitwise logical organization;– bitwise physical design.
• Datapath often has ALU, registers, some other function units.
• Data is generally passed via busses.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path logical organization
Registerfile sh
ifte
rmemory
constant
addresses Shift control
ALU op
carryout
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Register file porting
• Register file is an SRAM.• Additional ports add area, increase access
time.• But additional ports also reduce number of
cycles required for an operation.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Operand fetch from register file
+
1 port
First cycle
Second cycle
Third cycle
2 portsFirst cycle
First cycle
Second cycle
3 portsFirst cycle
First cycle
First cycle
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Register file tradeoffs
• SRAM delay grows approximately linearly in number of ports.
• Driver area grows considerably with added ports.
• At least two ports makes sense for data path through put.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path clocking
• Major signals: 1
2
– precharge s 1
– adrs s 2
– data v 2
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path timing
Registerfile sh
ifte
r
s 1
s 1
s 1
s 1
s 1
s 2
s 2
1 2s 2
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Typical data path structure
Slice includes one bit of function units, connected by busses:
registers shift ALUbus
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Bit-slice structure
• Many arithmetic and logical functions can be defined recursively on bits of word.
• A bit-slice is a one-bit (or n-bit) segment of an operation of minimum size to ensure regularity.
• Regular logical structure allows regular physical structure.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Abutting and pitch-matching
• Cells in bit-slice may be abutted together—requires matching positions on terminals.
• Pitch-matching is designing cells to ensure that pins are at proper positions for abutting.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path floorplanm
ux
latc
h
latc
h
mux
cons
tant
Reg
iste
r fi
le
shif
ter
AL
U
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Data path color plan
cell
VDD
VSS
result
Shifter input
Register file
control
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Subsystems as IP
• Standards for subsystems are more complex:– More variations.– More parameters.
• Open Core Protocol (OCP) defines socket for plug-and-play operation.
• SPIRIT defines standard documentation for subsystem IP.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Wishbone standard
• Basic unit is master-slave interface.– Defines handshake.
• Interface defines CLK, ADRS, DATA, WE, STB, ACK, CYC, RST.
• Three types of bus transfers: single read/write, block read/write, read/modify/write.
Modern VLSI Design 4e: Chapter 6 Copyright 2008 Wayne Wolf
Functional verification
• Particularly important for soft IP, but performed even for hard IP.
• Compare design module against known good design.
• QIP metric standard defines verification standards.
goldenreference
IPmodule
-inputvectors