MODELING AND SIMULATION OF GRAPHENE THREE BRANCH

JUNCTION USING VERILOG-A

CHIN EE MEI

UNIVERSITI TEKNOLOGI MALAYSIA

MODELING AND SIMULATION OF GRAPHENE THREE BRANCH

JUNCTION USING VERILOG-A

CHIN EE MEI

A project report submitted in partial fulfilment of the

requirements for the award of the degree of

Master of Engineering (Electrical - Computer & Microelectronics System)

Faculty of Electrical Engineering

Universiti Teknologi Malaysia

JUNE 2015

iii

To my beloved parents,

sister and brother,

for their love and support

iv

ACKNOWLEDGEMENT

First, I would like to express my gratitude to my family for giving strongly

support in all ways. I would like to take this chance to express my sincere gratitude

to my supervisors Dr. Shaharin Fadzli Abd Rahman, for his kindly support and

guidance. His patience and encouragement have provided valuable input into

completing the research project.

Least but not last, I would like to take this opportunity to thanks to my friends

for providing useful information and suggestion to this project.

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ABSTRACT

Graphene three-branch junction device (G-TBJ) is a non-conventional device

that offers promising potential in various application in digital (e.g. logic gates) and

analog (frequency mixer, etc) circuit. Operation of G-TBJ can be explained by a

capacitor-based equivalent circuit. However, the proposed equivalent circuit neglects

other device parameter and properties which can affect the characteristics of G-TBJ.

The main objective of this project is to investigate other device model consist of

graphene field effect transistor (G-FET). The feasibility of implementing of

embedded Verilog-A models to simulate TBJ was assessed. The device simulation is

performed using Quite Universal Circuit Simulator (QUCS). First, simulation results

of single G-FET is verified against with result measured from fabricated GFET in

experiment. Next, simulation is done at TBJ circuit level where two G-FET devices

are connected at two terminals. Simulation result shows that model which is

proposed and implemented in verilog-A has produced a close result with experiment

and simpler device physics formula to describe the operation principle of GFET.

Thirdly, TBJ is simulated as inverter. The inverter shows voltage gain of 0.0065 at

voltage supply of 0.1V.

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ABSTRAK

Graphene tiga cawangan peranti persimpangan (GTBJ) adalah peranti bukan

konvensional yang menawarkan potensi yang cerah dalam pelbagai aplikasi dalam

digital (contohnya litar logik) dan analog (frekuensi mixer) litar. Operasi GTBJ dapat

dijelaskan oleh litar setara berasaskan kapasitor. Walau bagaimanapun, litar setara

yang dicadangkan mengabaikan parameter peranti dan parameter lain yang boleh

memberi kesan kepada ciri-ciri GTBJ. Objektif utama projek ini adalah untuk

menyiasat model peranti lain terdiri daripada graphene kesan medan transistor

(GFET). Kemungkinan melaksanakan model Verilog-A untuk mensimulasikan TBJ

yang dinilai. Simulasi peranti dilakukan dengan menggunakan Quite universal circuit

simulator (QUCS). Pertama, keputusan simulasi tunggal GFET disahkan dengan

keputusan diukur mengukur peranti GFET dalam eksperimen. Seterusnya, simulasi

dilakukan di peringkat litar TBJ mana dua peranti G-FET disambungkan pada dua

terminal. Keputusan simulasi menunjukkan bahawa model yang dicadangkan dan

dilaksanakan dengan verilog-A adalah rapat dengan eksperimen dan lebih ringkas

untuk formula fizik peranti untuk menggambarkan prinsip pengendalian GFET.

Ketiga, TBJ disimulasi sebagai inverter. Inverter tersebut menunjukkan inverter

gandaan voltan daripada 0.0065 pada bekalan volt 0.1V.

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TABLE OF CONTENTS

CHAPTER TITLE PAGE

DECLARATION ii

DEDICATION iii

ACKNOWLEDGEMENTS iv

ABSTRACT v

ABSTRAK vi

TABLE OF CONTENTS vii

LIST OF TABLES x

LIST OF FIGURES xi

LIST OF SYMBOLS xv

LIST OF APPENDICES xvi

1 INTRODUCTION 1

1.2 Objectives 2

1.3 Scope of Work 2

1.4 Structure of Project 3

2 OVERVIEW OF GRAPHENE BASED DEVICE 4

2.1 Overview of Graphene 4

2.1.1 The Crystal Structure of Graphene 5

2.1.2 The Electronic Properties of Graphene 5

2.2 Graphene Field Effect Transistor 6

2.2.1 Device Structure 8

2.2.2 Current-Voltage Characteristics of

Graphene Transistor 10

2.2.3 Device Model Of Graphene Transistor 14

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2.3 Graphene Based Three Branch Junction

Device 17

2.3.1 Device Structure 17

2.3.2 Current Voltage Characteristics 18

. 2.3.3 Equivalent Circuit 19

2.3.4 Application of Three Branch

Junction 21

3 METHODOLOGY 22

3.1 Proposed Graphene TBJ Model 23

3.2 Project Workflow 26

3.3 Tools and Software 26

3.3.1 Verilog A Language Modelling 27

3.3.2 QUCS Studio 31

3.4 Schematic Circuit 31

3.4.1 QUCS Studio Verilog-A Compact Device

Modeling 31

3.4.2 Circuit Simulation 32

4 RESULT AND DISCUSSION 34

4.1 Case Study 1: Single GFET Model Validation 35

4.1.1 Circuit Schematic and Derived

Parameters 36

4.1.2 Result Discussion and Summary 37

4.2 Case Study 2: GFET based TBJ Model 37

4.2.1 Circuit Schematic and Derived

Parameters 38

4.2.2 Result Discussion and Summary 44

4.3 Case Study 3: GFET Based TBJ As Inverter 45

4.3.1 Circuit Schematic and Derived

Parameters 45

4.3.2 Result Discussion and Summary 46

5 CONCLUSION AND FUTURE WORK 49

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5.1 Future Work 55

REFERENCES 51

Appendices A-B 53 - 56

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LIST OF TABLE

TABLE NO. TITLE PAGE

3

3.1 Parameters extracted in simulated GFET model 29

4.1 Parameter defined for single GFET 39

4.2 Parameters extracted from experiment and

implemented in TBJ simulated model 43

4.3 Parameters extracted from TBJ modeling and

simulated as inverter 49

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LIST OF FIGURES

FIGURE NO. TITLE PAGE

2.1 Graphene structure 5

2.2 Graphene band structure 7

2.3 FET transfer characteristics showing ID (on a

logarithmic scale on the left and a linear scale on

the right) versus the gate–source voltage, VGS 8

2.4 Schematic of back gated MOSFET 10

2.5 Qualitative shape of the output characteristics

(drain current, ID, versus drain–source voltage,

VDS) of a MOSFET with an n-type large-area-

graphene channel, for different values of the top

-gate voltage, VGS,top 11

2.6 Comparison of drain current, log Id at different

back gate electric field with and without top gate 13

2.7 Comparison of study work by Gerhard Martin

Landauer, 2014. Drain current Ids versus drain

-source voltage Vds for varying back gate bias

voltage Vbs 14

2.8 Comparison of this GFET model to the transfer

characteristics of a 5 μm-GFET reported in

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Gerhard Martin Landauer (2004). 15

2.9 Graphene transistor with channel-access

resistances 16

2.10 A phenomenological circuit model to capture

asymmetry in the electron and hole branches of

current conduction in graphene (RHS) 17

2.11 Simulation of transfer characteristics of a GFET

with asymmetric Rhole and Relec 17

2.12 Schematic illustration of graphene TBJ (b) SEM

image of thE fabricated graphene-based TBJ

device. 19

2.13 Measured voltage transfer curves for various VBG,

(b) curvature at Vin=0V as a function of VBG, and

(c) input branch current-voltage characteristics 20

2.13 Equivalent circuit model for the graphene-based

TBJ device 21

3.1 Schematic of the GFET with various terminals

label 24

3.2 Proposed model for graphene TBJ with GFET

operation 25

3.3 Process Flow of graphene three branch circuit

modeling and simulation. 29

3.4 Excerpt of analog function simulated in GFET 30

3.5 Verilog-A implement for GFET module study 35

3.6 QucsStudio show verilog-A compact model for

three terminals GFET , named GFET attached with

C++ compiled model icon with parameters 36

3.7 Equivalent circuit schematic layout for the graphene 37

three branch junction

4.1 Schematic diagram of single GFET 40

4.2 Simulation Id- Vg result of Single GFET 42

4.3 Comparison n transfer characteristics result of

simulated 43

4.4 Single GFET in experiment 43

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4.5 Schematic diagram of TBJ 44

4.6 Simulated result of TBJ 44

4.7 Vout – Vs transfer characteristics comparison with

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experiment result at Vg=-6V 44

4.8 Vout – Vs transfer characteristics comparison with

experiment result at Vg=-4V 45

4.9 Vout – Vs transfer characteristics comparison with

experiment result at Vg=-2V 45

4.10 Vout – Vs transfer characteristics comparison with

experiment result at Vg=0V 46

4.11 Vout – Vs transfer characteristics comparison with

experiment result at Vg=2V 46

4.12 Vout – Vs transfer characteristics comparison with

experiment result at Vg=4V 47

4.13 Vout – Vs transfer characteristics comparison with

experiment result at Vg=6V 47

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LIST OF SYMBOLS

R - Resistor

L - Length

W - Width

Vth - Threshold Voltage

m - Mass

V - Voltage

I - Current

C - Capacitance

g - Gate terminal in field effect transistor

d - Drain terminal in field effect transistor

s - Source terminal in field effect transistor

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LIST OF APPPENDICES

APPENDIX TITLE PAGE

A Case Study 2: Simulation Result using QUCS 54

B Verilog A code from S.Rakheja work 56

CHAPTER 1

INTRODUCTION

Three-branch junction device (TBJ) is a non-conventional device which

operates in ballistic transport [1]. The advantages of the TBJ is simple structure, high

frequency operation and low power consumption. Demonstration of TBJ has been

done using high mobility-semiconductor such Gallium Arsenide, Indium Gallium

arsenide, graphene. TBJ can be used in many applications in digital (e.g. logic gates)

and analog (frequency mixer, etc) circuit [1].

In this study, possible application of graphene TBJ with well controlled gate

voltage is studied in application as logic circuit. Three-branch junctions have been

found featuring unique nonlinear electrical characteristics. Nonlinear voltage

characteristics or “V” curve have been observed at graphene TBJ dirac point [2].

However, study on graphene-TBJ is quite new and not much on the

application of graphene TBJ. MOSFET model equivalent circuit has been proposed

for graphene TBJ simulation work. The proposed MOSFET current model is for zero

bandgap graphene with backgate voltage controlled structure. In order to control the

nonlinear electrical characteristics, critical parameters such as graphene FETs device

size, oxide thickness and other key parameters are discussed in this study. The circuit

simulation result was presented.

2

1.1 Objectives

The objective of this research study is to assess the proposed device model

for TBJ device. The second objective is to simulate a logic circuit using the proposed

circuit model.

1.2 Scope of Work

In this project, MOSFET device model was proposed for graphene three

branch junction simulations. Verilog-A modeling language which absorb analog

capability was carried out for device modeling activity in this project. Circuit was

modeled with QUCS open software.

The non linear electrical characteristics of three branch junctions are looked

into. The scope of study mainly focuses on the characterization of transfer

characteristics and drain current model at TBJ at dirac point, from the aspects of

oxide thickness and device size with different backgate voltage applied. Furthermore,

feasibility and performance of the proposed application was investigated.

1.3 Sructure of Project

This project comprises five chapters. The first chapter is the introduction of

research. A statement of the objectives and scope of this project is also presented.

The second chapter consists of three parts of literature review. Part one is

the basic of graphene including its crystal structure of graphene and electronic

characteristics. The next two parts include graphene field effect transistor review and

graphene based three branch junction device.

3

The third chapter deals with methodology and simulation process flow. In

chapter four, results and discussion are carried out. The modeling methods and the

simulation results as well as drain current versus gate voltage will be presented and

analyzed. Lastly, in chapter five, a set of conclusions is presented.

51

REFERENCE

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Application. Springer-Verlag Berlin Heidelberg . 2012.

2. Zhiyong Zhang, H. X.-M. Direct extraction of carrier mobility in graphene field-

effect transistor using current-voltage and capacitance-voltage measurements.

Appl. Phys. Lett. 2012 .

3. Schwierz, F. Graphene Transistor. Nature Nanotechnology. 487-496. 2010.

4. Davide Mencarelli and L. P. Nanoscale Simulation of Three-contact Graphene

Ballistic Junction. Nanomaterials and Nanotechnology. 1-7. 2010.

5. Beibei Zhan, C. L. Graphene Field-Effect Transistor and Its

Application. Key Laboratory for Organic Electronics & Information Displays

(KLOEID), Nanjing University of Posts and Telecommunications, Nanjing.

2014.

6. P.K. Ang, A. L. Flow Sensing of Single Cell by Graphene Transistor in a

Microfluidic Channel. Nano Letters . 2010.

7. T. Q. Trung, N. T. A Flexible Reduced Graphene Oxide Field‐Effect Transistor

for Ultrasensitive Strain Sensing. Advanced Functional Materials. 2014.

8. Rakheja, S. An Ambipolar Virtual-Source-Based Charge-Current

CompactModel for Graphene. IEEE . 2014.

9. Xiang Yin and Seiya Kasai. Graphene-based three-branch nano-juction (TBJ)

logic inverter. Physica Status Solidi. 2013.

10. K. S. Novoselov, A. K. Graphene: A Future Material. Science. 306. 2004.

11. Seyoung Kim, Junghyo Nah, Insun Jo, Davood Shahrjerdi, Luigi Colombo, Zhen

Yao. Realization of a high mobility dual-gated graphene field-effect transistor

with Al2O3 dielectric. 2009.

12. Lemme, M. C. A Graphene Field-Effect Device. IEEE. 2007.

13. Shaharin Fadzli Abd Rahman and Seiya Kasai. Room temperature nonlinear

operation of a graphene-based three-branch nanojunction device with chemical

doping. Applied Physics Letters. 2012,

14. Ohno Y. M. Label-Free Biosensors based on Aptamer-modified Graphene Field-

Effect Transistors. Nano Lett.. 2009.

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15. Gerhard Martin Landauer and D. J. 2014. An Accurate and Verilog-A

Compatible Compact Model for Graphene Field Effect. IEEE . 2014.

16. S. Goodnick and J. Bird. Quantum-Effect and Single-Electron Devices,

IEEE Transactions on Nanotechnology 2. 368. 2003.

17. Jie Sun. Semiconductor Nanoelectronic Devices Based on Ballistic and

Quantum Effects. Lund University, Sweden. 2009.

18. Xiang Yin and Seiya Kasai. Fabrication of Graphene-based Three-branch Nano-

junction (TBJ) and its Application to Logic Circuits. IEICE Technical Report.

2013.

19. S. Rumyantsev. Electrical and Noise Characteristics of Graphene Field-Effect

Transistors: Ambient Effects, Noise Sources and Physical Nechanisms.

University of California. 2010.