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Stephan Henzler Mixed-Signal-Electronics 2011/12

Mixed-Signal-Electronics

PD Dr.-Ing. Stephan Henzler

1


Nyquist Rate

Analog-to-Digital Converters

2

Chapter 6


Analog-to-Digital Converter Families

Sampling frequency can be further increased by

– pipelining

– time interleaving, i.e. parallelization

3

Architecture Variant Speed Precision

Counting Operation single/dual slope integration low high

Weighted Operation successive approximation

algorithmic converter

w/wo redundancy, callibration

medium medium

Flash Operation • direct flash

• multi-stage flash

• interpolating flash

• folding flash

high low to medium

Oversampling -modulation, i.e. noise shaping

• discrete time

• continuous time

low to medium high

Time based emerging tbd. tbd.

Stephan Henzler Advanced Integrated Circuit Design 2011/12

General ADC Model

Linear model

often very useful

limitations as quantization

noise is de-correlated from

signal

Input signal must change

– sufficiently fast

– sufficiently strong

4


Dual-Slope Analog-to-Digital Converter

5


Dual-Slope Analog-to-Digital Converter

6


Iterative Analog-to-Digital Converters

Tracking ADC

Successive Approximation ADC

Algorithmic ADC

Pipeline ADC

7


Tracking ADCs

8


What would you ask if you had N questions to find out the

approximate value of the input voltage?

Converter with Successive Approximation

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1. Is it positive or

negative?

NEGATIVE

2. Is it in the upper or

lower negative region?

UPPER

3. …


This is a binary search technique:

Partition the interval where the input voltage is located in two sub-intervals and

check whether the voltage lies in the upper or lower part


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11


Converter with Successive Approximation (cont)

ADC is mainly a DAC and a comparator

(These are the critical building blocks)

Conversion principle:

Make DAC voltage equal to input voltage, minimize error

Depending on the voltage comparison the bits in the SAR

register are iteratively set or reset

12


Modified SAR Algorithm

Also based on binary search

technique

Comparison against zero

More suited for

implementation,

e.g. charge redistribution

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Modified SAR Algorithm

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Charge Redistribution SAR Converter

Phase I: Input Tracking

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Phase II: Hold

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Phase III: SAR Evaluation

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Phase III: SAR Evaluation

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Hybrid SAR Converters

Search can be done with different

references

Same idea as for DACs

– monotonous resistor string for MSBs

– binary weighted cap array for LSBs

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Add-On Material

1. Charge caps to -vin

2. Binary search in resistive

network: vx = -vin + vres

3. Interpolate in between two

subsequent taps of resistor

string by charge redistribution


More Details on SAR and Algorithmic ADC

Architectural Considerations on SAR

Pipelined SAR

Redundant SAR

20

Remember:

The goal is to make this

error voltage

equal to zero


Detailed SAR Architecture

Let’s look at the DAC in detail …

Thermometer Coding

Each DAC has same error contribution

Remainder:

21

Aaron Buchwald, Pipelined A/D Converters: The Basics, ISSCC 2008


Binary Weighted SAR

Binary weighting is desirable to reduce number of sub-DACs

Remainder:

Error contribution due to DAC mismatch scales with binary

weigting of reference

22


Binary Weighted SAR

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Weighted SAR with Distributed Gain

Binary weighting can be achieved also by using equal DACs

with a single reference voltage but with gain / scaling

elements

Due to scaling MSB DAC is most critical

Linear transformation enables distributed gain

24


Algorithmic Analog-to-Digital Converter

Comparator threshold constant

Voltage increment/decrement

constant

remainder is doubled in each

iteration step

accurate x2 circuit required

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26


Robertson Diagram

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Illustration in Robertson Diagram

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1.

2. 3. 4.

5.



Long conversion time

N cycles per inout sample

29

ADC

DAC

Lecturer Page Version


Voltage Doubling in Algorithmic Converter

Sample remainder Verr together with opamp offset voltage

Amplifier configured as voltage follower

C2 charged to amplifier offset voltage

30

Add-On Material

V1

V2



Disconnect input, discharge C1

Transfer charge of C1 to C2

31

Add-On Material

V1

V2



Disconnect C2, charge Q2 unchanged

Sample input again

32

Add-On Material

V1

V2



Combine charge on C1, offset compensated,

Four clock cycles required! 33

Add-On Material

V1

V2


Weighted SAR with Distributed Gain

Algorithmic converter in unfolded implementation

Long conversion time

N x TADC + N x TDAC

Speed-up by insertion of ADC and S&H in each stage

pipelining: high throughput at the price of latency

34


Pipelined ADC 1

Going for pipelined-ADC means

– cut the feed-back loop

– add a sample-and hold at the output of each stage to store

the remainder, i.e. the stage quantization error

– add a comparator, i.e. coarse ADC at input of each stage

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Pipelined ADC 2

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mixed-signal-electronics · general adc model linear model ... stephan henzler mixed -signal...

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