xilinx training xilinx analog mixed signal edk design flow note: agile mixed signal is now analog...
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Xilinx Training
Xilinx Analog Mixed Signal EDK Design Flow
Note: Agile Mixed Signal is Now Analog Mixed Signal
Welcome
This module introduces the EDK flow for Xilinx Agile Mixed Signal solutions
This module will list some key features of the XADC core that are enabled by Xilinx Agile Mixed Signal solutions
To Learn More About Xilinx Agile Mixed Signal
Related Videos– What is the Xilinx Agile Mixed Signal Solution?
• For beginners and enthusiasts
– Xilinx AMS HDL Design Flow• For digital designers who want to become familiar with HDL flow
– Xilinx AMS XADC Evaluation• For designers who want to know how the XADC interface can be evaluated for
their mixed signal application
1. Evaluate 2. Implement 3. Simulate
Implementing XADC in your Design
1. Evaluate
• XADC evaluation card is bundled with all 7 series TDPs • Choose XADC
settings and begin measuring
2. Implement
• Set attributes based on evaluation and connect I/O
• MicroBlaze processor initializes XADC settings at run time
3. Simulate
• Simulate HW (XADC & FPGA logic) using analog stimulus file
• Use HW in the loop with ISim to verify prototype
Edit Settings
Evaluating the XADC
KC705
USB
123.456
Optional External Instrument(e.g. signal generator)
Resources (DACs) for basic testing andconnectors for external instruments
#1
Ribbon cable connectionto “analog header” on KC705
National Instruments LabView GUI• XADC settings
• ADC data collection and analysis
XADC Evaluation Card
XADC-AXI IP Overview
Customizable
Fully tested, documented, and supported by Xilinx
Unlicensed and provided for free with Xilinx software
AXI4-Lite Interface
XADC Core Logic
XADC Hard Macro
XADC-AXI IP for ZynQ-7000 EPP and the MicroBlaze Processor
Embedded Design Kit Suite
Xilinx Platform Studio (XPS)– Design environment for processor
subsystem– Microprocessor Hardware Specification
(MHS) file– ChipScope™ Pro logic analyzer
integration
Software Development Kit (SDK)– Project workspace – Board Support Package (BSP)– Software application– Software debugging
Adding the XADC-AXI IP
Customize the XADC core
here
Adding the XADC-AXI IP (continued)
XADC-AXI IP Product Guide
XPS Design Flow
Perform Design Rule Check
(DRC)
Generatehardware
Export hardware platform
information to SDK
XADC block diagram and its connections
as seen in EDK
SDK Integration
Drivers included with
BSP
system.xml contains the hardware configuration
Application Development Driver Documentation
Driver API documentation
Simulation in XPS
The Simulation Model Generator (SimGen) tool generates and
configures various simulation models for the specified hardware
Launches SimGen(integrated in
XPS)
Enables coverfication of hardware and software when
run in ISIM
Launches ISim (integrated in
XPS)
Scripts for third-party simulators
Enables co-verfication of hardware and software when
run in ISim
Simulation and Verification
Text file contains analog information (sensors, external voltages, etc.) thatcan be introduced into the simulation
Simulate XADC (Analog) and Digital
Associating Analog Stimulus
Associating analog stimulus file to the XADC model
C_SIM_MONITOR _FILE parameter in the system.mhs file
Performing ELF Simulation Example
XADC-AXIModel
ELF Simulation
Stimulus File Example
Analog information readin directly by model
Summary
1. Evaluate the XADC for performance and settings– XADC Evaluation Card is bundled with all 7 series TDPs (e.g., KC705)– Pick required XADC settings (attributes) and evaluate performance
2. Implement the design using the XADC AXI core – Add the XADC AXI core to your embedded platform using Xilinx Platform Studio– Synthesize and implement the design using XPS and import the hardware
settings to SDK– Using SDK, generate board support packages and develop applications that
leverage the XADC block
3. Simulate the XADC in an HDL simulator– XPS enables co-verification of hardware and software for embedded designs– SimGen generates Verilog or VHDL models for XADC– Support for analog test vectors using an analog stimulus file
Where Can I Learn More?
Learn more at www.xilinx.com/AMS– Agile Mixed Signal white paper (WP392)– XADC User Guide (UG480)
Visit www.xilinx.com/innovation/7-series-fpgas.htm– Application examples – New 7 series documentation
Xilinx training courses– www.xilinx.com/training
• Xilinx tools and FPGA architecture courses• Hardware description language courses• 7 series design courses• Basic FPGA architecture, basic HDL coding techniques, and other free Videos
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