mipi i3c interface –advanced features...delay time [dt] in-band, via i3c bus all read in sync...
TRANSCRIPT
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Radu Pitigoi-AronPrincipal Engineer, Systems Architect
QUALCOMM Technologies, Inc
MIPI I3C℠ Interface – Advanced Features
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Outline
• MIPII3C℠ – intelligentmultifeaturedinterface• Listofmainbusmanagementprocedures• TimingControl– Problemssolved,Challenges,Practicalimplementationaspects
• Elementsofflowcontrol– Problemssolved,Challenges,Practicalimplementationaspects
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MIPII3C℠BusClients
3
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MIPII3C℠– IntelligentMultifeaturedInterface
4
• MIPII3C℠supportsseveralcommunicationformats,allsharingatwo-wireinterface.– ThetwowiresaredesignatedSDAandSCL:
• SDA(SerialData)isabidirectionaldatapin• SCL(SerialClock)canbeeitheraclockpinoradatapinwhileincertainHDRModes
• AnMIPII3C℠Bussupportsthemixingofvarious Messagetypes:– I2C-likeSDRMessages,withSCLclockspeedsupto12.5MHz– BroadcastandDirectCommonCommandCode(CCC)MessagesthatallowtheMastertocommunicatetoall
oroneoftheSlavesontheI3CBus,respectively– HDRModeMessages,whichachievehigherdataratesperequivalentclockcycle– I2CMessagestoLegacyI2CSlaves– Slave-initiatedrequeststotheMaster,forexampleforIn-BandInterruptortorequesttheMasterrole
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MIPII3C℠BUSManagementFeatures• DynamicAddressAssignment• Hot-Join• In-BandInterrupt• SecondaryMaster• In-BandHardRESET• TimingControl• CommonCommandCodes• ErrordetectionandRecovery• ElementsofFlowControl
5
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TimingControl• ComplexapplicationsrequireseveralSensorsonacommon
timeline• SynchronousSystemsandEvents
– Controllingthesamplingmomentshasthepotentialofdrasticallyreducingthesystemenergyexpenditure
• AsynchronousSystemsandEvents– Theaccuracyofthetimestampsofeventsmatters
• TheSynchronousandAsynchronousmodescanbeusedindependentlyandconcurrentlyonthesamebusanddevices
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SynchronousSystemsandEvents
7
S_RED
ST+DT
S_GREEN S_BLUE
SENSORSREADNOTINSYNC
SYNCTick[ST]andDelayTime[DT]
in-band,viaI3Cbus
ALLREADINSYNC
SequenceRepetitionPeriodAdjustable[0.2;5sec],1secnominal
Sequencerepeats
T_Phstart T_Phstart
SENSORSDATANOTINSYNC
ALLDATAINSYNC
ST+DT
DT
Sensorssample Sensorssample Sensorssample Sensorssample Sensorssample Sensorssample
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Synchronous– MultipleTransactions
8
SequenceRepetitionPeriodAdjustable[0.2;5sec],1secnominal
I3Cmessages,onthebusSomeI3CtransactionsSTARTconditionisusedbytheSlaves(sensors)foradjustingtheir(sensors’)internaltimers
Sequencerepeats
ST&DTtonextST&DTdelayAdjustable[0.2;5sec],1secnominalEachST&DTinstantiationincludesTimerErrorCorrectiondata
ST&DTPolling
Pollingorsomething
else
I3CSTART
SensorsSample
unsynchronized
STifvalidatedbyDT
I3CSTART I3CSTART I3CSTART
Pollingorsomething
else
ST&DTPolling
T_Phstart,calculatedfromSTandDT
STifvalidatedbyDT
T_Phstart,calculatedfromSTandDT
Refresh/AdjustSensor’sTimer
DTbetweenSTandT_PhStart
SyncTick[ST]&DelayTime[DT]
SyncTick[ST]&DelayTime[DT]
SensorsSample
unsynchronized
SensorsSample
unsynchronized
SensorsSampleinsync
SensorsSampleinsync
SensorsSample
unsynchronized
SensorsSampleinsync
SensorsSampleinsync
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Synchronous– CommonCommandCodes• SETXTIMECCC• Configurationmessages
– ODR(OutputDataRate)– TPH(ProcedureRepetitionTime)– TU(TimeUnit)
• RunTimemessages– SYNCTick[ST]– DelayTime[DT]
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AsynchronousSystemsandEvents• FourAsyncModes
– Basic– AsyncMode0– Enhanced– AsyncMode1,2and3
• SETXTIMEistheCCC– Thedefiningbyteselectstherunningmode
10
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Async0TimeDiagram
11
SENSORSAMPLE
1STHWEVENT
2NDHWEVENT
Sensor’sSCNT1Start Sensor’sCNT2Start
SC1captured SC2captured
Master’sMCNT2Start
MREFcapturedMaster’sTimestampMTS MC2captured
VirtualMC1
Sensor’sclockfortimer/counter
Master’sclock/virtualclockfortimer/counter
Master’sclockfortimer/counter
SensorInitiatesIRQ
MTS=MREF–MC2×SC1/SC2
Timeline
MASTER
SENSOR
Sensor’sclockfortimer/counter
MTS – MasterTimestamp,expressedinMASTER’stimeunits
MREF – MasterReference,i.e.StartofMaster’ssecondarycounter,MCNT2
MC1,MC2– Master’scountersvalues,capturedatthecorrespondingHWSE events.
SC1,SC2– Slave’scountersvalues,capturedatthecorrespondingHWSE events.
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Async0onSDR
12
R TACK
S S_ADDR IBI R ISR Read T SC1 Byte1 T SC1 Byte2 T SC2 Byte1ACK
ISR ReadSC1
Byte1
First SCL Rising Edge After ACK or T Bit
T
MASTER
SENSOR
SENSOR SAMPLE 1ST HW EVENT 2ND HW EVENT
Virtual MC1
Sensor’s SCNT1 Start Sensor’s SCNT2 Start
SC1 Captured SC2 CapturedSensor Initiates IRQ
Sensor’s Clock for Timer/Counter Sensor’s Clock for Timer/Counter
Master’s MCNT2 StartMREF Captured
Master’s Timestamp MTS
MC2 Captured
I3C BUS
I3C SDR SCLLEGEND
Bus Management
Master to Slave
Slave to Master
T Bit - Transition
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ElementsofFlowControl• TheTransmitterdrivesactivelythedatalines
– SDAonHDR-DDR– SDAandSCLonHDR-TSx
• TheReceivermightneedtoendthetransaction– ThebusneedstoprovidetheopportunityfortheReceivertochange
thestateofaline,inapre-establishedway
13
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HDR-DDRTransactionsHDR-DDRPreambleValues
14
ContextPreambleValueandInterpretation
2’b00 2’b01 2’b10 2’b11
AfterEnterHDR
Reservedfor
FutureUse
CommandWordfollows - -
AfterReadCMD - SlaveACK,Datafollows
SlaveNACK,Aborted
AfterReadDATA CRCWordfollows
MasterAborts,Slaveyields.
Masterdrivessecond0.
Datafollows.
Masterdoesnotdrivesecondbit.
AfterWriteCMD - Datafollows -
AfterWriteDATA CRCWordfollows - Datafollows
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HDR-DDR– SlavecontrolsDDRREADcommand
15
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
Beginning of new DATA Word
0.3 X VDD
0.7 X VDD
0.7 X VDD
0.7 X VDD
0.7 X VDD
0.3 X VDD
0.3 X VDD
0.3 X VDD
0.7 X VDD
0.3 X VDD
0.7 X VDD
0.3 X VDD
C1
CCC DATA [15:0]
C10
PAR1CCC DATA
[15:0]
tSCO
C2
1 2 43
56
PAR0PAR1 PRE1 PRE0 D0.7 D0.6
PAR0 PRE1 PRE0 D0.7 D0.6
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
2 2 2
Beginning of HDR Restart or HDR EXIT Pattern
0.3 X VDD
0.7 X VDD
0.7 X VDD
0.7 X VDD
0.7 X VDD
0.3 X VDD
0.3 X VDD
0.3 X VDD
0.7 X VDD
0.3 X VDD
0.7 X VDD
0.3 X VDD
C1C10
tSCO
PAR0PAR1CCC DATA
[15:0] PRE1 PRE0
PAR0PAR1CCC DATA [15:0] PRE1 PRE0
1 2 43
5
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SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
2 2 2
BeginningofHDRRestartorHDREXITPattern
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
HDR-DDR– MasterControlsDDRREADTransaction[1]
EarlyendingwithnoCRC
16
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1
tSCO
C2
D0.7 D0.6
PRE0 D0.7 D0.6
BeginningofnewDATAWord
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SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
BeginningofCRC
7
8 9 10 11 12
1'b1 1'b1 1'b0 1'b0
CLK_CRC1
13 14 15
CLK_CRC2 CLK_CRC3
HDR-DDR– MasterControlsDDRREADTransaction[2]
EarlyendingwithCRC
17
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1
tSCO
C2
D0.7 D0.6
PRE0 D0.7 D0.6
BeginningofnewDATAWord
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HDR-DDR– SlaveRequestsDDRWRITETermination[1]
18
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
BeginningofnewDATAWord
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
C2
D0.7 D0.6
D0.7 D0.6
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
2 2 2
BeginningofHDRRestartorHDREXITPattern
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
EarlyendingwithnoCRC
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HDR-DDR– SlaveRequestsDDRWRITETermination[2]
19
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
PAR0PAR1
BeginningofnewDATAWord
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
C2
D0.7 D0.6
D0.7 D0.6
EarlyendingwithCRC
M_SDA
S_SDA
SCL
M_SCL
S_SCL
SDA
PAR0PAR1
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1
1 2 3 4 5 6 7
DATA[15:0] PRE1 PRE0
C10
PAR0PAR1DATA[15:0] PRE1 PRE0
tSCO
BeginningofCRC1'b1 1'b1 1'b0 1'b0
CLK_CRC1
8 9 10 11
67
12
CLK_CRC2 CLK_CRC3
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HDR-TSx– MasterControlsS2MDataTransfer
20
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
T0T1
T0T1
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1 C2
BeginningofnewDATAWord
T10T11 T9
T10T11 T9
1 2 3 4 5 6 7
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
T0T1
T0T1
2 2 2
BeginningofHDRRestartorHDREXITPattern
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1 C2
1 2 3 4 5 6 7
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HDR-TSx– SlaveControlstheM2SDataTransfer
21
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
T0T1
T0T1
BeginningofnewDATAWord
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1 C2
T10T11 T9
T10T11 T9
1 2 3 4 5 6
SCL
M_SCL
S_SCL
M_SDA
S_SDA
SDA
T0T1
T0T1
2 2 2
BeginningofHDRRestartorHDREXITPattern
0.3XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.7XVDD
0.3XVDD
0.3XVDD
0.3XVDD
0.7XVDD
0.3XVDD
0.7XVDD
0.3XVDD
C1 C2
1 2 3 4 5 6 7
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ENDXFERCCC– EarlyTerminationSetupandInvocation
22
S 7’h7E/W/ACK
ENDXFERCCC/T
DefiningByte/T
(Optional)Data/T
Sr
Sr P
Defining Byte / T
S
Sr
7’h7E/ W / ACK
ENDXFER CCC/ T
ENDXFER has ended
Sr Slave Addr/ RnW / ACK
Data/ T
Describes Slave
Sr
P
7’h7E/ W / ACK
P
Sr Slave Addr/ RnW / ACK
Next CCC
Repeat for additional Slaves on ENDXFER
• DefiningBytes• 0x7F– SET/GETRepetitionIntervalforHDR-TSx• 0x55– InitiatestheHDR-TSxwithEndingDataTransferProcedureEnabled• 0xF7– SET/GETCRCIndexforHDR-DDR• 0xAA– InitiatestheHDR-DDRwithEndingDataTransferProcedureEnabled
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