microwave amplifier designweb.nchu.edu.tw/~ycchiang/microwave/microwave_10.pdf · twowo o t owe ga...
TRANSCRIPT
Microwave Amplifier Design
1
Microwave Amplifier Designc owave p e es g
• Two-Port Power Gains
LL SPGGainPower , inavs
inPP
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Figure 11-1 (p. 537) A two-port network with general source and load impedances.
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4
Two Port Power Gainswo o t owe Ga s
• Example 11.1 Comparison of Power Gain DefinitionsS 50 a with GHz, 10at parameters following thehasor transistmicrowaveA
SSSS 15040.0 ,1005.2 ,1001.0 ,15045.0:impedance reference
o22
o21
o12
o11
SolutionZZ LS . 30 , 20
ZZ 1 22 S
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11
1 12
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in
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LST
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SG
5
111 SS
Two Port Power Gainswo o t owe Ga s
Figure 11-2 (p. 540) The general transistor amplifier circuit.
( )i tf thiEff ti (l d)t tf thiEff ti
21
:network matching(source)input for thegain Effective
21
:network matching(load)output for thegain Effective
2
in
:istorfor transgainpowerTransducer1
1 G
S
SS
L
LLG 2
22
:gainertransducoverallThe1
1
2210
:istorfor transgain power Transducer
SG LST GGGG 0 :gainer transducoverall The
6
Two Port Power Gainswo o t owe Ga s
• If the transistor is unilateral, Conjugate match GaAs FET equivalent CKTso that S12 = 012
→ in = S11, out = S22out 22
2
2
1
1
SG S
S
2210
11
1
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S S
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2
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ff
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7
81
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Two Port Power Gainswo o t owe Ga s
Figure 11-4 (p. 542)g pPhotograph of a low noise MMIC amplifier using three HEMTs with coplanar waveguide circuitry. The amplifier has a gain of 20 dB from 20 to 24 GHz. The contact pads on the left and right of the chip are for RF input and output, with DC bias connections at the top. Chip dimensions are 1.1 2.0 mm. Courtesy of R W Jackson and B Hou of the University of Massachusetts and J Wendler of M/A-COM
8
Courtesy of R. W. Jackson and B. Hou of the University of Massachusetts and J. Wendler of M/A-COM.
StabilityStab ty
• Unconditional stability:impedances load and source passive allfor 1 ,1 outin
• Conditional stability:1 ,1 i.e.,
pp, outin
LS
unstableypotentiall as toreferred also is case This ,impedancesload and source passive of rangecertain afor only 1 ,1 outin
• Frequency dependence
• Rigorous treatment of stability requires that the network S parameters have l i h i h h lf l f l i ddi i | | 1no poles in the right-half complex frequency plane, in addition to |in| < 1
and |out| < 1.
9
StabilityStab ty
• Stability Circlesnally unconditiofor Conditions :circle stability output for theequation The
1
:amplifier stable
211211i
SSS L 22
211211in 1
1
SSSS
L
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1
11
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StabilityStab ty
• Stability Circles:circle stability Output :circle stability Input
( t )
1122
SSC
RC LLL
( t )
2211
SSC
RC SSS
(center)
2112
2222
1122
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SCL
(center)
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SCS
(radius) 2222
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11
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0thensetweIf ZZ stablenalunconditioisdevicetheIf
11 5(a)Figure1
0 then ,set weIf
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chart.Smith theoutside completely is circle stability
stable, nalunconditio is device theIf
11.5(b) Figure1
11.5(a) Figure1
11
11
S
S
1for1
1for ,1 11
SRC
SRC LL
11
1for ,1 22 SRC SS
StabilityStab ty
Figure 11-5 (p. 544)Output stability circles for a conditionally stable device. (a) |S11| < 1. (b) |S11| > 1.
12
p y y ( ) | 11| ( ) | 11|
StabilityStab ty
• Tests for Unconditional Stability: testK : test
11
condition sRollet'22
222
11 SSK
111 11
22
11
211222out
S
SSSSS
S
S
S
S
condition Auxiliary
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satisfied.usly simultaneo are,1 21122211 SSSS
11 22
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1 havemust weAlso,
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out
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SSSSSRC
RC
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11
1121121122
S
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13
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StabilityStab ty
• Example 11.2 Transistor StabilityS voltagebias a with GHz 2at FET GaAs 102-HFET HP for the parameters The
SSSS
ZVgs
o22
o21
o12
o11
0
6.27781.0 ,6.123122.3 ,4.6202.0 ,6.60894.0
)50( follows asgiven are 0
Solution
condition sRollet': testK 47361.1 o
221122
SSCL
607.02
1
2112
2222
211
SSSS
K50.022
2112
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S
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21122211 SSSS
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11
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test
199.0222112
2211
SSR
S
S
S
14
21121122 SSSS 22
11 SS
StabilityStab ty
Figure 11-6 (p. 549)Stability circles for Example 11.2.
15
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Design for Maximum Gain (Conjugate Matching)G0 gain overall thefixed, is Since for Solving S
LS GG0
matching conjugate ifGain Maximum. and by controlled be will
g,
22
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and
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require condition matching
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24
Similarly,C
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16
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Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
as definedare , , , s variableThe 2211 CBCB
12 0 :case unilateral The
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17
12S
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Example 11.3 Conjugately Matched Amplifier Designmatching stub-single using GHz 4.0at gain maximumfor amplifier an Design
SSSSfZS 0
(GH )) 50( parameters following thehas FET GaAs The
GHz.5 to3 fromgain theand lossreturn input plot the and Calculate sections.
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(GHz)
Solution
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Solution
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211 1951
1
GHz 4.0at Check
SSK
testK
o
21
211 1238720
4
gain, maximumFor
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Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
dB20.617.41
)(continued
2 SG
Solution
dB 30.876.6
12
210
2
SS
SG
dB 22.267.11
1 2
22
2
L
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dB 72.1622.230.820.6 gain,er transducoverall The
maxTG
Figure 11-7a (p. 552)Figure 11-7b (p. 553) (b) RF circuit.
19
(a) Smith chart for the design of the input matching network.g (p ) ( )
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
Fi 11 7b ( 553) ( ) F
20
Figure 11-7b (p. 553) (c) Frequency response.
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Constant Gain Circles and Design for Specified Gain12 ignored, enough to small is S 1G12
11.unilateral
gg
GT
11
1 211
max
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21
22 L
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Constant Gain Circles and Design for Specified GainSg :ofvaluefixedFor 11SgS
SSS
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gSSS
SSg
g
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Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Example 11.4 Amplifier Design for Specified Gaingain constant Plot GHz.4.0at dB11 ofgain a have toamplifier an Design
GG LS
thehas FET The GHz. 5 to3 fromgain amplifier overall and lossreturn input plot the and Calculate dB. 1 and dB 0 and dB, 3 and dB 2for circles
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50660010082908003 0
(GHz))50( parameters following
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Solution
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dB632921GS dB082562SG
dB 9.156.11
1
dB6.329.21
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211
max
max
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max
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23
1 222
max S
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
875.0 dB 3)(continued SS gG
Solution
29401206270
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o
o
SS
SS
RC
gGRC
3030705200
806.0 dB 1294.0 120627.0
o
o
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SS
RC
gGRC
440.0 70440.0
640.0 dB 0303.0 70520.0
o
LL
LL
LL
RC
gGRC
LL
24
Figure 11-8a/b (p. 556) (a) Constant gain circles. (b) RF circuit.
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
Figure 11-8b (p. 557) (c) Transducer gain and return loss.
25
g (p ) ( ) g
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Low-Noise Amplifier DesignfigurenoiseconstantofcirclesofDerivation 11
:amplifierport - twoafor figure Noisefigure noiseconstant of circles of Derivation
2N YYRFF 11
111
opt
0ZY
S
SS
where
, optmin SS
N YYG
FF1
1 opt
opt
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Y
admittance source optimum admittance source
minopt SSS
FYjBGY
d ittftlor transistof resistance noise equivalent
figure noise minimum min
N
GRF device theof parametersNoise
admittance source ofpart real SG
26
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
2
t2
2
opt20
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opt11
4
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optoptoptopt
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S
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opt0
min2
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opt 141
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1
12
opt
N
NNR
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F
27
0NS 1N
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
• Example 11.5 Low-Noise Amplifier DesignS -para following thehas and figure, noise minimumfor biased is FET GaAsA
RFSS
SSZ
N Calculate . 20 ,10062.0 dB, 6.1 ;605.0 ,819.1
,2605.0 ,606.0:) 50( GHz 4at parameters noise and meterso
optmino
22o
21
o12
o110
GT
figure. noise thisgain with maximum e with thfigure noise dB 2 a havingamplifieran design Then .unilateral assumed is device if in error maximum the
Solution
059.0 22112112 SSSS
U 0986.012
tmin
FFN
11
11
22
222
211
TGSS
0986.014 opt
0
ZR
NN
10056.01
oopt
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dB 0.5130.1dB 5.00.891or
11 22
T
TU
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24.0
1
12
opt
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N
F
28
TUG 1NF
Single-Stage Transistor Amplifier DesignS g e Stage a s sto p e es g
circlesgain constant )(continued Solution
0.300 600.52 0.805 0.1
(dB)g
oSSSS RCgG
0.150 600.58 0.946 7.1 0.205 600.56 0.904 5.1
o
o
for 605.0 Choose
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o
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: maximum2
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0
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Figure 11-9a (p. 561)Circuit design for the transistor amplifier of Example 11 5
29
Circuit design for the transistor amplifier of Example 11.5. (a) Constant gain and noise figure circles. (b) RF circuit.
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Narrow bandwidth due to– Matching requirement for maximum gain ↔ transistors are not 50Matching requirement for maximum gain ↔ transistors are not 50– |S21| decreases with frequency at the rate of 6 dB/octave
• Common approaches for broadband (cost: gain, complexity…)– Compensated matching networks (|S21| cost: input/output matching)Compensated matching networks (|S21|, cost: input/output matching) – Resistive matching networks (matching, cost: gain loss and noise figure)– Negative feedback (frequency response, matching, stability, cost: gainNegative feedback (frequency response, matching, stability, cost: gain
and noise figure)– Balanced amplifiers (broadband match, cost: twice transistor & power)– Distributed amplifiers (broadband gain, matching, noise figure, cost:
circuit size, single stage gain)
30
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Balanced Amplifiers
Figure 11-10 (p. 562) A balanced amplifier using 90° hybrid couplers.
BABA
BABA
SSGGjSSj
SSSS
21
2222
1212
2221
1211
BA
BA
FFF
GGGS
1
,0identical are amplifier theIF 11
31
BA2
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Example 11.6 Performance and Optimization of a Balanced Amplifier
0.1090.100length stubsection Input onOptimizationOptimizatiParameter
AfterBeforeNetwork Matching
0.4610.432length stubsection Output 0.1340.045length linesection Output 0.1130.179length linesection Input
Figure 11-11 (p. 564) Gain and return loss, before and after ti i ti f th b l d lifi f E l 11 6
32
optimization, for the balanced amplifier of Example 11.6.
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Distributed Amplifiers
Figure 11-12 (p. 565) Configuration of an N-stage distributed amplifier.
Figure 11-13 (p. 566) (a) Transmission line circuit
33
for the gate line of the distributed amplifier;
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Distributed Amplifiers
Figure 11-13 (p. 566) (b) equivalent circuit Figure 11-14 (p. 566) (b) equivalent circuit of a single unit cell of the gate line. of a single unit cell of the drain line.
Figure 11-14 (p. 566) (a) Transmission line circuit f th d i li f th di t ib t d lifi
34
for the drain line of the distributed amplifier;
Broadband Transistor Amplifier Designoadba d a s sto p e es g
• Distributed Amplifiers Example 11.7i CZCR
22 , 50 Assume 0 ZZZ gd
g
gsgg
g
ggsiggg
CZ
lC
CLjl
ZCRj
2mS. 35 pF, 27.0, 300 , 10
gCRR
mgs
dsi
lNlNim
d
dsdd
dds
dddd
eeVgI
lCCLj
lRZj
ddgg
2GHz.18~1 16;8,4,,2 fN
lNlNgdm
llim
o
eeZZgPG
eeeeVgI
ddgg
ddgg
222
out
lNlNgdm
ll
eeZZg
eePG
ddgg
ddgg
422
in
ddgg
ll
llN
ee ddgg
ln
4
t
2
35
ddgg llN
opt
Power Amplifiersowe p e s
• Characteristics of Power Amplifiers and Amplifier Classes– Important considerations for power amplifier: efficiency gainImportant considerations for power amplifier: efficiency, gain,
intermodulation products, thermal effects.– LNA, fixed gain Amp: small-signal amplifiers (transistor: linear device)
P:efficiency Amplifier
out 1dBdB :
01 GGGainCompressed
efficiencyaddedpowerP
:
DC
out
conduct always linear, :A Classdistortionation intermodul Linearity,
01
PP
PPPAEPAE
11
DC
inout
78%llhcycle 1/2only conduct :B Class
50% efficiency maximum
GPP
G1111
DC
out
circuitresonant100%nearefficiencycycle 1/2 than more cutoffnear :C Class
78% type,pull-push
36
circuitresonant 100%,near efficiency
Power Amplifiersowe p e s
• Large-Signal Characterization of Transistors– For power near or larger than P1 S parameters will depend on inputFor power near or larger than P1, S parameters will depend on input
power level, output impedance, frequency, bias condition, temperature.
– Table 11.1 Small-Signal S Parameters and Large-Signal Reflection Coefficients (Silicon Bipolar Power Transistor)
12 01610 4781770 7471670 35250 073724231720 7690013.51290.4551670.8561630.35940.0657610.41760.76800
dBMHz
oooooo
oooooo22211211
PLPSP GSSSSf
10.01850.4911870.7971690.36350.0799608.31690.76100012.01610.4781770.7471670.35250.0737242.31720.76900
oooooo
37
Power Amplifiersowe p e s
• Load-pull contourstmeasuremen Automated
tunersstubhanicalelectromecwith
:modelsNonlinar RCC
!!e!Temperatur
, , , dsgdmgs RCgC
!!e!Temperatur
Figure 11-16 (p. 572)
38
Constant output power contours versus load impedance for a typical power FET.
Power Amplifiersowe p e s
• Example 11.8 Design of a Class A Power AmplifierBJT.silicon NPN MRF858S Motorola using MHz900at amplifier power aDesign gppg
Solution
39
Power Amplifiersowe p e s
Figure 11-17 (p. 574) RF circuit for the amplifier of Example 11.8.
40