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Microelectronics Presentation DaysMarch 2010

FPGA for Space

Bernard Bancelinfor David Dangla

Atmel ASIC BUAerospace Product Line

March 30, 2010Bernard BANCELIN ATMEL 2

ATMEL RHBD FPGA

Atmel Radiation Hardened FPGAs

Re-programmable (SRAM based technology)No reliability issue

SEU hardened Memory pointsCore cell Flip-Flops, embedded memory, configuration memory and controller No need for SEU mitigation

SEL immunity and TID tolerance up to 300 krad

Embedded Memory blocks (FreeRAM)

Atmel also offers EEPROMs for FPGA configuration

March 30, 2010Bernard BANCELIN ATMEL 3

ATMEL RHBD FPGA

ATF280F Key Features

280K equivalent ASIC gates50MHz maximum system clock14400 core-cells (each 2 LUT + 1 DFF)115 Kbit FreeRAM (900 modules of 32x4 blocks)1.8V Core / 1.8V and 3.3V I/OsDedicated LVDS buffers: 8 Rx + 8 TxCold-sparing and 3.3V PCI-compliant I/Os

ATC18RHA 0.18um technology (same as ATC18RHA ASIC)MCGA 472 (308 User I/O) / MQFP-352 (232 User I/O)Possibility for MQFP-256 (148 User I/O) packages

Configuration load integrity checkConfiguration self-integrity checkBoundary scan interface

March 30, 2010Bernard BANCELIN ATMEL 4

ATMEL RHBD FPGA

Atmel Radiation Hardened FPGAs

Layout rulesImproved to avoid multiple nodes charge collection during a single heavy ion impact

SEU hardened Memory pointsCore cell Flip-Flops, embedded memory, configuration memory based on radiation hardened Flip-Flops

Controller protected by classical TMRIncluding combinatorial logic and flip-flop of all states machines

Clock and reset treesProtected by DMR (resistive isolation path based on N and P isolated path carrying the same signal)

Your Design is radiation Hardened by constructionNo need for SEU/SET mitigation

March 30, 2010Bernard BANCELIN ATMEL 5

ATMEL RHBD FPGA

Hardened Memory Cell and Isolation Path

March 30, 2010Bernard BANCELIN ATMEL 6

ATMEL RHBD FPGA

Test Results

Single Event Latch-upNo SEL detected over all the runs performed and in particular with the runs performed at 1.95V core voltage and 3.6V I/O buffer at LBNL with Xenon and 45 deg tilting angle that corresponds to a LET of 76 MeV/(mg/cm²) and a device under test (DUT) temperature of 125°C, up to fluence of 1.10+7 part/cm².

Cross sectionThe configuration SEU error cross section per device versus effective LET is derived from the tests performed in UCL, LBNL and RADEF.

- Configuration memory SEU saturated cross-section better than 5.10-3 per device (3.10-9 cm² per bit) with a LET threshold around 30MeV at Vcc min.

- No SET was recorded with a LET of 43 MeV/(mg/cm²). - SET error cross-section per device about 1.6 10-4 at 60MeV/(mg/cm²). - FreeRAM Asymptotic SEU error cross-section per bit about 6.5 10-8

cm².

March 30, 2010Bernard BANCELIN ATMEL 7

ATMEL RHBD FPGA

SEU sensitivity of ATF280F configuration bits

March 30, 2010Bernard BANCELIN ATMEL 8

ATMEL RHBD FPGA

Design

Power-on current

- Wrong evaluation of power-on current: Random initial configuration induce high power in core cells

- Sequential start of configuration memory (final value to be confirmed after full characterization)

Routing: speed improvement

- Pass gates on local/express buses with lower Ron

- 10% improvement

New silicon fully functional, characterization in progress

Design Optimization

March 30, 2010Bernard BANCELIN ATMEL 9

ATMEL RHBD FPGA

AT69170E Key Features

4 Mbit Rad Hard EEPROM512 bytes Pages

Standard TWI programming interfaceFPGA serial configuration interface

3.3V Supply VoltageFP18 Package

Endurance: 10K cyclesData retention: 15 yearsTID > 60KrdProgramming tools

Standalone USB programmer

POR TWIInterf

Serial-izer

EEPROMCore

AT69170E

Memory Controller

March 30, 2010Bernard BANCELIN ATMEL 10

ATMEL RHBD FPGA

Design Tools

Front-End3 years contract signed with MENTORMENTOR Precision Synthesis

- VHDL / Verilog entry- Automatic IDS Macro detection and mapping- On going improvements

Back-EndATMEL Figaro IDS

- Automated Place & Route- STA- Power Estimator- VHDL / Verilog netlist export with SDF back-annotation- Bitstream generation

ATMEL Configurator Programming Tool- ATMEL EEPROM programming

March 30, 2010Bernard BANCELIN ATMEL 11

ATMEL RHBD FPGA

ATFS450 FPGA Features

Joint ATMEL and HIREC development with CNES and JAXA supportOSC 150nm SOI process

Latch-up freeFar more easier SEU/SET hardening (smaller die size)

450K equivalent ASIC gates 152x152 core cells75 MHz internal performance3.3V and 1.8V programmable IO and 1.5V array bias voltages230 cold sparing and PCI Compliant I/O padsRadiation hardened FreeRAM™180 KBits8 pairs LVDS 240Mbps transceivers and 8 pairs LVDS 240Mbps receivers8 Global SEU/SET immune ClocksPackage MQFPF256 (118 IOs), MQFPF352 (214 IOs) Radiation hardness

Heavy ions Latch-up free at LET of 70 MeV/mg/cm² at 125°CSEU/SET free at LET of 64 MeV/mg/cm²Test up to a Total Dose of 100 krad

March 30, 2010Bernard BANCELIN ATMEL 12

ATMEL RHBD FPGA

Devices Availability

AT40KEL040 Now

ATF280FSamples Now Engineering Models (after full characterization)

- ATF280F-2J-E July 2010- ATF280F-KA-E July 2010

Flight Models (QML-Q, QML-V) Nov 2010ESCC evaluation Jan 2011

ATFS4501st samples Nov 2010Flight Models Jan 2012

AT69170EPrototypes oct 2010Space Qualification Q2 2011

March 30, 2010Bernard BANCELIN ATMEL 13

ATMEL RHBD FPGA

ATMEL FPGA suite Improvements

Precision Improvements• Usage of other macros than FGEN1• Max Fan-Out and Replicate• capacitor, fan-in, timing in macro• report on number of Core Cell per LPM• IO pad registers (Done (2009a.95 upd2 prod)• more combinationnal cell in ATF280 than in AT40K• BufZ not automaticaly inserted in ATF280 (Done (2009a.95 upd2 prod)• GCLKBUF on clock pad• over max size ROM generates crash• skip unused pins in hierarchical blocks• register with enable (FDE) not working (Done (2009a.95 upd2 prod)• new wireload model • inconsistent timing reports• optionnal use of FA, MULT• use Carry select adder LPM• LPM MUX macro generator not selected• some ROM generated with FGEN1• Area report without LPM

March 30, 2010Bernard BANCELIN ATMEL 14

ATMEL RHBD FPGA

Space FPGA Roadmap

Hig

her i

nteg

ratio

n

Time scale

ATFS450ATFS450

AT40K SOIAT40K CMOS

Legend

AT280

IDS Design Kit

2 off AT280 2 off ATFS450

March 30, 2010Bernard BANCELIN ATMEL 15

ATMEL RHBD FPGA

Module 2: Reconfigurable Processor

March 30, 2010Bernard BANCELIN ATMEL 16

ATMEL RHBD FPGA

Reconfigurable Processor Synoptic

March 30, 2010Bernard BANCELIN ATMEL 17

ATMEL RHBD FPGA

Reconfigurable Processor Test

March 30, 2010Bernard BANCELIN ATMEL 18

ATMEL RHBD FPGA

Module2: ATF280F+AT69170

March 30, 2010Bernard BANCELIN ATMEL 19

ATMEL RHBD FPGA

Devices Availability

Reconfigurable Processor AT697F+ATF280FPackage CQFP352Samples Dec 2010 Qualification using ESCC (not ECSS) tbd (Q2/2011?)

Module with 2xATF280 and 2xAT69170Package CQFP352Samples (1Q after AT69170 availability) Q1 2011Flight Models Q3 2012

Some Customer Request for a module with ATF280+AT69170

March 30, 2010Bernard BANCELIN ATMEL 20

ATMEL RHBD FPGA

Space FPGA Roadmap

Hig

her i

nteg

ratio

n

Time scale

1200 Kg

2500 Kg2500 Kg

NG FPGA CMOSNG FPGA CMOS

ATFS450ATFS450

AT40K SOIAT40K CMOS

Legend

AT280

NG FPGA SOIMCP FPGA

300 Kg

2000 Kg

2 off 2500 Kg

IDS Design Kit NG DK

2 off AT280 2 off ATFS450

March 30, 2010Bernard BANCELIN ATMEL 21

ATMEL RHBD FPGA

Questions?

Thank You