microcontrollers: lecture 3 interrupts, timers, adc

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Microcontrollers: Lecture 3Interrupts, Timers, ADC

Michele Magno

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Calendar 07.04.2016:

Power consumption; Low power States; Buses, Memory, GPIOs 08.04.2016

Interrupts, Timers, ADC, DAC Exercises

15.04.2016 Serial Communications

21.04.2016 – 22.04.2016 Programming STM32

28.40.2016 DMA / Interfacing external devices

29.04.2016 Sensors / Radios Projects presentation and exercises.

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Outline

Interrupts Introduction and STM32

Timers ADC Exercises.

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‘Interrupt’ DefinitionFrom Wikipedia:

A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a part of the [device, such as an internal peripheral] or an external peripheral.

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Waiting for an Event: Family Vacation

Polling

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Waiting for an Event: Family Vacation

Polling

Wake me up when we get there...

Interrupts

An engineering example...

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Typical application profile

Time

•Application phases:• OFF – power is not applied to MCU• STARTUP INITIALIZATION – MCU performs configuration (peripherals, clocks, …)• Tperiod

• INACTIVE – MCU is in low power mode to reduce power consumption• ACTIVE – MCU is in normal mode and performs tasks

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OFF STARTUP INITIALIZATION

IRQ

IDD

IRQ

TASKS

Process ACTIVE

INACTIVE

Tperiod Tperiod

TASKS

ACTIVE

INACTIVE INACTIVE

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Waiting for an Event: Button Push

100% CPU Load

while(1) {

// Polling GPIO button

while (GPIO_getInputPinValue()==1)

GPIO_toggleOutputOnPin();

}

// GPIO button interrupt

#Iterrupt servise routine

__interrupt void rx (void){

GPIO_toggleOutputOnPin();

}

> 0.1% CPU Load

How interrupts can affect system design…

Polling Interrupts

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Interrupts Help Support Ultra Low Power

Only timers are running

Very little CPUeffort required

Lots of sleep time

Keep CPU asleep (i.e. in Low Power Mode) while waiting for event

Interrupt ‘wakes up’ CPU when it’s required

Another way to look at it is that interrupts often cause a program state change

Often, work can be done by peripherals, letting CPU stay in low power mode (e.g. Gate Time)

Basic program topology...

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Interrupts

A way to respond to an external event (i.e., flag being set) without polling

How it works: H/W senses flag being set Automatically transfers control to s/w that

“services” the interrupt When done, H/W returns control to

wherever it left off

Advantages: Transparent to user cleaner code μC doesn’t waste time polling

Main ProgISR

::::

RETI

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Foreground / Background Schedulingmain() {

}

while(1){backgroundor

Low Power Mode}

//InitinitGPIO();initClocks();...

ISR1get dataprocess

System Initialization

The beginning part of main() is usually dedicated to setting up your system

Background

Most systems have an endless loop that runs ‘forever’ in the background

In this case, ‘Background’ implies that it runs at a lower priority than ‘Foreground’

In microcontrollers, the background loop often contains a Low Power Mode command – this sleeps the CPU/System until an interrupt event wakes it up

Foreground

Interrupt Service Routine (ISR) runs in response to enabled hardware interrupt

These events may change modes in Background – such as waking the CPU out of low-power mode

ISR’s, by default, are not interruptible

Some processing may be done in ISR, but it’s usually best to keep them short

ISR2set a flag

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Foreground / Background (States)

Foreground(higher priority)

ISR1 ISR2 ISR2

Background main() main()(lower priority)

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STM32L1x - Block Diagram 13

08.04.2016

Presentation Title

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Nested Vectored Interrupt Controller (NVIC)

Hardware unit that coordinates among interrupts from multiple sources Define priority level of each interrupt source

(NVIC_PRIx_R registers) Separate enable flag for each interrupt source

(NVIC_EN0_R and NVIC_EN1_R)

Interrupt does not set I bit Higher priority interrupts can interrupt lower priority ones

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Nested Vector Interrupt Controller NVIC

Up to 81 interrupts (depends on the STM32 device type)

Programmable priority level of 0-15 A higher level corresponds to a lower priority, so level 0 is

the highest interrupt priority

Dynamic reprioritization of interrupts

Grouping of priority values into group priority and sub-priority fields Interrupt tail-chaining

An external Non-maskable interrupt (NMI)

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EXTI module: from pin to NVICGPIOA_0 GPIOB_0

GPIOI_0

EXTIChannel 0

GPIOA_1 GPIOB_1

GPIOI_1

Channel 1

GPIOA_15 GPIOB_15

GPIOI_15

Channel 15

CORTEX M4

NVICExti_0

Exti_1Exti_2

Exti_3

Exti_4

Exti_9-5

Exti_15-10

Wakeup

PVDRTC_Alarm USB OTG FS WkupETH Wkup USB OTG HS WkupRTC Tamper

RTC Wkup

Event

Interrupt

ENABLE

DISABLE

Inp

ut

floa

tin

g

PVD_IRQ

RTC_IRQ

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Nested Interrupt: If a interrupt request (IRQ)

with higher priority is raised, it is served first

Tail chaining: for nested ISR does not restore

all saved registers from the stack.

Stack pop pre-emption: If another exception

occurs during the unstacking process of an

exception, the processor abandons the stack

Pop

TIMERS

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08.04.2016Presentation Title

2020

Timers

Correct system timing is a fundamental requirement for the proper operation of a real-time application; If the timing is incorrect, the input data may be processed after the output

was updated The timers may be driven from an internal or external clock; Usually timers include multiple independent capture and compare

blocks, with interrupt capabilities; Main applications:

Generate events of fixed-time period; Allow periodic wake-up from sleep; Count external signals/events; Signal generation (Pulse Width Modulation – PWM); Replacing delay loops with timer calls allows the CPU to sleep between operations,

thus consuming less power.

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Timer/Counter BasicsCounterRegisterClock Input

Clock GPIO Pin (TACLK)

Counter Overflow Action Interrupt

Notes Timers are often called “Timer/Counters” as a counter is the essential element “Timing” is based on counting inputs from a known clock rate

Input Counter Action

What happens on each clock input?

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Timer/Counter BasicsCounterRegister

CounterOverflow Action Interrupt (TAIFG)

FFFF

FFFE

FFFD

04

03

02

01 01

Each pulse of clock input

increments the counter register

Interrupt occurs when timer overflows back to zero

Notes Timers are often called “Timer/Counters” as a counter is the essential element “Timing” is based on counting inputs from a known clock rate Actions don’t occur when writing value to counter

TAR

Can I 'capture' a count/time value?

Clock Input Clock GPIO Pin (TACLK)

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Frequency, Time Period, Resolution

timer interrupt timer interrupt timer interrupt

Time Period

Definitions Frequency: How many times per second Time Period: Amount of time between successive events Resolution: Granularity in determining system events

With what resolution can we determine if an

event occurred here?

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CounterRegister

15 0TAR


Notes Capture time (i.e. count value) when Capture Input signal occurs

Capture Basics

Alternatively, use CCR for compare...

Clock Input Clock GPIO Pin

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Capture/Compare Register (CCRn)

CounterRegister

15 0TAR


Capture Input signal triggerstransfer:

Counter → Capture

Notes Capture time (i.e. count value) when Capture Input signal occurs When capture is triggered, count value is placed in CCR and an interrupt is generated

Capture Basics


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CounterRegister

15 0TAR

CounterOverflow Action Interrupt

Capture Input signal triggerstransfer:

Counter → Capture

Notes Capture time (i.e. count value) when Capture Input signal occurs When capture is triggered, count value is placed in CCR and an interrupt is generated Capture Overflow (COV): indicates 2nd capture to CCR before 1st was read

Capture Input CCInA CCInB Software

Capture Actions Interrupt Signal peripheral Modify pin (TIM_OUT)

Capture Basics


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Compare BasicsCounterRegisterClock Input



A key feature for timers is the ability to create

consistent, periodic interrupts

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Compare Basics


CounterRegisterClock Input



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Compare Basics

Compare Actions Interrupt Signal peripheral Modify pin (TIM_OUT)


CounterRegisterClock Input



when Counter = CompareCompare Actions can occur

Notes There are usually 2 to 7 compare registers (CCR’s), therefore

up to 8 interrupts or signals can be generated Counter must count-to Compare value to generate action

TAR

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15 0Example.

16-bit Counter(TA0R)

Interrupt (TA0IFG)

Divideby 5-bits

(up to ÷ 64)

Enable(TA0IE)

CCR0

CCR1

CCR2

CCR3

CCR4

CCR5

CCR6

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Timer_A7 Summary

TimerA0.0: Is the first instance (Timer0 or TA0) of Timer_A7 on the device _A7 means it has 7 Capture/Compare Registers (CCR’s)

CCR registers can be configured for: Compare (set when CAP=0) generates interrupt (CCnIFG) and

modifies OUT signal when TAR = CCRn Capture (when CAP=1) grabs the TAR value and sets an interrupt (CCnIFG) when triggered by the selected

CCIx input

15 0

16-bit Counter(TAR)

Interrupt (TAIFG)

Divideby 5-bits

(up to ÷ 64)

Enable(TAIE)

CCR0

CCR6 CAP=1 CM SCS COV

CC0IFGCC0IE

TA0.0...CAP=0

CC6IFGCC6IE

TA0.6

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• The general-purpose timers consist of a 16-bit (or 32bits) auto-reload counter driven by a programmable prescaler.

• They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).

• Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers.

• General-purpose TIMx timer features include:- 16-bit up, down, up/down auto-reload counter.- 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock

frequency by any factor between 1 and 65535.- Up to 4 independent channels for:

‣ Input capture‣ Output compare‣ PWM generation (Edge- and Center-aligned modes)‣ One-pulse mode output

Timers – STM32

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Timers – Basic architecture STM32.

CLOCKS

CLOCKS / N

Counter/Autro-reload

Capture/compare

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RCC – Real Time Clock Control

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Timers

General-purpose timer block diagram

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Timers

PATH: TimerX - Channel 1 - output compare

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Timers


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Timers


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Timers


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Timers

24MHz

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Timers

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Timers

The counter clock can be divided by a prescaler.

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Timers

The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down.

CK_CNT

CNT

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Timers

In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

CK_CNT

CNT

AutoreloadRegister

Timer Interrupt

Period

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Timers

Output compare mode: This function is used to control an output waveform or indicating when a period of time has elapsed.

CK_CNT

CNT

AutoreloadRegister

Timer Interrupt

OC1

CH1 Interrupt

Compare Register

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Timers

Output compare mode: This function is used to control an output waveform or indicating when a period of time has elapsed.

CK_CNT

CNT

AutoreloadRegister

Timer Interrupt

OC1

CH1 Interrupt

Compare Register

Used to schedule periodic events

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PWM

What is Pulse Width Modulation? Pulse width modulation (PWM) is a simple method of

using a rectangular digital waveform to control an analog variable

PWM delivers a variable amount of power efficiently to external hw devices

PWM control is used in a variety of applications, ranging from communications to automatic control, i.e. control speed of electric motors, brightness of a LED, temperature of heating element

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PWM

The period is normally kept constant, and the pulse width, or “on” time is varied

The duty cycle is the proportion of time that the pulse is ‘on’ or ‘high’, and is expressed as a percentage:

duty cycle = 100% * (pulse on time) / (pulse period)

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PWM

Whatever duty cycle a PWM stream has, there is an average value, as indicated by the dotted line

If the on time is small, the average value is low; if the on time is large, the average value is high

By controlling the duty cycle, we control this average value

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PWM

The average value can be extracted from the PWM stream

with a low-pass filter

In this case, and as long as PWM frequency and values of R

and C are appropriately chosen, Vout becomes an analog

output• In practice, this sort of filtering is not always required;

many physical systems have response characteristics which, in reality, act like low pass filters

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Applications using PWM Devices used in robotics

DC motors

Servos

Solenoids

Closed loop control systems

Communications and pulse code modulation

Benefits include

Microprocessor control

Efficient use of power

Tolerance to analog noise

Not susceptible to component drift

Any device whose response to changes in current or voltage is slow compared to the frequency of the PWM signal is a candidate for being controlled via PWM.

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STM32 – GPIO Timers for PWM The STM32 hardware timers are separate hardware blocks that can count from 0 to a given value triggering some

events in between.

In the PWM mode the timer controls the output of 1 or more output channels.

When the counter value reaches 0, maximum or a compare value defined for each channel, the output value of the

channel can be changed.

Various configuration options define which events change the value and how it is changed.T; f = 1/T

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STM32 – GPIO Timers for PWM

Up to 4 channel

Edge-aligned mode

Center-aligned mode

Timer Type Resolution Prescaler ChannelsMAX

INTERFACE CLOCK

MAX TIMER CLOCK* APB

TIM1, TIM8 Advanced 16bit 16bit 4 SysClk/2 SysClk 2

TIM2, TIM5 General purpose 32bit 16bit 4 SysClk/4 SysClk, SysClk/2 1


TIM9 General purpose 16bit 16bit 2 SysClk/2 SysClk 2

TIM10, TIM11 General purpose 16bit 16bit 1 SysClk/2 SysClk 2

TIM12 General purpose 16bit 16bit 2 SysClk/4 SysClk, SysClk/2 1


TIM6, TIM7 Basic 16bit 16bit 0 SysClk/4 SysClk, SysClk/2 1

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Example, a 16 bit Timer

fSystemClock=ftimer=8MHz

As you said we have a tick in every,

Ttimer=1/fSystemClock=1/ftimer=1/8MHz=0.125μs

With a 16 bit Timer it means,ticksmax=(216-1)=65535ticks

So the timer will overflow in every,toverflow=ticksmax×Ttimer=65535×0.125μs=8.191875ms

Frequency and Times

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GPIO Timer Block diagram

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APB1 or APB 2?

APB2

APB1

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Timer Example exercisesCalculate the Timer Setting for the Clock & divider values needed to create a timer interrupt every 2seconds when the CPU of the following processor is in the deep sleep mode allowed.

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Timers - Exercises

Input Clock= ____________

Low Power SleepLow Power Model= _____________________

32KHz

Timer Clock= ____________ / __________ =

1/ 32KHz

1 32KHz

Time = ____________ * __________ =

32KHz

16 or 32 bit?

655322s

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CORTEXTM-M3CPU

24 MHz

ARM

®Pe

riphe

ral B

us(m

ax 2

4MH

z)

2 x I2C

1 x SPI

2 x USART/LINSmartcard / IrDaModem Control

37/51/80 I/Os

Up to 16 Ext. ITs

JTAG/SW Debug

Power SupplyReg 1.8V

POR/PDR/PVD

DMA7 Channels

Nested vect IT Ctrl

1 x USART/LINSmartcard/IrDaModem Control

1 x SPI

Bridge

Bridge

1 x Systick Timer

ARM

® L

ite H

i-Spe

ed B

usM

atrix

/ Ar

bite

r (m

ax 2

4MH

z)

RTC / AWU

ARM® Peripheral Bus(max 24MHz)

XTAL oscillators32KHz + 4~25MHz

Int. RC oscillators

40KHz + 8MHz

PLL

8kB SRAM

Flas

h I/F 64kB - 128kB

Flash Memory

Clock Control

20B Backup Data

1 x 12-bit ADCup to16 channels

Temperature Sensor

2 x Watchdog(independent & window)

6 x 16-bit Timer 1 x CEC

2-channel 12-bit DAC

1 x 16-bit PWM Synchronized AC Timer

• Core and operating conditions- ARM® Cortex™-M3 - 1.25 DMIPS/MHz up to 24 MHz - 2.0 V to 3.6 V range - -40 to +105 °C

• LQFP48, LQFP/BGA64, LQFP100

• Advanced analog- 12-bit1.2 µs conversion time ADC- Dual channel 12-bit DAC

• Enhanced control- 16-bit motor control timer- 6x 16-bit PWM timers

• Rich connectivity- 8 communications peripherals

STM32 Value line 64K-128KBytes System Diagram

60

Sensors

60Copyright 2009 Texas Instruments

Integrated 9DoF IMU (Invensense) Low-power cameras (Centeye, Awaiba, SoftKinetic) IR sensors (LEAP, PMD) EF sensors (Microchip GestIC, Plessy sensors) ECG contactless (EPIC from Plessey) and bio sensors Multi-Gas sensors Contactless Voltage + Current Acoustic sensors (MEMS, Analog, Digital)

Grove Starter Kit for LaunchPad

61

Sensors data acquisitionData acquisition system components:

Sensors:Convert analogue measurements of physical quantities (e.g. temperature, pressure, humidity, velocity, flow-rate, linear motion, position) into electrical signals (voltage or current).

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Data acquisition system components

Signal conditioning (filtering and amplification):- The operations required to convert the measured analogue signal to the

electrical signal range of the analogue-to-digital converter (ADC) may involve filtering, amplification, attenuation or impedance transformation.

Analogue-to-Digital Converter (ADC):- Input: Signal to be measured; - Output: A digital code compatible with the digital processing system;- Requires:

• Sample-and-hold: Used to take a snapshot of the continuously changinginput signal and maintain the value over the sample interval set by a clocksystem;

• A sampling frequency based on the Nyquist theorem.

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ADC conversion Sample and Hold

Sample and Hold circuit does the signal time quantization

Restriction to digital information processing.Known digital computers can only process discrete time series Sample and hold-devices.Ideally: width of clock pulse → 0

Convert signal function in a series of value

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Analogue-to-Digital Converter (ADC) The ADC takes the voltage from the acquisition system (after signal

conditioning) and converts it to an equivalent digital code;

ADC architectures: Successive Approximation (SAR) Sigma Delta (SD or ∆Σ) Slope or Dual Slope Pipeline Flash

ADC ideal transfer function

ADC performance

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ADC performance Resolution, R:

The resolution specifies the width of the digital output word;- 10, 12, 16 Bit ADC

The width of the word implies the smallest change to the analogue voltage thatcan be converted into a digital code;

The Least Significant Bit (LSB):

Accuracy: Degree of conformity of a digital code representing the analogue

voltage to

Speed: Maximum output data rate expressed in sample per second (sps)

nref

LSB

VV

2=

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ADC Block Examples

Voltage reference

Clock sources

Conversion trigger

ADC Features 3 ADCs : ADC1 (master), ADC2 and ADC3 (slaves)

Maximum frequency of the ADC analog clock is 36MHz.

12-bits, 10-bits, 8-bits or 6-bits configurable resolution.

ADC conversion rate with 12 bit resolution is up to: 2.4 M.sample/s in single ADC mode,

4.5 M.sample/s in dual interleaved ADC mode,

7.2 M.sample/s in triple interleaved ADC mode.

Conversion range: 0 to 3.6 V. ADC supply requirement: VDDA = 2.4V to 3.6V at full speed and down to 1.65V

at lower speed.

Up to 24 external channels.

3 ADC1 internal channels connected to: Temperature sensor,

Internal voltage reference : VREFINT (1.2V typ),

VBAT for internal battery monitoring.

• The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources.

• A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

• The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds.

• The ADC input clock is generated from the PCLK2 clock divided by a prescaler.

• To synchronize ADC conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer.

ADC – Summary and examples

12-bit successive approximation ADC

ADC

Successive Approximation ADC

Tconv = n * TCK

Analog references / supply

ADC

The ADCCLK clockprovided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescalerfor the ADC clock

If prescaler == 0 on the STM32 discovery ADCCLK==36MHz

ADC

RCC – Real Time Clock Control

There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order.

The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage VREFINT is connected to ADCx_IN17. These two internalchannels can be selected and converted as injected or regular channels.The recommended sampling time for the temperature sensor is 17.1 μs.

ADC

Conversion can be triggered by an externalevent (e.g. timer capture, EXTI line)

ADC

Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel.

Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user.

ADC

When the conversion is done, data is stored in 16 bits registers and the proper flags are set to indicate the end of conversion

ADC

ADC speed performances

AHB_PRESC

/1,2,..512

APB2_PRESC

/1, 2, 4, 8,16

ADC_PRESC

/2,4, 6, 8

ADC_CLK(36MHz max)

AHBCLK(168MHz max)

(1). ADC_PRESC = /2 (2). ADC_PRESC = /4

(a)APB_PRESC = /2

(b)APB_PRESC = /1

SYSCLK(168MHz max)

APB2CLK(84MHz max)

AHBCLK APB2CLK ADC_CLK ADC speed(15 cycles)

168MHz (a)84MHz

(2)21MHz

0.714μs1.4 Msample/s

144MHz (a)72MHz

(1)36MHz


120MHz (a)60MHz

(1)30MHz

0.5μs2 Msample/s

96MHz (a)48MHz

(1)24MHz


72MHz (b)72MHz

(1)36MHz


ADCCLK, up to 36MHz, taken from PCLK through a prescaler (Div2, Div4, Div6 and Div8).

Programmable sample time for each channel (from 4 to 480 clock cycles)

Total conversion Time = TSampling + Tconversion

ADCx

112 cycles

144 cycles

480 cycles

SMPx[2:0]

With Sample time= 3 cycles @ ADC_CLK = 36MHz total conversion time is equal to:

ADC ConversionTime

ADCCLKPrescaler/2, /4, /6 or /8

PCLK

3 cycles

15 cycles

28 cycles

84 cycles

58 cycles

Sample

Time

Selection

Resolution TConversion

12 bits 12 Cycles

10 bits 10 Cycles

8 bits 8 Cycles

6 bits 6 Cycles

resolution Total conversion Time

12 bits 12 + 3 = 15cycles 0.416 us 2.4 Msps

10 bits 10 + 3 = 13 cycles 0.361 us 2.71 Msps

8 bits 8 + 3 = 11 cycles 0.305 us 3.27 Msps

6 bits 6 + 3 = 9 cycles 0.25 us 4 Msps

Comparator 1 features 8080

• Non-inverting input selectable from 24 I/Os

• Selectable edge detection through EXTI Line 21

• COMP1 and ADC can’t be used at same time since they share the ADC switch matrix

VSS

CH25

CH24

CH23

CH4

ADC

VCOMP

VREFINT

1.22V

VDD

10K400K

10K400K

+

-

COMP1

CH5

CH22

Temp. Sensor *VREFINT *

Group 8

Group 1

Group 9

Group 7

Group 3

Group 2

CH10

CH11

CH12

CH13

CH1

CH2

CH3

CH0

CH14

CH15

CH19

CH20CH21

CH9

CH8

CH6

CH7

CH18

ADC Switch matrix

EXTI 21

CMP1OUT

Routing Interface

PC0

PC1

PC2

PC3

PA0

PA1

PA2

PA3

PA6

PA7

PC4

PC5

PB12

PB13

PB14

PB15

PB0

PB1

PA4

PA5

PE7

PE8

PE9

PE10

Comparator 2 features 1/2 8181

• Rail-to-rail comparator with selectable threshold: Internal reference voltage VREFINT, VREFINT submultiples (1/4, 1/2, 3/4), DAC output 1 & 2 or one external I/0 (PB3).

• Selectable non-inverting input from external I/Os: PB4 or PB5.

• Selectable edge detection through EXTI line 22.

Group 6GR 6-1

GR 6-2

PB3

TIM3 OCREF ClearTIM3 Input Capture 4TIM2 OCREF ClearTIM2 Input Capture 4

TIM4 Input Capture 4TIM4 OCREF ClearTIM10 Input Capture 1

DAC_OUT1

VREFINT (1.22V)

-+

¾ VREFINT

½ VREFINT

¼ VREFINT

PB4

PB5 EXTI 22COMP2

DAC_OUT2

VREFINT

CMP2OUT

81

Comparator 2 features 2/2 82

Group 6GR 6-1

GR 6-2

PB3

DAC_OUT1

VREFINT (1.22V)

-+

¾ VREFINT

½ VREFINT

¼ VREFINT

PB4

PB5 EXTI 22COMP2

DAC_OUT2

VREFINT

CMP2OUT

82

• COMP2 output can be redirected to:• Timer input captures for pulse width or signal frequency measurements

• Timer output compare reference clear signal “OCREFCLR”, putting the PWM signal in safe state as soon as analog input voltage crosses the reference.

TIM2 IC4

TIM2 OCRECLR

TIM3 IC4

TIM3 OCREFCLR

TIM4 IC4

TIM4 OCRECLR

TIM10 IC1

OUTSEL[2:0]

Comparators in Window mode 1/2 83

• Interrupt and Wake-up modes:

• Vin > Upper threshold• Vin < Lower threshold• Lower threshold < Vin

< Upper threshold• Vin < Lower threshold

or Vin > Upper threshold

Lower threshold: Multiple source

+

-

-

+

Upper threshold: VREFINT = 1.22V

Window comparator configuration switch

Input voltage

COMP2

COMP1

PB4

PB5

GR 6-1

GR 6-2

microcontrollers: lecture 3 interrupts, timers, adc

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