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Enclustra GmbH – Technoparkstr. 1 – CH-8005 Zürich – Switzerland

Phone +41 43 343 39 43 – www.enclustra.com

Mercury CA1 FPGA Module

User Manual

Document Info

Product Manager Martin Heimlicher

Author(s) André Schlegel

Reviewer(s) Marc Oberholzer, Christoph Glattfelder

Enclustra GmbH – Technoparkstr. 1 – CH-8005 Zürich – Switzerland

Phone +41 43 343 39 43 – www.enclustra.com

Document Info

Version 1.11

Date 09.03.2016

15.02.2016 3 / 63 Version 1.10

Copyright reminder

Copyright © 2016 by Enclustra GmbH, Switzerland. All rights are reserved.

Unauthorized duplication of this document, in whole or in part, by any means is prohibited without

the prior written permission of Enclustra GmbH, Switzerland.

Although Enclustra GmbH believes that the information included in this publication is correct as of

the date of publication, Enclustra GmbH reserves the right to make changes at any time without

notice.

All information in this document is strictly confidential and may only be published by Enclustra

GmbH, Switzerland.

All referenced trademarks are the property of their respective owners.

Document History

Version Date Author Comment

1.11 09.03.2016 D. Ungureanu Updated section Ethernet PHY Configuration

and Secure EEPROM

1.10 15.02.2016 G. Köppel Updated section Ethernet PHY and Secure

EEPROM

1.09 29.07.2014 P. Clements Corrected the naming of the modules in the

Module Configurations section and in the DDR2

SDRAM parameters section

1.08 07.03.2014 B.Pfiffner Updated section DDR2 SDRAM

1.07 10.04.2013 P. Clements Updated to the latest pin naming, removed

Mercury module connector and differential

pairs net lengths tables

1.06 09.04.2013 M. Oberholzer Updated to the latest document template,

added assembly drawings, added information

on differential input termination resistor

identifiers and locations, updated accessories

section, minor improvements throughout the

document

1.05 20.04.2012 S. Ziegler Corrected SPI Flash size to 16 MB

1.04 18.04.2012 S. Ziegler Corrected module dimensions top view (FX10)

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Version Date Author Comment

1.03 9.08.2011 C. Glattfelder Updated SPI Flash programming section

1.02 31.05.2011 M. Oberholzer Corrected LED count in section “Module

Description”

1.01 31.03.2011 C. Glattfelder Differential trace length table added

1.00 16.02.2011 André Schlegel First release

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Table of Contents

1 Overview .......................................................................................................... 8

1.1 General ....................................................................................................................... 8

1.1.1 Warranty ............................................................................................................................... 8

1.1.2 RoHS ...................................................................................................................................... 8

1.1.3 Disposal and WEEE .............................................................................................................. 8

1.1.4 Safety Recommendations and Warnings ......................................................................... 8

1.1.5 Electro-Static Discharge ...................................................................................................... 9

1.1.6 EMC ....................................................................................................................................... 9

1.2 Features ..................................................................................................................... 9

1.3 Deliverables ............................................................................................................... 9

1.4 Accessories .............................................................................................................. 10

1.4.1 Mercury PE1 Board ............................................................................................................ 10

2 Module Description ..................................................................................... 11

2.1 Block Diagram ......................................................................................................... 11

2.2 Module Configurations .......................................................................................... 12

2.3 Part Numbers and Ordering Codes ....................................................................... 12

2.4 Module Top-/Bottom Views .................................................................................. 14

2.4.1 Top View ............................................................................................................................. 14

2.4.2 Bottom View ....................................................................................................................... 14

2.5 Assembly Drawings ................................................................................................ 15

2.5.1 Assembly Drawing (Top View) ......................................................................................... 15

2.5.2 Assembly Drawing (Bottom View) ................................................................................... 16

2.6 Module Footprint ................................................................................................... 17

2.7 Mercury Module Connectors ................................................................................. 18

2.8 User I/Os .................................................................................................................. 19

2.8.1 Pinout .................................................................................................................................. 19

2.8.2 I/O Types ............................................................................................................................. 19

2.8.3 FPGA I/O Banks .................................................................................................................. 22

2.8.4 VREF Usage ......................................................................................................................... 22

2.8.5 VCC_IO Usage .................................................................................................................... 23

2.8.6 Dual Purpose Pins .............................................................................................................. 24

2.8.7 Signal Terminations ........................................................................................................... 24

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2.9 Power ....................................................................................................................... 27

2.9.1 Power Generation Overview ............................................................................................. 27

2.9.2 Power Enable ...................................................................................................................... 27

2.9.3 Supply Voltage Inputs ....................................................................................................... 28

2.9.4 Supply Current Consumption .......................................................................................... 29

2.9.5 Supply Voltage Outputs.................................................................................................... 29

2.9.6 Supply Current Consumption Example ........................................................................... 30

2.9.7 Heat Dissipation ................................................................................................................. 32

2.10 Clock Generation .................................................................................................... 32

2.10.1 Overview ............................................................................................................................. 32

2.10.2 Signal Description .............................................................................................................. 33

2.11 LEDs .......................................................................................................................... 33

2.11.1 FPGA LEDs........................................................................................................................... 33

2.12 DDR2 SDRAM .......................................................................................................... 33

2.12.1 DDR2 SDRAM Type ........................................................................................................... 34


2.12.3 On-Die Termination........................................................................................................... 36

2.12.4 Parameters .......................................................................................................................... 36

2.13 SPI Flash ................................................................................................................... 37

2.13.1 SPI Flash Type ..................................................................................................................... 38


2.13.3 FPGA Bit Streams ............................................................................................................... 39

2.14 Ethernet ................................................................................................................... 39

2.14.1 Ethernet PHY Type ............................................................................................................. 39

2.14.2 Ethernet PHY Configuration ............................................................................................. 40


2.14.4 External Connectivity ......................................................................................................... 42

2.15 USB ........................................................................................................................... 42

2.15.1 USB Device Controller Type ............................................................................................. 42


2.16 RTC ........................................................................................................................... 43

2.16.1 RTC Type ............................................................................................................................. 44

2.17 SHA1-EEPROM ........................................................................................................ 44

2.17.1 EEPROM Type ..................................................................................................................... 44

2.18 Current and Power Monitor .................................................................................. 44

2.18.1 Monitor Type ...................................................................................................................... 44

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3 FPGA Configuration ..................................................................................... 45

3.1 Master Serial Configuration .................................................................................. 45

3.2 SPI Flash Programming .......................................................................................... 46

3.2.1 Signal description .............................................................................................................. 46

3.2.2 In-System-Programming using the Quartus-II Programmer ....................................... 47

3.3 Slave Serial Configuration ..................................................................................... 47


3.4 Firmware Download via USB ................................................................................. 48

3.4.1 FPGA Configuration ........................................................................................................... 49

3.4.2 Flash Programming ........................................................................................................... 50

3.5 JTAG ......................................................................................................................... 50


3.5.2 External connectivity ......................................................................................................... 51

4 I2C Communication ...................................................................................... 52

4.1 Overview .................................................................................................................. 52


4.2 I2C Decive Addresses ............................................................................................. 53

4.3 SHA-1 EEPROM ....................................................................................................... 53

4.3.1 Memory Map ...................................................................................................................... 53

5 Technical Data .............................................................................................. 56

5.1 Absolute Maximum Ratings .................................................................................. 56

5.2 Recommended Operating Conditions .................................................................. 56

5.3 Mechanical Data ..................................................................................................... 57

6 Ordering and Support .................................................................................. 58

6.1 Ordering .................................................................................................................. 58

6.2 Support .................................................................................................................... 58

7 Additional Information ................................................................................ 59

7.1 Mercury Module Connector Pinout ...................................................................... 59

7.2 Differential Pairs Net Length ................................................................................. 59

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1 Overview

1.1 General

The Mercury CA1 FPGA modules are optimized for SoPC high speed communication and DSP

applications. They offer high-performance and yet low-cost Altera Cyclone IV E FPGAs, large and

high-bandwidth memory, an USB 2.0 High-Speed interface, LVDS I/Os as well as a gigabit Ethernet

interface.

The use of Mercury CA1 FPGA modules, in contrast to building a custom FPGA hardware, significantly

simplifies system design and thus shortens time to market and decreases the development effort of

your product.

The Mercury Starter base board enables you to quickly put together a prototyping system and start

developing your system 'hands-on'.

1.1.1 Warranty

For information concerning the warranty please read through the “General Business Conditions” on

Enclustra’s website1.

1.1.2 RoHS

The Mercury module are designed and produced according to the Restriction of Hazardous

Substances (RoHS) Directive (2011/65/EC).

1.1.3 Disposal and WEEE

The Mercury modules must be disposed properly at the end of its life span. If a battery is installed

onto the board it must also be disposed correctly.

The Mercury modules are not designed “ready for operation” for the end-user. The Waste Electrical

and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mercury boards.

Nonetheless users should still dispose the product properly at the end of life.

1.1.4 Safety Recommendations and Warnings

Ensure that the power supply is disconnected from the board before inserting or removing a Mercury

module, connecting interfaces, replacing SD-Cards and batteries, connecting jumpers, etc.

Take special care with the mounting orientation of Mercury modules – they can fit in the connectors

both ways round. The base board and the module may be damaged if inserted the wrong way and

powered up.

Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage.

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Over-voltage on power or signal lines can cause permanent damage.

1.1.5 Electro-Static Discharge

Electronic boards are sensitive to Electro-Static Discharge (ESD). Please ensure that the product is

handled with care and only in an ESD protected environment.

1.1.6 EMC

This is a Class A product and is not intended to be used in domestic environments. The product may

cause electromagnetic interference in which appropriate measures must be taken.

1.2 Features

Altera Cyclone IV E FPGA

Up to 256 MB DDR2 SDRAM

Up to 16 MB SPI Flash

Gigabit Ethernet PHY

25MHz clock generator

Hi-Speed Dual USB UART/FIFO

I2c EEPROM with SHA-1 Engine

24 differential pairs and 98 single-ended user I/Os or 148 single-ended user I/Os

Voltage and temperature monitoring

Single input supply 5..15 V

1.2 V / 1.8 V / 2.5 V / 3.3 V I/Os

Smaller than a credit card: (65 x 54 mm, dual 168-pin Hirose FX10 connectors)

1.3 Deliverables

Mercury CA1 FPGA module

Mercury CA1 user manual2 (this document)

Mercury CA1 pinout list (Microsoft Excel document)

Mercury CA1 Reference Design

Mercury CA1 VHDL Top-Level and pinout files

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Mercury CA1 reduced schematics

Mercury Master pinout excel sheet and Module Pin Connection Guidelines

Mercury CA1 IO Netlength excel sheet

1.4 Accessories

The Mercury-family base boards are ideal for rapid prototyping and low volume series for Mercury

CA1 FPGA module based systems.

1.4.1 Mercury PE1 Board

Dual 168-pin Hirose FX10 connectors for Enclustra Mercury FPGA modules

Low-jitter clock generator

System monitor

System controller

eMMC Managed NAND flash

PCIe 2.0 x4 interface

USB 3.0 device interface

4 × USB 2.0 host interface

USB 2.0 device (UART, SPI, I2C, JTAG)

mPCIe/mSATA card holder

FMC LPC connector

2 × 40-pin Anios pin header

3 × 12-pin Pmod™ pin header

5 to 15V or USB bus power (with restrictions)

More information about the Mercury PE1 Baseboard is found on our webpage.3

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2 Module Description

2.1 Block Diagram

Figure 1: Hardware Block Diagram

The heart of the Mercury CA1 FPGA module is the Altera Cyclone IV E FPGA device. Most of its I/O

pins are connected to the Mercury module connector, making 148 user I/Os available at the Mercury

module connector.

The memory subsystem is built from a 16 MB SPI Flash and a 128 MB DDR2 SDRAM in the standard

configuration.

The FPGA is either configured with a bitstream residing in the SPI Flash, via an USB device controller

fitted on the module, via an external microcontroller or via the JTAG interface connected to Mercury

module connector.

The module is also equipped with a gigabit Ethernet PHY, making it ideal for communication

applications.

A FTDI USB 2.0 High-Speed interface is fitted on the module to easy implement a communication link

to a host PC.

A real time clock as well as a voltage and power monitoring is available on the I2C bus for SOPC

applications.

The 25 MHz clock generation is done based on a 50 MHz crystal oscillator.

The module-internal supply voltages (1.0 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V) are generated from the single

input supply voltage 5..15 V.

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Three yellow LEDs are connected to FPGA pins for easy status signaling.

A yellow LED is connected to a FTDI USB 2.0 High-Speed controller user pin for easy status signaling.

2.2 Module Configurations

Part number FPGA SDRAM Flash Temp Range

ME-CA1-30-8C-D7 EP4CE30F23C8N 128 MB DDR2 16 MB 0..70°C



Table 1: Standard Module Configurations

Table 1 shows the available standard module configurations. Custom configurations are possible;

please contact us for further information.

2.3 Part Numbers and Ordering Codes

Every module has a label with a marking specifying the part number and the serial number, as shown

in Figure 2:

Figure 2: Module label

Table 2 shows the correspondence between part number and ordering code.

Part number Ordering code

EN101228 ME-CA1-115-7I-D8-R6

EN100046 ME-CA1-115-8C-D8-R5

EN100000

SN123456

Part Number

Serial Number

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Part number Ordering code

EN101227 ME-CA1-115-8C-D8-R6

EN101223 ME-CA1-30-7I-D7-R6

EN100930 ME-CA1-30-8C-D7-R4

EN100009 ME-CA1-30-8C-D7-R5

EN101222 ME-CA1-30-8C-D7-R6

EN101226 ME-CA1-75-7I-D7-R6

EN100929 ME-CA1-75-8C-D7-R4

EN100010 ME-CA1-75-8C-D7-R5

EN101225 ME-CA1-75-8C-D7-R6

Table 2: Part Numbers and Ordering Codesa

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2.4 Module Top-/Bottom Views

2.4.1 Top View

Figure 3: Module Top View

2.4.2 Bottom View

Figure 4: Module Bottom View

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2.5 Assembly Drawings

2.5.1 Assembly Drawing (Top View)

Figure 5: Assembly Drawing (Top View)

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2.5.2 Assembly Drawing (Bottom View)

Figure 6: Assembly Drawing (Bottom View)

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2.6 Module Footprint

Figure 7 shows the dimensions of the module footprint on the base board. Maximal component

height under the module is depending on the connector type. See section 2.7 for detailed connector

information.

Figure 7: Module Dimensions Mounting Holes Top View

Warning

The Mercury CA1 FPGA module may be placed the wrong way around on the base

board. Always check that the mounting hole positions on the base board and the

Mercury CA1 FPGA module are aligned!

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5.8

mm

50.2

mm

6.0mm Ø 1.2mm2x

48.0mm

J700

J701

Ø 1.1mm2x

Figure 8: Module Dimensions Module Connector Holes Top View

2.7 Mercury Module Connectors

Two Hirose FX10 168 pin 0.5mm pitch headers with a total of 336 pins have to be integrated on the

base board. Up to four M3 screws may be used to mechanically fasten a Mercury module to the base

board.

The pinout of the module connector is found in section 7.1 on page 59.

Figure 7 shows the mechanical drawing of the module footprint. Table 3 shows the connector type as

well as some additional information. The connector is available with different packaging options

(only tray packaging listed below, see datasheet for detailed options) and different stacking heights.

Reference Type Description Digikey Part Number

Mercury

Module

Connector A/B

FX10A-168P-SV(71) Hirose FX10, 168-pin, 0.5 mm

pitch, 4mm stacking height

FX10A-168P-SV(71)-ND

Mercury

Module

Connector A/B

FX10A-168P-SV1(71) Hirose FX10, 168-pin, 0.5 mm

pitch, 5mm stacking height

FX10A-168P-SV1(71)-ND

Table 3: Mercury Connector Types

Figure 9 shows the pin numbering for the Mercury module connectors J700 and J701. The pins of the

Mercury module connector J700 are numbered J700-1 to J700-168 while the pins of the Mercury

module connector J701 are numbered J701-1 to J701-168.

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Figure 9: Pin Numbering for the Mercury Module Connector (Base Board Top View)

2.8 User I/Os

2.8.1 Pinout

The pinout of the module connector is found in section 7.1 on page 59.

2.8.2 I/O Types

Six different I/O types do exist. The following table shows the characteristics of each I/O type.

TYPE Description Direction Termination Note

IO_Bn_RX_CLKyP_zz

IO_Bn_RX_CLKyN_zz

Differential

Input Clock

Pair

Input

Only

100 Ω

on board

Each differential input clock pair

can optionally be used as two

single ended input clocks. For

that purpose the 100 Ω

termination resistor must be

removed.

IO_Bn_xP_zz

IO_Bn_xN_zz

Differential

IO Pair

Input or

Output

- Each differential IO pair can

optionally be used as two single

ended IOs.

1 167

2 168

Warning

Do not use excessive force to latch a Mercury module into the Mercury connectors

on the base board as this could damage the Mercury module as well as the base

board. Always make sure that the Mercury module is oriented the right way before

plugging it into the base board.

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TYPE Description Direction Termination Note

IO_Bn_RX_xP_zz

IO_Bn_RX_xN_zz

Differential

Input Pair

Input

Only

100 Ω

on board

Each differential input pair can

optionally be used as two single

ended inputs. For that purpose

the 100 Ω termination resistor

must be removed.

Bn_IN_CLKy Single Ended

Input Clock

Input

Only

- -

IO_Bn_zz Single Ended

IO

Input or

Output

- -

IO_Bn_S_zz Restricted

Single Ended

IO

Input or

Output

- These IOs can only be used if no

differential modes of any FPGA

banks are used.

Table 4: I/O Types Description

Key:

n: FPGA I/O bank number

x: Differential pair number

y: Clock input number (according to the FPGA pin name)

zz: FPGA pin number (e.g. AA3)

FPGA

Bank

IO_Bn_RX_CLKyP_zz

IO_Bn_RX_CLKyN_zz

IO_Bn_xP_zz

IO_Bn_xN_zz

IO_Bn_RX_xP_zz

IO_Bn_RX_xN_zz

Bn_IN_CLKy Bn_IO_yy Bn_IOS_yy

Bank 1 - - - - - -

Bank 2 1 pair 9 pairs - - 11 4

Warning

Using differential signals in single ended mode may have an affect to any other

differential signals located on the same FPGA bank. Check the pinout of your FPGA

design using Altera Quartus II.

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FPGA

Bank

IO_Bn_RX_CLKyP_zz

IO_Bn_RX_CLKyN_zz

IO_Bn_xP_zz

IO_Bn_xN_zz

IO_Bn_RX_xP_zz

IO_Bn_RX_xN_zz

Bn_IN_CLKy Bn_IO_yy Bn_IOS_yy

Bank 3 1 pair - 4 pairs - 21 3

Bank 4 1 pair - 4 pairs - 21 3

Bank 5 - 5 pairs - 2 11 10

Bank 6 - - - 2 30 -

Bank 7 - - - - - -

Bank 8 - - - - - -

Total 3 pairs 14 pairs 8 pairs 4 94 20

Table 5: I/O Types vs. FPGA I/O Banks

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2.8.3 FPGA I/O Banks

The FPGA’s I/O pins are grouped into eight I/O banks. All I/O pins within a particular I/O bank must

use the same I/O (VCC_IO) and reference (VREF) voltages. Table 6 shows the main attributes of the

FPGA I/O banks.

Bank Connectivity VCCO VREF

Bank 1 Ethernet, FTDI USB controller, SPI Flash,

I2C, FPGA configuration

3.3 V Not Supported

Bank 2 Mercury module connector User selectable

(VCC_IO_B2)

User selectable


(VCC_IO_B3)

User selectable


(VCC_IO_B4)

User selectable


(VCC_IO_B5)

User selectable


(VCC_IO_B6)

User selectable

Bank 7 DDR2 SDRAM 1.8 V 0.9 V

Bank 8 DDR2 SDRAM, Ethernet 1.8 V 0.9 V

Table 6: FPGA I/O Banks

2.8.4 VREF Usage

Referenced I/O standards using VREF can be used on Mercury module connector. The reference

voltage has to be applied to all VREF pins of the respective bank(s).

If a bank is configured to use an unreferenced I/O standard, the VREF pins of this bank on the

Mercury module connector are available as user I/O pins.

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2.8.5 VCC_IO Usage

The VCC_IO for the I/O banks located on Mercury module connector are configurable by applying the

required voltage to the VCC_IO_B[x] pins on the Mercury module connector.

Table 7 shows the VCC_IO_B[x] pins located on Mercury module connector.

Signal name FPGA Pins FPGA Pin type Supported

Voltages

Connector Pins

VCC_IO_B2 All VCC_IO2 pins VCC_IO2 1.2 V, 1.5 V, 1.8 V,

2.5 V, 3.0 V, 3.3 V

J701-140

J701-143


2.5 V, 3.0 V, 3.3 V

J701-88

J701-95


2.5 V, 3.0 V, 3.3 V

J701-64

J701-67


2.5 V, 3.0 V, 3.3 V

J700-38

J700-41


2.5 V, 3.0 V, 3.3 V

J700-74

J700-77

Table 7: VCCO Pins

Warning

Only use VCCO voltages compliant with the equipped FPGA device. Any other

voltages may damage the equipped FPGA device as well as other devices on the

Mercury CA1 FPGA module.

Do not leave a VCC_IO pin floating. Doing so may damage the equipped FPGA device

as well as other devices on the Mercury CA1 FPGA module.

Warning

Only use VREF voltages compliant with the equipped FPGA device. Any other

voltages may damage the equipped FPGA device as well as other devices on the


Do not leave a VREF pin floating when using a referenced I/O standard. Doing so

may damage the equipped FPGA device as well as other devices on the Mercury CA1

FPGA module.

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2.8.6 Dual Purpose Pins

Table 8 lists pins that have special functions during the FPGA configuration or when activated in the

bitstream. For more details please refer to the Cyclone IV Configuration Handbook11.

FPGA Pin Mercury CA1

Signal

Special Function

CRC_ERROR IO_B6_L21 Active-high signal that indicates that the error-detection circuit has

detected errors in the configuration SRAM bits. This pin is optional

and is used when the CRC error-detection circuit is enabled. This

pin can be set in Quartus II software to support open-drain output.

DEV_CLR# IO_B5_3P_N21 Optional chip-wide reset pin that allows you to override all clears

on all device registers. When this pin is driven low, all registers are

cleared; when this pin is driven high, all registers behave as

programmed.

DEV_OE IO_B5_3N_N22 Optional pin that allows you to override all tri-states on the device.

When this pin is driven low, all I/O pins are tri-stated; when this pin

is driven high, all I/O pins behave as defined in the design.

INIT_DONE IO_B6_L22 This is a dual-purpose status pin and can be used as an I/O pin

when not enabled as INIT_DONE. When enabled, a transition from

low to high at the pin indicates when the device has entered user

mode. If the INIT_DONE output is enabled, the INIT_DONE pin

cannot be used as a user I/O pin after configuration.

Table 8: Dual Purpose Pins

2.8.7 Signal Terminations

2.8.7.1 Differential Inputs

All differential inputs (IO_Bn_RX_xP_zz / IO_Bn_RX_xN_zz) and differential clock inputs

(IO_Bn_RX_CLKyP_zz / IO_Bn_RX_CLKyN_zz) are terminated on the Mercury CA1 module by means

of 100 Ω parallel termination resistors.

These differential inputs can be used as single-ended inputs, if the corresponding 100 Ω parallel

termination resistors are removed from the Mercury CA1 FPGA module. Table 9 shows the resistor

identifiers for each of the differential input pairs.

Differential Input Pair Resistor Identifier

IO_B3_RX_0P_AA8 / IO_B3_RX_0N_AB8 R305


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Differential Input Pair Resistor Identifier

IO_B3_RX_2P_W10 / IO_B3_RX_2N_Y10 R307




IO_B4_RX_2P_W13 / IO_B4_RX_2N_Y13 R311


IO_B2_RX_CLK1P_T2 / IO_B2_RX_CLK1N_T1 R304

IO_B3_RX_CLK6P_AA11 /

IO_B3_RX_CLK6N_AB11

R303

IO_B4_RX_CLK7P_AA12 /

IO_B4_RX_CLK7N_AB12

R300

Table 9: Parallel Termination Resistor Identifiers for Differential Input Pairs

Figure 10 shows the location of the parallel termination resistors for the differential input pairs.

Please see Figure 6 for locating the region of interest on the Mercury CA1 FPGA Module’s bottom

side (use SC3 as orientation reference).

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Figure 10: Parallel Termination Resistor Locations for Differential Input Pairs

2.8.7.2 Differential IOs

Differential IOs (IO_Bn_xP_zz / IO_Bn_xN_zz) are not terminated on the Mercury CA1 module by

external termination resistors. These IOs must be terminated by external termination resistors on the

base board (close to the module pins).

2.8.7.3 Single-Ended Outputs

There are no series termination resistors on the Mercury CA1 module for single-ended outputs. If

required, series termination resistors may be equipped on the base board (close to the module pins).

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2.9 Power

2.9.1 Power Generation Overview

The Mercury CA1 module uses a single power input voltage in the range of 5..15V nominal.

Four supply voltages (3.3V, 2.5, 1.8V, 1.2V) are generated by the module-internal power circuitry.

The 3.3V and the 2.5V voltage are fed to pins on the Mercury module connectors and can thus be

used to power devices on the base board.

A current and power monitor accessible through I2C can be used to observe the power consumption

on the 1.2V voltage that is used as FPGA core voltage.

Please note that the output of the 1.2 V regulator is limited to 8A. Since the power consumption may

be higher for big FPGA devices with high toggling rates, the 1.2V regulator might be replaced by a

12A device for custom configurations.

IR3841

η = 85%

IR3841

ƞ = 90%

LM26420X

ƞ = 85%

Mercury Module Connectors

VCC_IN 5..15V max 3A

1.2V / 8A

2.5V / 2A

1.8V / 2A

FLASH @ 20mA

ETH @ 3mA

FTDI @ 100mA

FGPA_VCCIO1 @ 100mA

VCC_2V5 @ max 1.6A

FPGA @ 200mA

DDR2 @ 400mA

FPGA_VCCIO_7/8 @ 200mA

FTDI @ 50mA

LDO

5V

LP2985-

50

Input

Power

Filter

(10 Pins) VCC_3V3

(10 Pins)

VCC_2V5

(8 Pins)

PWR_GOOD

Current/

Power

Monitor

INA220

LDO

1.0V

LD39015

M10R

1.0V / 150mA

FPGA @ max 8A

5V / 150mA 16mA

16mA

3.3V / 8A VCC_3V3 @ max 3A

PWR_GOOD

PWR_EN

PWR_EN PWR_GOOD

ETH @ 450mA

ETH @ 100mA

I2C

FPGA

PWR_EN PWR_GOODI2C_SCL

I2C_SDA

Figure 11: Power Generation Overview

2.9.2 Power Enable

The Mercury CA1 FPGA module provides a power enable input on the Mercury module connector.

This input may be used to shut down the DC/DC converters for 1.2 V, 1.8 V and 2.5 V generation,

15.02.2016 28 / 63 Version 1.10

which leave the FPGA, the DDR2 SDRAM, the gigabit Ethernet PHY and the FTDI USB controller

unpowered.

The 3.3 V power rail is always active.

The PWR_EN input is pulled to 3.3 V on the Mercury CA1 module with a 2k2 pull-up resistor. Leaving

it unconnected will thus result in an always powered FPGA.

The PWR_GOOD output is pulled to 3.3 V on the Mercury CA1 module with a 2k2 pull-up resistor. It is

pulled down by any of the switching regulators (1.2 V, 1.8 V, 2.5 V or 3.3 V) if a problem occurs.

Pin name Module Connector

Pin

Remarks

PWR_EN J700-10 Floating/3.3V: core power supplies enabled

Tied to GND: core power supplies disabled

PWR_GOOD J700-12 0: at least one power supply not ok

1: all power supplies ok

Table 10: Module Power Enable Pins

2.9.3 Supply Voltage Inputs

A total of 10 Mercury module connector pins are used to feed the input supply voltage to the


The maximum current consumption of the Mercury CA1 FPGA module is limited by the Mercury

module connector, which is rated with 300 mA per pin according to the Hirose FX10 datasheet4. Thus

a maximum current of 3A can be consumed by the Mercury CA1 FPGA module.

Pin name Module

Connector J700

Pins

Module

Connector J701

Pins

Nominal

Voltage

Minimum

Voltage

Maximum

Voltage

Maximum

Current

VCC_MOD 1, 2, 3, 4, 5, 6, 7,

8, 9, 11

- 5 V...15

V

4.75 V 15.75 V 3 A

Table 11: Supply Voltage Inputs

Warning

Do not apply other voltages to the PWR_EN pin than 3.3V or GND. Doing so may

damage the Mercury CA1 FPGA module. It is OK to leave the PWR_EN pin

unconnected.

15.02.2016 29 / 63 Version 1.10

2.9.4 Supply Current Consumption

The total input supply current IVCC_MOD can be expressed as follows

mAINVCC

PIV

IINVCC

PP

IINVCC

PI

VVCCVVCC

VLDOV

VVCC

V

VVCC

VLDOtot

INVCC 162_

90.085.0

2.1

__

33_21_

5_33

33_

21

21_

5__

PVCC_1V2 denotes the total consumed power on the 1.2V power supply while PVCC_3V3 denotes the total

consumed power on the 3.3V power supply. η1V2 and η3V3 denote the efficiency of the 1.2V and 3.3V

DC/DC converters.

Because the 1.8 V and 2.5 V are generated based on the 3.3 V power supply the total consumed

power of the 3.3 V is expressed as

85.0

8.1

85.0

5.23.3

8.15.23.33.3

81_52_

33_

81

81_

52

52_

33_

81

81_

52

52_

33_33_

VVCCVVCC

VVCC

V

VVCC

V

VVCC

VVCC

V

VVCC

V

VVCC

VVCCVVCC

IVIVIV

IVIVIV

PPIVP

According to the equation above the higher the input supply voltage the lower the input supply

current.

2.9.5 Supply Voltage Outputs

Two of the four generated supply voltages on the module can be used to power devices located on

the base board. Table 12 lists the available supply voltages and the respective supply voltage pins.

The maximum current that can be consumed of these output supply voltages are limited by the

Mercury module connector and by the voltage regulators.

Warning

The power consumption of the FPGA is highly dependent on the configured bitstream

and the actual I/O activity. Be sure to connect a power supply that is capable of

delivering the required power. Please calculate the power budget of your design as

described in section 2.9.6.

Make sure that voltage connected to the VCC_MOD pins and the consumed supply

current are within the tolerance specified in Table 11. If this is not the case, the

Mercury CA1 FPGA module will most likely not function properly and may even be

damaged.

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Nominal

Output

Voltage

Vnom

Tolerance

Module Connector J700

Pins


Pins

Max.

Current

Imax

3.3V +/- 5% 26, 29, 50, 86 55, 79, 115, 127, 152, 155 3A

2.5V +/- 5% 53, 62, 65, 89 52, 76, 108, 128 2A

Table 12: Supply Voltage Outputs

2.9.6 Supply Current Consumption Example

This section shows the typical supply current consumption for a mixed SoPC and DSP application for

Cyclone IV E EP4CE30 and EP4CE75 devices.

The tables below list the test conditions that are used to estimate power consumption of the FPGA.

Condition EP4CE30 EP4CE75

SoPC Part

Clock frequency 100 MHz 100 MHz

Number of used LUTs 5000 5000

Number of used FFs 5000 5000

Number of used M9K Block RAMs 16 16

Number of used 18x18 multipliers 4 4

Table 13: FPGA Test Conditions (SOPC)


DSP Part

Clock frequency 250 MHz 250 MHz

Warning

The maximum output current must not be exceeded under any circumstances. Doing

so will most likely cause malfunctions on the Mercury CA1 FPGA module and may

even damage it.

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Number of used LUTs 22700 68000

Number of used FFs 22700 68000

Number of used M9K Block RAMs 48 277

Number of used 18x18 multipliers 62 196

Table 14: FPGA Test Conditions (DSP)

The tables below list the total supply current consumption for different supply voltages and different

FPGA types. Consider that the total supply current consumption I_VCC_MOD can be beyond the

specification for lower input supply voltages VCC_MOD.

Input

Supply

Voltage

VCC_MOD

[V]

I_VCC_1V2

[A]

I_VCC_2V5

external

[A]

I_VCC_2V5

total

[A]

I_VCC_3V3

external

[A]

I_VCC_3V3

total

[A]

I_VCC_MOD

[A]

5 3.36 1.3 1.5 2.5 4.63 4.38

9 3.36 1.3 1.5 2.5 4.63 2.45

12 3.36 1.3 1.5 2.5 4.63 1.84

15 3.36 1.3 1.5 2.5 4.63 1.48

Table 15: Typical Supply Current Consumption EP4CE30

Input

Supply

Voltage

VCC_MOD

[V]

I_VCC_1V2

[A]

I_VCC_2V5

external

[A]

I_VCC_2V5

total

[A]

I_VCC_3V3

external

[A]

I_VCC_3V3

total

[A]

I_VCC_MOD

[A]

5 3.36 1.3 1.5 2.5 4.63 5.54

9 3.36 1.3 1.5 2.5 4.63 3.09

12 3.36 1.3 1.5 2.5 4.63 2.33

15 3.36 1.3 1.5 2.5 4.63 1.87

15.02.2016 32 / 63 Version 1.10

Table 16: Typical Supply Current Consumption EP4CE75

The Mercury CA1 module allows a maximum input supply current of 3.0 A. This input supply current

depends on the FPGA configuration, the current consumption of the 2.5V 3.3V supply voltage which

are fed to the module connector as well as on the input supply voltage.

2.9.7 Heat Dissipation

The required airflow can be calculated by using the Cyclone IV E power estimation spreadsheet

provided by Altera5.

2.10 Clock Generation

2.10.1 Overview

A 50 MHz crystal oscillator is integrated on the Mercury CA1 FPGA module, whose output signal is

divided into a 25 MHz clock. The 25 MHz clock is fed to the FPGA and additionally fed to the Ethernet

PHY.

The Ethernet PHY generates a 125 MHz reference clock based on the 25 MHz clock. This 125 MHz

reference clock is also connected to the FPGA but is not always available (e.g. only a 25 MHz clock is

available when the Ethernet PHY is in reset). For more details please refer to the Marvel 88E1318

Ethernet PHY datasheet.

Warning

The Mercury CA1 module allows a maximum input supply current of 3.0 A. This input

supply current depends on the FPGA configuration, the current consumption of the

2.5V 3.3V supply voltages which are fed to the module connector as well as on the

input supply voltage.

The 1.2 V power supply provides a maximal output current of 8.0A.This may not be

sufficient for larger FPGA devices operated at high clock frequencies (>200MHz) and

signal toggle rates (50%). Please check your design’s power consumption using the

Altera PowerPlay Early Power Estimator Spreadsheet5.

Warning

Always make sure that the required airflow really is available. A heat sink for the

Mercury CA1 module’s FPGA may be required in some cases. Overheating may lead

to damages on the Mercury CA1 FPGA module.

.

15.02.2016 33 / 63 Version 1.10

2.10.2 Signal Description

Clk Signal Name Freq (MHz) FPGA Pin FPGA Pin Type

CLK25 25.0 B12 CLK9/DIFFCLK_5P

CLK125 125.0 A12 CLK8/DIFFCLK_5N

Table 17: Clock Resources

2.11 LEDs

2.11.1 FPGA LEDs

Three yellow LEDs are connected to the FPGA. Optionally, a fourth LED is connected to the FPGA, but

its pin is shared with a control signal of the FTDI USB device controller. In order to use the fourth LED,

resistor R208 must be assembled while R210 has to be removed.

Signal Name FPGA Pin FPGA Pin Type Module Connector

J701

Remarks

Led_N<0> B1 DIFFIO_L2N 29 Active low

Led_N<1> B2 DIFFIO_L2P 33 Active low

Led_N<2> J2 DIFFIO_L23P 37 Active low

LED_N<3>* J1 DIFFIO_L23N 41 Active low

This LED is connected to a

multipurpose pin on the FPGA

and cannot be used by

default.

Table 18: FPGA LEDs

2.12 DDR2 SDRAM

The DDR2 SDRAM equipped on the Mercury CA1 is specified up to 400 MHz (CL 5-5-5) but please

note: The Altera DDR2 memory controller supports only up to 166MHz on Cyclone IV!

15.02.2016 34 / 63 Version 1.10

2.12.1 DDR2 SDRAM Type

Table 19 shows the equipped DDR2 SDRAM types. Please note that other types might be used in

future.

Type Size Configuration Manufacturer Datasheet

W971GG6JB-25 128 MB 64M x 16bit Winbond

W972GG6JB-25 256 MB 128M x 16bit Winbond

Table 19: DDR2 SDRAM Type


Table 20 shows the signals of the FPGA-DDR2 SDRAM interface.

Signal name FPGA Pin FPGA Pin type IO voltage

Ddr2_A<0> E12 DIFFIO_T33P 1.8V

Ddr2_A<1> F13 DIFFIO_T46P 1.8V

Ddr2_A<2> E15 DIFFIO_T52P 1.8V

Ddr2_A<3> E16 DIFFIO_T60N 1.8V



Ddr2_A<6> C19 DIFFIO_T56N 1.8V

Ddr2_A<7> D19 DIFFIO_T56P 1.8V

Ddr2_A<8> B10 DIFFIO_T30P 1.8V

Ddr2_A<9> A7 DIFFIO_T23N 1.8V





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Ddr2_Dq<0> C6 DIFFIO_T15N 1.8V

Ddr2_Dq<1> A3 DIFFIO_T9N 1.8V

Ddr2_Dq<2> B3 DIFFIO_T9P 1.8V



Ddr2_Dq<5> A5 DIFFIO_T18P 1.8V

Ddr2_Dq<6> F10 DIFFIO_T17P 1.8V

Ddr2_Dq<7> F8 DIFFIO_T11N 1.8V







Ddr2_Dq<14> E14 DIFFIO_T46N 1.8V

Ddr2_Dq<15> D13 DIFFIO_T44P 1.8V

Ddr2_Clk_N A18 DIFFIO_T53N 1.8V

Ddr2_Clk_P B18 DIFFIO_T53P 1.8V

Ddr2_Cke A20 PLL2_CLKOUTN 1.8V

Ddr2_Ba<0> E11 DIFFIO_T32N 1.8V

Ddr2_Ba<1> A17 DIFFIO_T50N 1.8V

Ddr2_Ba<2> B17 DIFFIO_T50P 1.8V

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Ddr2_Cs_N B9 DIFFIO_T29P 1.8V

Ddr2_Cas_N A16 DIFFIO_T49N 1.8V

Ddr2_Ras_N C13 DIFFIO_T44N 1.8V

Ddr2_We_N C17 DIFFIO_T54P 1.8V

Ddr2_Dm<0> F7 DIFFIO_T3N 1.8V

Ddr2_Dm<1> F11 DIFFIO_T32P 1.8V

Ddr2_Dqs <0> C8 DIFFIO_T20N 1.8V

Ddr2_Dqs <1> B13 DIFFIO_T35P 1.8V

Ddr2_Odt B20 PLL2_CLKOUTP 1.8V

Table 20: DDR2 SDRAM Signal Description

2.12.3 On-Die Termination

No external termination is implemented on the hardware. It is thus strongly recommended to enable

the DDR2 SDRAM device’s on-die termination (ODT) feature.

2.12.4 Parameters

Module

SDRAM

Size

128 MByte

ME-CA1-30-8C-D7

ME-CA1-75-8C-D7

256 Mbyte

ME-CA1-115-8C-D8

Reference

Design

Data

Width

16 bit 16 bit 16 bit

Bank Bits 3 3 3

Row Bits 13 14 13

Column

Bits

10 10 10

15.02.2016 37 / 63 Version 1.10

Module

SDRAM

Size

128 MByte

ME-CA1-30-8C-D7

ME-CA1-75-8C-D7

256 Mbyte

ME-CA1-115-8C-D8

Reference

Design

FMAX

tCK

166,7 MHz 166,7 MHz 166,7 MHz

CAS

Latency

5 5 5

tRRD 10 ns 10 ns 10 ns

tREFI 7.8 us 7.8 us 7.8 us

tRFC 127.5 ns 195.5 ns 195.5 ns

tRCD 12.5 ns 12.5 ns 12.5 ns

tRP 12.5 ns 13.125 ns 13.125 ns

tCCD 2 2 2

tRC 57.5 ns 58.125 ns 58.125 ns

tWR 15 ns 15 ns 15 ns

tRAS(max) 70 us 70 us 70 us

tRAS(min) 45 ns 45 ns 45 ns

tWTR 7.5 ns 7.5 ns 7.5 ns

Table 21: DDR2 SDRAM Parameters

For the DDR2 Ram are used the data (Reference Design) by the Table 21 DDR2 SDRAM Parameters.

With these parameters can run all different boards with the same bit stream. All the information for

Quartus can be found under Mercury CA1 Memory Templates2.

2.13 SPI Flash

The SPI Flash can be used to store the FPGA bit streams, NIOS II application code and other user data.

It is connected to the FPGAs configuration port and the signals are also available on the Mercury

15.02.2016 38 / 63 Version 1.10

module connector. Please refer to section 3 for more details about FPGA configuration and

programming the Flash memory.

2.13.1 SPI Flash Type

Table 22 shows the equipped SPI Flash device type.

Type Size Manufacturer Datasheet

M25P128-VME6TG 128 Mbit Numonyx / STMicro www.numonyx.com6

Table 22: SPI Flash Type


Table 23 shows the signals of the SPI Flash interface.

Signal name FPGA Pin Mercury Connector Pin IO voltage

CLK K2 J700-118 3.3 V

DO/IO1 K1 J700-122 3.3 V

DI/IO0 D1 J700-114 3.3 V

CS# E2 J700-116 3.3 V

HOLD#/IO3 n.c.

Pulled to VCC_3V3

n.c. -

WP#/IO2 n.c.

Pulled to VCC_3V3

n.c. -

Table 23: SPI Flash Signal Description

Warning

Other Flash memory devices might be equipped on future revisions of the Mercury

CA1 module.

In Slave Serial configuration mode the configuration clock pin can’t be switched to

output mode after configuration. Therefore the SPI Clock must be connected to

another IO pin if the SPI flash shall be used after configuring the FPGA in Slave Serial

mode.

See also section 3 for further information.

15.02.2016 39 / 63 Version 1.10

2.13.3 FPGA Bit Streams

The SPI Flash can be used to store the FPGA configuration bitstream. If the FPGA shall be configured

from the SPI Flash, the bitstream has to be stored at address 0. The size of the bitstream is

dependent of the equipped FPGA type. The remaining SPI Flash sectors are available for user data

storage. See also section 3.

Table 24 shows the bitstream sizes of different FPGAs.

FPGA Size No of Sectors (64kByte)

EP4CE30 9.534 Mbit 146

EP4CE40 9.534 Mbit 146

EP4CE55 14.889 Mbit 228

EP4CE75 19.965 Mbit 305

EP4CE115 28.571 Mbit 436

Table 24: FPGA Bit Stream Sizes

2.14 Ethernet

There is one 10/100/1000 Mbit Ethernet PHY on the CA1 board, connected to the FPGA via the

RGMII interface. The 25 MHz clock for the PHY is generated on board from the 50 MHz oscillator. A

125 MHz reference clock generated by the PHY is fed back to the FPGA.

All necessary components for the Ethernet PHY are on board. The signals on the Mercury Module

connector can be connected directly to the magnetics. The center tap voltage is also provided by the

Mercury CA1 FPGA module (see also section 2.14.4). The LED signals are active low.

2.14.1 Ethernet PHY Type

Table 25 shows the equipped Ethernet PHY device type.

With revision 6, a new type of PHY has been introduced. This requires new software functions to

configure the PHY.

Revision Type Manufacturer MDIO Address Type

R1 to R5 88E1318 Marvell 0 10/100/1000 Mbit

R6 KXZ9031RNXIA Micrel 3 10/100/1000 Mbit

Table 25: Ethernet PHY Type

15.02.2016 40 / 63 Version 1.10

The Marvel 88E1318 datasheet is only available on Marvell’s extranet (account creation required)

(https://extranet.marvell.com/).

2.14.2 Ethernet PHY Configuration

The new Ethernet PHY on the Mercury CA1 module requires the configuration of the RGMII delays in

order to achieve the same timing as the Marvel 88E1318 PHY used in the previous versions.

The steps required for the PHY configuration are presented in Table 26.

Step Register Write Value Description

1 0xD 0x0002 Select MMD Device Address 2h

2 0xE 0x0004 Select RGMII Control Signal Pad Skew Register

3 0xD 0x4002 Select register data for the selected register

4 0xE 0x0070 Write the value for Control Delay (RX delay = 7, TX delay = 0)

5 0xD 0x0002

6 0xE 0x0005 Select RGMII RX Data Pad Skew Register

7 0xD 0x4002

8 0xE 0x7777 Write the value for RX Delay (RX delay = 7 for all lanes)

9 0xD 0x0002

10 0xE 0x0006 Select RGMII TX Data Pad Skew Register

11 0xD 0x4002

12 0xE 0x0000 Write the value for TX Delay (TX delay = 0 for all lanes)

13 0xD 0x0002

14 0xE 0x0008 Select RGMII Clock Pad Skew Register

15 0xD 0x4002

16 0xE 0x03FF Write the value for Clock Delay (RX delay = 31, TX delay = 31)

Table 26 Ethernet PHY Configuration- RGMII Delays

https://extranet.marvell.com/

15.02.2016 41 / 63 Version 1.10

Because the new PHY is on MDIO address 3 and the previous version was on MDIO address 0, there

are no compatibility issues when using a logic block or a firmware code that configures the Micrel

Ethernet PHY. The configuration can be used with any module revision.


Table 27 shows the signals of the Ethernet interface.


ETH_INT# A11 DIFFCLK_4N 1.8 V

ETH_RST# G5 VREFB1N0 3.3 V

ETH_MDC H7 DIFFIO_L1P 3.3 V

ETH_MDIO D10 DIFFIO_T31N 1.8 V

ETH_RXC B11 DIFFCLK_4P 1.8 V

ETH_RX_CTL B6 DIFFIO_T22P 1.8 V

ETH_RXD0 C3 DIFFIO_T4N 1.8 V

ETH_RXD1 C7 DIFFIO_T20P 1.8 V

ETH_RXD2 E7 DIFFIO_T7N 1.8 V

ETH_RXD3 F9 IO 1.8 V

ETH_TXC E5 PLL3_CLKOUTP 1.8 V

ETH_TX_CTL E6 PLL3_CLKOUTN 1.8 V

ETH_TXD0 A6 DIFFIO_T22N 1.8 V

ETH_TXD1 D7 DIFFIO_T15P 1.8 V

ETH_TXD2 A10 DIFFIO_T30N 1.8 V

ETH_TXD3 C4 DIFFIO_T4P 1.8 V

Table 27: Ethernet Signal Description

15.02.2016 42 / 63 Version 1.10

2.14.4 External Connectivity

The Ethernet lines can be directly connected to the magnetics. Please refer to the Mercury Master

Pinout and the Enclustra Module Pin Connection Guidelines for more details about the connection of

Ethernet signals.

2.15 USB

2.15.1 USB Device Controller Type

Table 22 shows the equipped USB controller device type.

Type Manufacturer Datasheet

FT2232HQ FTDI www.ftdichip.com7

Table 28: USB Device Controller type

The FTDI FT2232H USB device controller can be used to easy implement a communication link to a

host PC. Port A is intended for data transfer in UART, SPI, I2C or synchronous FIFO mode. Port B is

used to configure the FPGA, program the SPI Flash and access the I2C bus.

Note that for synchronous FIFO mode an additional D Flip-Flop is inserted for each of the read and

write control signals (FTDI_RD#, FTDI_WR#, see Figure 12) in order to meet the setup time of the

FT2232H. For more information please refer to the schematics.

For more information about the FPGA configuration and SPI Flash programming and I2C bus access

refer to section 3.4.

For more information about the I2C bus access refer to section 4.

Figure 12: FT2232H Synchronous FIFO Mode Connectivity

DQ

DQ

FT2232H Cyclone IV E FPGA

FTDI_CLKOUT

FTDI_D [7:0]

FTDI_OE#

FTDI_RD#

FTDI_WR#

FTDI_RXF#

FTDI_SIWU

FTDI_TXE#

15.02.2016 43 / 63 Version 1.10

Figure 12 shows the connectivity between the FPGA and the FT2232H USB device controller in

synchronous FIFO mode.


Table 27 shows the signals of the USB interface for the synchronous FIFO configuration.


FTDI_CLKOUT G1 CLK1 3.3 V

FTDI_D0 D2 DIFFIO_L5P 3.3 V

FTDI_D1 E1 DIFFIO_L8N 3.3 V

FTDI_D2 E3 DIFFIO_L3N 3.3 V

FTDI_D3 E4 DIFFIO_L3P 3.3 V

FTDI_D4 F1 DIFFIO_L9N 3.3 V

FTDI_D5 F2 DIFFIO_L9P 3.3 V

FTDI_D6 G3 DIFFIO_L1N 3.3 V

FTDI_D7 H6 DIFFIO_L6P 3.3 V

FTDI_OE# J1 DIFFIO_L23N 3.3 V

FTDI_RD# H2 DIFFIO_L13P 3.3 V

FTDI_WR# J6 DIFFIO_L6N 3.3 V

FTDI_RXF# H1 DIFFIO_L13N 3.3 V

FTDI_TXE# J4 DIFFIO_L12P 3.3 V

FTDI_SIWU H5 VREFB1N1 3.3 V

Table 29: FTDI USB Controller in Synchronous FIFO Mode Signal Description

2.16 RTC

A real time clock is connected to the I2C bus. VCC_BAT can be connected directly to a 3V battery or

left open. The RTC also features a battery buffered 128 bytes user SRAM and a temperature sensor.

See section 4 for more details about the I2C bus on the Mercury CA1.

15.02.2016 44 / 63 Version 1.10

2.16.1 RTC Type

Table 25 shows the equipped RTC device type.


ISL12020M Intersil www.intersil.com8

Table 30: Real Time Clock Type

2.17 SHA1-EEPROM

The security EEPROM is used to store the module type and serial number as well as the Ethernet

MAC address and other information. It is connected to the I2C bus. See section 4 for more details.

This EEPROM should only be read be the user.

With revision 6 a new type of EEPROM has been introduced. This requires new software functions to

access the module information. Refer to the EEPROM manufacturer’s datasheet for details.

2.17.1 EEPROM Type

Table 31 shows the equipped EEPROM device type.

Revision Type Manufacturer Datasheet

R1 to R5 DS28CN01 Maxim www.maxim-ic.com9

R6 ATSHA204A Atmel

Table 31: EEPROM Type

2.18 Current and Power Monitor

An I2C current and power monitor can be equipped to monitor the 1.2V supply. The shunt for the

monitor is 5 mΩ. See section 4 for more details about the I2C bus on the Mercury CA1.

2.18.1 Monitor Type

Table 32 shows the equipped current monitor device type.


INA220 TI www.ti.com10

Table 32: Current Monitor Type

15.02.2016 45 / 63 Version 1.10

3 FPGA Configuration

Table 33 shows the FPGA configuration pins and their location on the Mercury module connector.

These signals allow to boot the FPGA from the SPI Flash (section 3.1), to program the SPI Flash from

an external device (section 3.2) or to directly configure the FPGA from an external device (section

3.2.2).

The pins MSEL0, MSEL2 and MSEL3 of the FPGA are always low.

Signal Name FPGA Pin FPGA Pin Type SPI Flash Pin Mercury

Module

Connector Pin

FPGA_DCLK K2 DCLK CLK J700-118

FPGA_DI K1 IO/DATA0 DO J700-122

FPGA_STATUS# K6 STATUS# - J700-124

FPGA_CONF_DONE M18 CONF_DONE - J700-130

FPGA_CONFIG# K5 CONFIG# - J700-132

FPGA_MODE (L18)1 MSEL1 - J700-126

FLASH_DI D1 DIFFIO_L5N DI J700-114

FLASH_CS# E2 DIFFIO_L8P CS# J700-116

Table 33: FPGA Configuration Interface

3.1 Master Serial Configuration

In master serial configuration mode the FPGA reads the bitstream from the SPI Flash. The bitstream

must be located at address 0x0.

1 This signal is inverted on the Mercury CA1 module and thus not directly connected to the FPGA.

Warning

All configuration signals except FPGA_STATUS#, FPGA_MODE and FPGA_CONFIG#

must be high impedance as soon as the FPGA is programmed! Violating this rule may

damage the equipped FPGA device as well as other devices on the Mercury CA1

FPGA module.

15.02.2016 46 / 63 Version 1.10

Signal Name Description

FPGA_DCLK Must be high impedance during configuration and operation

FPGA_DI Must be high impedance during configuration and operation

FPGA_STATUS# Is used as input to delay the start of the configuration when pulled low and is

pulled low by the FPGA if any CRC error occurs during the configuration.

FPGA_CONF_DONE Goes high after configuration (when enabled in the bitstream)

FPGA_CONFIG# When pulled low, the FPGA is de-configured and all pins are tri-stated.

The rising edge of FPGA_CONFIG# initializes the configuration.

FPGA_MODE Must be pulled down during and after configuration. Use a resistor

(100R..560R) and do not connect FPGA_MODE directly to GND.

FLASH_DI Must be high impedance during configuration and operation

FLASH_CS# Must be high impedance during configuration and operation

Table 34: Master Serial Configuration Signal Description

3.2 SPI Flash Programming

The signals of the SPI Flash are directly connected to the module connector. Because the SPI Flash

signals are also connected to the FPGA, the FPGA pins must be tri-stated while accessing the SPI Flash

directly. This is ensured by pulling the FPGA_CONFIG# signal to GND and the FPGA_MODE signal to

VCC.

3.2.1 Signal description


FPGA_DCLK SPI clock

FPGA_DI SPI MISO

FPGA_CONFIG# Must be pulled to GND during SPI Flash programming. When released, all

pins of the SPI interface must be high impedance!

FPGA_MODE Must be high during the flash programming to put the SPI interface of the

FPGA into high impedance mode! When FPGA_MODE is low, all pins of the

SPI interface must be high impedance!

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FLASH_DI SPI MOSI

FLASH_CS# SPI CS#

Table 35: Flash Programming Signal Description

3.2.2 In-System-Programming using the Quartus-II Programmer

To do in-system programming with the Quartus-II Programmer (Cyclone IV datasheet section 811) the

configuration signals have to be connected as shown in Table 36. Further, a jumper or DIP switch on

the signal FPGA_MODE to GND must be installed. FPGA_MODE must be pulled to GND to allow the

FPGA to load the bitstream from the SPI flash. But for the flash programming FPGA_MODE must be

high.

Signal Name Altera ByteBlaster Connector Signal Name

FPGA_DCLK 1 2 GND

FPGA_CONF_DONE 3 4 VCC

FPGA_CONFIG# 5 6 Open

FPGA_DI 7 8 FLASH_CS#

FLASH_DI 9 10 GND

Table 36: Altera ByteBlaster Connector Pinout for in-System Flash Programming

3.3 Slave Serial Configuration

In the slave serial configuration mode, the bitstream is transmitted from an external device to the

FPGA.

The configuration pins of the FPGA are connected directly to the Mercury module connector. This

allows configuring the FPGA from a microcontroller or another SPI capable device.

Warning

Accessing the SPI Flash directly without pulling FPGA_CONFIG# to GND and

FPGA_MODE to VCC may damage the equipped FPGA device as well as other devices

on the Mercury CA1 FPGA module.

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Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the

device. For more details about the Altera configuration interface please refer to the Cyclone IV

configuration handbook11.

FPGA_DCLK remains in input mode after the configuration has finished. If the SPI Flash shall be

accessed after slave serial configuration, another IO pin must be connected to the FPGA_DCLK signal

on the base board.



FPGA_DCLK Configuration clock

FPGA_DI Configuration data

FPGA_STATUS# Is pulled low by the FPGA if any CRC error occurs during the configuration.

FPGA_CONF_DONE Goes high after configuration

FPGA_CONFIG# When pulled low, the FPGA is de-configured and all pins are tri-stated.

The rising edge of FPGA_ CONFIG # initializes the configuration.

FPGA_MODE Must be pulled high (or left open) during and after configuration

Table 37: Slave Serial Configuration Signal Description

3.4 Firmware Download via USB

The FPGA configuration interface and SPI Flash signals are connected to the FTDI FT2232H USB

device controller. This allows to configuring the FPGA over USB or programming the SPI flash from a

PC without any additional hardware. The Enclustra FPGA module configuration tool is available for

download on our homepage and offers both, FPGA configuration and Flash programming via USB.

The FPGA is configured in serial slave mode; please refer also to section 3.2.2.

Port A of the FT2232H is used in synchronous FIFO mode to transfer data between the FPGA and the

USB master. Port B of the FT2232H is used to interface to the I2C pins of the Mercury CA1 FPGA

module and to program the SPI Flash or to configure the FPGA in passive serial mode. Furthermore,

general purpose IO pins of Port B are used to control the configuration multiplexers (U1103..1107).

The configuration multiplexers allow 4 different states as shown in Table 38.

While accessing the SPI flash it is required to set FPGA_CONFIG# low to ensure that the FPGA SPI

link is inactive!

15.02.2016 49 / 63 Version 1.10

Don’t connect FPGA_MODE directly to GND on the base board. Otherwise the Firmware download

and flash programming via USB will not work.

I2C bus access is still possible after the FPGA has been configured.

State CONFIG_EN# FPGA_MODE FPGA_CONFIG# CONFIG_I2C_EN#

High impedance 1 X 1 1

FPGA

configuration

0 1 1 1

SPI Flash access 0 0 0 1

I2C access X X X 0

Table 38: FPGA Configuration States

3.4.1 FPGA Configuration

Table 39 shows the connections for the FT2232H for FPGA configuration only. See also section 3.2.2

and refer to the Cyclone IV configuration handbook11.

FT2232

Port

Signal Dir Static

Value

Description

BDBUS0 CONFIG_CLK O - FPGA configuration clock

BDBUS1 CONFIG_DO O - FPGA configuration data

BCBUS1 FPGA_CONF_DONE I -

BCBUS2 FPGA_STATUS# I -

BCBUS3 FPGA_CONFIG# O -

BCBUS4 FPGA_MODE O 1 FPGA configuration mode select

BCBUS5 CONFIG_EN# O 0 Configuration multiplexer control signal

BCBUS6 CONFIG_I2C_EN# O 1 Configuration multiplexer control signal

Warning

After FPGA configuration or flash programming operations the configuration

multiplexers must be set to high impedance mode! Otherwise the FPGA may not work

correctly or might be damaged!

15.02.2016 50 / 63 Version 1.10

Table 39: USB Configuration Circuit for FPGA Configuration

3.4.2 Flash Programming

Table 39 shows the connections for the FT2232H for Flash programming only. See also section 3.2

and refer to the SPI Flash datasheet6.

FT2232

Port

Signal Dir Static

Value

Description

BDBUS0 CONFIG_CLK O - SPI clock

BDBUS1 CONFIG_DO O - SPI write data

BDBUS2 CONFIG_DI I - SPI read data

BDBUS3 CONFIG_CS# O - SPI chip select

BCBUS3 FPGA_CONFIG# O 0

BCBUS4 FPGA_MODE O 0 FPGA configuration mode select

BCBUS5 CONFIG_EN# O 0 Configuration multiplexer control signal

BCBUS6 CONFIG_I2C_EN# O 1 Configuration multiplexer control signal

Table 40: USB Configuration Circuit for Flash Programming

3.5 JTAG

The FPGA can be configured using the JTAG interface. Also some development features tool as the

NIOS II Debugger and Altera SignalTap II Logic Analyzer use the JTAG interface.


The JTAG pins of the FPGA are connected directly to the module connector.

Signal Name FPGA Pin FPGA Pin Type Mercury Module

Connector Pin

JTAG_TCK L2 TCK J700-123

JTAG_TMS L1 TMS J700-119

JTAG_TDI L5 TDI J700-117

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Signal Name FPGA Pin FPGA Pin Type Mercury Module

Connector Pin

JTAG_TDO L4 TDO J700-121

Table 41: JTAG Interface

3.5.2 External connectivity

Figure 13 shows the external connectivity of the JTAG connector for use with the Altera Download

Cables12. No pull-up/down resistors are necessary.

The FPGA as well as the SPI Flash may be configured conveniently by making use of the Altera

Quartus II Programmer software13 which is part of the Altera Quartus II Web Edition Software14.

Figure 13: JTAG Connectivity on Base Board

15.02.2016 52 / 63 Version 1.10

4 I2C Communication

4.1 Overview

The I2C bus on the Mercury CA1 connects the FPGA, the EEPROM, the RTC, the current monitor and

the FT2232H USB controller through the configuration multiplexer and is also available on the

module connector. This allows external devices to read for example the module type and

configuration from the EEPROM.

Figure 14: I2C Overview


Table 42 shows the signals of the I2C interface. All signals have a pull up to VCC_3V3.

Signal name FPGA Pin FPGA Pin type IO voltage FT2232H Pin Connector

Pin

I2C_SDA C2 DIFFIO_L4P VCC_3V3 BDBUS1 /

BDBUS2

J700-113

I2C_SCL C1 DIFFIO_L4N VCC_3V3 BDBUS0 J700-111

I2C_INT# J3 VREFB1N2 VCC_3V3 - J700-115

Table 42: I2C Signal Description

Current

Monitor

SHA-1

EEPROMRTC

Mercury CA1 FPGA Module

FPGA

I2C Bus

FT2232H

USB

controller

ConfigMux


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4.2 I2C Decive Addresses

Device Address (7 bit) Device

0x40 Current Monitor

0x50 SHA-1EEPROM

0x57 RTC User SRAM

0x6F RTC Registers

Table 43: I2C Device Addresses

4.3 SHA-1 EEPROM

The SHA-1 EEPROM is used to store the module serial number and configuration.

In future, it will also be used for copy protection and licensing features. Please contact us for further

information.

4.3.1 Memory Map

The SHA-1 EEPROM has 4 sectors of 256 bit each.

Sector 0 is used to store the module information and the Ethernet MAC address.

Sector 1..3 are reserved for future use.

Address Length

(Bit)

Description

0x00 32 Module Serial Number

0x04 32 Module Product Number

0x08 32 Module Configuration

0x0C 32 Reserved

0x10 48 Ethernet MAC Address

0x16 48 Reserved

0x1C 32 Checksum

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Table 44: SHA-1 EEPROM Sector 0 Memory Map

4.3.1.1 Module Serial Number

The module serial number is a unique 32 bit number that identifies the module. It is stored using big-

endian byte order (MSB on the lowest address).

4.3.1.2 Module Product Number

Module Product Family Subtype Rev. Product Number

Mercury CA1 0x0322 0x00 0x01 0x0322 0001

Table 45: Product Number

4.3.1.3 Module Configuration

The memory sizes are defined as Resolution*2(Value-1) (e.g. DRAM=0: not Equipped, DRAM=1: 8MB,

DRAM=2: 16MB, DRAM=3: 32MB, etc).

Address Bits Comment Min Value Max Value Resolution

0x08 7..4

3..0

FPGA Type

FPGA Speed Grade

0

6

4

8

See Table 47

0x09 7

6

5..4

3

2

1

0

Temperature Range

Power

No of Ethernet Ports

Gigabit Ethernet

RTC equipped

Current monitor equipped

Reserved

0 (Consumer)

0 (Normal)

0

0 (Fast only)

0

0

-

1 (Industrial)

1 (Low Power)

2

1

1

1

-

0x0A 7..2

1..0

Reserved

USB Device Ports

-

0

-

1

0x0B 7..4

3..0

DDR2 RAM Size

Flash Memory Size

0 MB

0 MB

128 GB

16 GB

8 MBytes

1 MBytes

Table 46: Module Configuration

Value FPGA Type

0x0 Cyclone IV E30

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Value FPGA Type

0x1 Cyclone IV E40

0x2 Cyclone IV E55

0x3 Cyclone IV E75

0x4 Cyclone IV E115

Table 47: FPGA Types

4.3.1.4 MAC Address

The MAC address used for Ethernet communication is stored using big-endian byte order (MSB on

the lowest address).

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5 Technical Data

5.1 Absolute Maximum Ratings

Symbol Rating Unit

VCC_MOD Supply voltage relative to GND -0.5 to 15.75 V

VCC_IO_B[x] I/O banks power supply voltage relative to GND -0.5 to 3.9 V

V_IO I/O input voltage relative to GND2 -0.5 to 3.95 V

Temp Ambient temperature for customer modules

Ambient temperature for industrial modules

0 to +70

-40 to +85

°C

Table 48: Absolute Maximum Ratings

5.2 Recommended Operating Conditions

Symbol Rating Unit

VCC_MOD Supply voltage relative to GND 4.75V to 15.75V V

VCC_IO_B[x] I/O banks power supply voltage relative to GND 1.14 to 3.46 V

V_IO I/O input voltage relative to GND2 -0.5 to 3.6 V

Temp Ambient temperature for customer modules

Ambient temperature for industrial modules

0 to +70

-40 to +85

°C

Table 49: Recommended Operating Conditions

2 For details please refer to the Cyclone IV FPGA I/O interfaces handbook.

15.02.2016 57 / 63 Version 1.10

5.3 Mechanical Data

Symbol Value

Size 56.0 x 54.0 mm

Component height top 3.0 mm

Component height bottom 1.2 mm 3

Weight 18 g

Table 50: Mechanical Data

3 This value does not consider the module connectors that are fitted on the bottom side.

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6 Ordering and Support

6.1 Ordering

Please use Enclustra's online request/order form for ordering or requesting information:

http://www.enclustra.com/order

6.2 Support

Please follow the instructions on Enclustra's online support site:

http://www.enclustra.com/support

http://www.enclustra.com/order

http://www.enclustra.com/support

15.02.2016 59 / 63 Version 1.10

7 Additional Information

7.1 Mercury Module Connector Pinout

The Mercury module connector pinout is available as a Microsoft Excel file from Enclustra’s website:

http://www.enclustra.com/en/products/fpga-modules/mercury-ca1/#downloads

7.2 Differential Pairs Net Length

If using differential pairs, a differential impedance of 100 Ohms should be met on the base board.

Make sure that the two nets of a differential pair have the same length.

The lengths of the differential pair trace lines on the Mercury CA1 FPGA module are available in a

Microsoft Excel file from Enclustra’s website:




15.02.2016 60 / 63 Version 1.10

Figures

Figure 1: Hardware Block Diagram ................................................................................................... 11

Figure 2: Module label ........................................................................................................................ 12

Figure 3: Module Top View ................................................................................................................ 14

Figure 4: Module Bottom View ......................................................................................................... 14

Figure 5: Assembly Drawing (Top View) .......................................................................................... 15

Figure 6: Assembly Drawing (Bottom View) .................................................................................... 16

Figure 7: Module Dimensions Mounting Holes Top View ............................................................. 17

Figure 8: Module Dimensions Module Connector Holes Top View ............................................. 18

Figure 9: Pin Numbering for the Mercury Module Connector (Base Board Top View) ............. 19

Figure 10: Parallel Termination Resistor Locations for Differential Input Pairs ........................... 26

Figure 11: Power Generation Overview ............................................................................................ 27

Figure 12: FT2232H Synchronous FIFO Mode Connectivity .......................................................... 42

Figure 13: JTAG Connectivity on Base Board ................................................................................... 51

Figure 14: I2C Overview ...................................................................................................................... 52

Tables

Table 1: Standard Module Configurations ....................................................................................... 12

Table 2: Part Numbers and Ordering Codesa ................................................................................. 13

Table 3: Mercury Connector Types ................................................................................................... 18

Table 4: I/O Types Description .......................................................................................................... 20

Table 5: I/O Types vs. FPGA I/O Banks ............................................................................................. 21

Table 6: FPGA I/O Banks ..................................................................................................................... 22

Table 7: VCCO Pins.............................................................................................................................. 23

Table 8: Dual Purpose Pins ................................................................................................................ 24

15.02.2016 61 / 63 Version 1.10

Table 9: Parallel Termination Resistor Identifiers for Differential Input Pairs ............................. 25

Table 10: Module Power Enable Pins ............................................................................................... 28

Table 11: Supply Voltage Inputs ....................................................................................................... 28

Table 12: Supply Voltage Outputs .................................................................................................... 30

Table 13: FPGA Test Conditions (SOPC) ........................................................................................... 30

Table 14: FPGA Test Conditions (DSP).............................................................................................. 31

Table 15: Typical Supply Current Consumption EP4CE30.............................................................. 31

Table 16: Typical Supply Current Consumption EP4CE75.............................................................. 32

Table 17: Clock Resources .................................................................................................................. 33

Table 18: FPGA LEDs ........................................................................................................................... 33

Table 19: DDR2 SDRAM Type ............................................................................................................ 34

Table 20: DDR2 SDRAM Signal Description .................................................................................... 36

Table 21: DDR2 SDRAM Parameters ................................................................................................. 37

Table 22: SPI Flash Type ..................................................................................................................... 38

Table 23: SPI Flash Signal Description .............................................................................................. 38

Table 24: FPGA Bit Stream Sizes ........................................................................................................ 39

Table 25: Ethernet PHY Type ............................................................................................................. 39

Table 26: Ethernet Signal Description .............................................................................................. 41

Table 27: USB Device Controller type ............................................................................................... 42

Table 28: FTDI USB Controller in Synchronous FIFO Mode Signal Description .......................... 43

Table 29: Real Time Clock Type ......................................................................................................... 44

Table 30: EEPROM Type ..................................................................................................................... 44

Table 31: Current Monitor Type ........................................................................................................ 44

Table 32: FPGA Configuration Interface ........................................................................................... 45

Table 33: Master Serial Configuration Signal Description ............................................................. 46

Table 34: Flash Programming Signal Description ........................................................................... 47

15.02.2016 62 / 63 Version 1.10

Table 35: Altera ByteBlaster Connector Pinout for in-System Flash Programming ................... 47

Table 36: Slave Serial Configuration Signal Description ................................................................ 48

Table 37: FPGA Configuration States................................................................................................ 49

Table 38: USB Configuration Circuit for FPGA Configuration ....................................................... 50

Table 39: USB Configuration Circuit for Flash Programming ........................................................ 50

Table 40: JTAG Interface ..................................................................................................................... 51

Table 41: I2C Signal Description ....................................................................................................... 52

Table 42: I2C Device Addresses ......................................................................................................... 53

Table 43: SHA-1 EEPROM Sector 0 Memory Map .......................................................................... 54

Table 44: Product Number ................................................................................................................. 54

Table 45: Module Configuration ....................................................................................................... 54

Table 46: FPGA Types ......................................................................................................................... 55

Table 47: Absolute Maximum Ratings .............................................................................................. 56

Table 48: Recommended Operating Conditions ............................................................................ 56

Table 49: Mechanical Data ................................................................................................................. 57

References

1 Enclustra General Business Conditions

http://www.enclustra.com/en/products/gbc/

2 Mercury CA1 User Manual, Enclustra GmbH, 2016

http://download.enclustra.com/#Mercury_CA1

3 Mercury Baseboard PE1

http://www.enclustra.com/en/products/base-boards/mercury-pe1/

4 Hirose FX10 Series Product Website

http://www.hirose-connectors.com/connectors/H205SeriesGaiyou.aspx?c1=FX10&c3=3

5 Cyclone III, Cyclone IV and Cyclone V PowerPlay Early Power Estimator

http://www.altera.com/support/devices/estimator/cy3-estimator/cy3-power_estimator.html

6 64-Mbit, serial Flash memory with SPI bus interface: M25P64-VME6TG

http://www.numonyx.com

http://www.enclustra.com/en/products/gbc/

http://download.enclustra.com/#Mercury_CA1

http://www.enclustra.com/en/products/base-boards/mercury-pe1/

http://www.hirose-connectors.com/connectors/H205SeriesGaiyou.aspx?c1=FX10&c3=3

http://www.altera.com/support/devices/estimator/cy3-estimator/cy3-power_estimator.html

http://www.numonyx.com/

15.02.2016 63 / 63 Version 1.10

7 FTDI USB 2.0 High-Speed Device Controller : FT2232HQ

http://www.ftdichip.com

8 Real Time Clock with embedded crystal: ISL12020M

http://www.intersil.com

9 1kbit I2C EEPROM with SHA1 Engine: DS28CN01

http://www.maxim-ic.com

10 Current/Power Monitor with two-wire interface: INA220

http://www.ti.com

11 Configuration and Remote System Upgrades in Cyclone IV Devices

http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf

12 Altera Download Cables Product Website

http://www.altera.com/products/devkits/kit-cables.html

13 Altera Design Software Product Website

http://www.altera.com/products/software/sfw-index.jsp

14 Altera Quartus II Stand-Alone Programmer Product Website

https://www.altera.com/download/programming/quartus2/pq2-index.jsp

http://www.ftdichip.com/

http://www.intersil.com/

http://www.maxim-ic.com/

http://www.ti.com/

http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf

http://www.altera.com/products/devkits/kit-cables.html

http://www.altera.com/products/software/sfw-index.jsp

https://www.altera.com/download/programming/quartus2/pq2-index.jsp

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