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CADSL Operating System Memory Management Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: [email protected] EE-717/453:Advance Computing for Electrical Engineers Lecture 26 (07 Nov 2013)

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  • CADSL

    Operating SystemMemory Management

    Virendra SinghAssociate ProfessorComputer Architecture and Dependable Systems LabDepartment of Electrical EngineeringIndian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/E-mail: [email protected]

    EE717/453:Advance Computing for Electrical Engineers

    Lecture 26 (07 Nov 2013)

  • CADSL2

    Memory Management• Ideally programmers want memory that is

    – large– fast– non volatile

    • Memory hierarchy – small amount of fast, expensive memory – cache – some medium-speed, medium price main memory– gigabytes of slow, cheap disk storage

    • Memory manager handles the memory hierarchy

    07 Nov 2013 EE-717@IITB

  • CADSL3

    Virtual Memory: Paging (1)

    The position and function of the MMU

    07 Nov 2013 EE-717@IITB

  • CADSL4

    Paging (2)

    The relation betweenvirtual addressesand physical memory addres-ses given bypage table

    07 Nov 2013 EE-717@IITB

  • CADSL5

    Page Tables (1)

    Internal operation of MMU with 16 4 KB pages07 Nov 2013 EE-717@IITB

  • CADSL6

    Page Tables (2)

    • 32 bit address with 2 page table fields• Two-level page tables

    Second-level page tables

    Top-level page table

    07 Nov 2013 EE-717@IITB

  • CADSL7

    Page Tables (3)

    Typical page table entry

    07 Nov 2013 EE-717@IITB

  • CADSL8

    TLBs – Translation Lookaside Buffers

    A TLB to speed up paging

    07 Nov 2013 EE-717@IITB

  • CADSL9

    Inverted Page Tables

    Comparison of a traditional page table with an inverted page table

    07 Nov 2013 EE-717@IITB

  • CADSL10

    Page Replacement Algorithms

    • Page fault forces choice – which page must be removed– make room for incoming page

    • Modified page must first be saved– unmodified just overwritten

    • Better not to choose an often used page

    – will probably need to be brought back in soon

    07 Nov 2013 EE-717@IITB

  • CADSL11

    Optimal Page Replacement Algorithm

    • Replace page needed at the farthest point in future

    – Optimal but unrealizable

    • Estimate by …– logging page use on previous runs of process– although this is impractical

    07 Nov 2013 EE-717@IITB

  • CADSL12

    Not Recently Used Page Replacement Algorithm

    • Each page has Reference bit, Modified bit– bits are set when page is referenced,

    modified• Pages are classified

    – not referenced, not modified– not referenced, modified– referenced, not modified– referenced, modified

    • NRU removes page at random– from lowest numbered non empty class07 Nov 2013 EE-717@IITB

  • CADSL13

    FIFO Page Replacement Algorithm

    • Maintain a linked list of all pages – in order they came into memory

    • Page at beginning of list replaced

    • Disadvantage– page in memory the longest may be often used

    07 Nov 2013 EE-717@IITB

  • CADSL14

    Second Chance Page Replacement Algorithm

    • Operation of a second chance– pages sorted in FIFO order– Page list if fault occurs at time 20, A has R bit set

    (numbers above pages are loading times)

    07 Nov 2013 EE-717@IITB

  • CADSL15

    The Clock Page Replacement Algorithm

    07 Nov 2013 EE-717@IITB

  • CADSL16

    Least Recently Used (LRU)• Assume pages used recently will used again

    soon– throw out page that has been unused for longest

    time

    • Must keep a linked list of pages– most recently used at front, least at rear– update this list every memory reference !!

    • Alternatively keep counter in each page table entry

    – choose page with lowest value counter– periodically zero the counter

    07 Nov 2013 EE-717@IITB

  • CADSL17

    Simulating LRU in Software (1)

    LRU using a matrix – pages referenced in order 0,1,2,3,2,1,0,3,2,3

    07 Nov 2013 EE-717@IITB

  • CADSL18

    Simulating LRU in Software (2)

    • The aging algorithm simulates LRU in software

    • Note 6 pages for 5 clock ticks, (a) – (e)07 Nov 2013 EE-717@IITB

  • CADSL19

    The Working Set Page Replacement Algorithm

    • The working set is the set of pages used by the k most recent memory references

    • w(k,t) is the size of the working set at time, t

    07 Nov 2013 EE-717@IITB

  • CADSL20

    Review of Page Replacement Algorithms

    07 Nov 2013 EE-717@IITB

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