maste thesis ap thiago assis

Analysis of Transistor Sizing and Folding Effectiveness to

Mitigate Soft ErrorsThiago Rocha de Assis

Advisor: Ricardo Augusto da Luz ReisCo-Advisor: Fernanda Gusmão de Lima Kastensmidt

• Introduction

• Single Event Effect

• 3D NMOSFET Device

• Ion Profile

• Transistor Sizing

• Transistor Folding

• Case Study – 6T SRAM Cell

• Conclusions

OutlineOutlineIntroductionSingle Event Effect

2

Introduction

1

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding

Case Study – 6T SRAM Cell

Conclusions3

• Motivation

– Necessity of apply an accurate methodology to evaluate transient effects caused by radiation in integrated circuits

– Reduce the tolerance of transistors to radiation with the scale of technology

• Objective

– Evaluate the effectiveness of transistor sizing and folding techniques to mitigate soft errors

OutlineIntroduction: Motivation & Obj.Methodology

Motivation & Objective

4

Introduction: Motivation & Obj.MethodologySources of Radiation

Methodology

Mesh refinements..

5

MethodologySources of RadiationSAA

Sources of Radiation

• Sources of Radiation

– Cosmic rays + Sun + Trapped Particles

(Bo

ud

eno

t, 2

00

6)

“Radiation is defined as energy in transit in the form of high-speed particles or electromagnetic waves (YAVORSKY, 1972).”

6

Sources of RadiationSAARadiation Effects in IC

SAA

(Boudenot, 2006)7

• Transient vs. Permanent Errors

• Permanent effects

– Total Ionizing Dose (TID)

– Displacement Damage (DD).

• Transient effects

– Single Event Transient (SET)

– Single Event Upset (SEU)

– Single Bit Upset (SBU) and Multiple Bit Upset (MBU).

SAARadiation Effects in ICSingle Event Effects

Radiation Effects in IC

Many others…. Single Event Latchup (SEL), Single Event Gate Rupture (SEGR), Single Event Functional Interruption (SEFI)

8

Total Ionizing Dose Displacement Damage

SAARadiation Effects in ICSingle Event Effects

Radiation Effects in IC

Lon

g te

rm d

egr

adat

ion

……

(ECOFFET, 2007)

(NASA, 1993) 9

Single Event Effect

2

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions10

• Single Event Effect

– The SEE generation mechanism.

Radiation Effects in ICSingle Event Effect3D NMOSFET Device

Single Event Effect

11

3D NMOSFET Device

3

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions12

Single Event Effect3D NMOSFET Device3D NMOSFET vs. PTM L54

3D NMOSFET Device

Region Width (x) Width(y) Width (z) Doping

LDD 115 nm 30 nm 240 nm n-type. Peak: 1e19

Source\Drain 240 nm 60 nm 240 nm n-type. Peak:1e20

SSR 90 nm 5 nm 240 nm n-type. Peak:1.5e18

Gate 136 nm 300 nm 240 nm n-type. Peak:2e20

Oxide 136 nm 1.4 nm 240 nm None

Substrate 0.9 1.5 0.3 um p-type. Peak:5.5e18

(MIT, Well tempered bulk CMOS,2008)

(DASGUPTA, Vanderbilt University. 2007)13

Single Event Effect3D NMOSFET Device3D NMOSFET vs. PTM L54

3D NMOSFET Device

Device modeled using Davinci tool from Synopsys.

Methods:1. Numerical method of Newton2. Incomplete Cholesky Conjugate Gradients (ICCG).

Substrate Contact

Gate

DrainSource

Physical Models:1. Shockley-Read-Hall Model -

SRH 2. Auger Recombination Model

- AUGER 3. Carrier-Carrier Scattering

Mobility Model - CCSMOB 4. Bang-Gap Narrowing Model -

BGN

14

3D NMOSFET Device3D NMOSFET vs. PTM L54Ion Profile

3D NMOSFET vs. PTM L54

Vs=Vb= 0 VVgs= 1.2V

15

3D NMOSFET Device3D NMOSFET vs. PTM L54Ion Profile

3D NMOSFET vs. PTM L54

Vs=Vb= 0 VVgs= 1.2V

Threshold Voltage•ST 90nm: Vt=0.34 V•PTM model: Vt=0.39V (ASU, 08)•TCAD Model: Vt=0.36

(ASU, Predictive Technology Model , 2008) (STMicroelectronics. HCMOS9_GP Design Rules ,2002)

16

Ion Profile

4

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions17

3D NMOSFET vs. PTM L54Ion profileIon profile – Alpha Particle

Ion Profile

• The Environment (LERAY, 2004)

• For sea level

• Alpha particle

• About 1 MeV/(mg/cm2)

• Avionics

• 10-20 MeV/(mg/cm2)

• Space Applications

• +20 MeV/(mg/cm2)

(LERAY, International Conference on Integrated Circuit Design and Technology, 2004)

18

Ion ProfileIon Profile – Alpha ParticleIon Profile - Copper

Ion Profile – Alpha Particle

• Alpha Particle (He nuclei)

(ZIEGLER, SRIM 2008, 2008) 19

Ion ProfileIon Profile – Alpha ParticleIon Profile - Copper

Ion Profile – Alpha Particle

• Alpha Particle (He nuclei)

(ZIEGLER, SRIM 2008, 2008)

Radial Distribution: 50nm

20

Ion Profile – Alpha ParticleIon Profile – CopperIon Profile - Krypton

Ion Profile - Copper

• Copper (Cu)

(ZIEGLER, SRIM 2008, 2008) 21

Ion Profile – Alpha ParticleIon Profile – CopperIon Profile - Krypton

Ion Profile - Copper

• Copper (Cu)



22

Ion Profile – Alpha ParticleIon Profile – KryptonIon Profile

Ion Profile - Krypton

(ZIEGLER, SRIM 2008, 2008) 23

Ion Profile – Alpha ParticleIon Profile – KryptonIon Profile

Ion Profile - Krypton

• Krypton (Kr)


24

Ion Profile – Alpha ParticleIon ProfilePhysical Models

Ion Profile

• Impact details

–Hit the transistor drain center

– Impact angle: 90 degrees

–Pass through the device

Element /

Energy

LET(dE/dX)

MeV/(mg/cm2)

Radial (r)

m

Alpha – 1

MeV

1.31 0.05

Cu, 395 MeV 26.5 0.5

Kr, 270 MeV 40.5 0.65

Table 4 - Ion profile3D NMOSFET under irradiation

Ion track


25

Ion Profile – Alpha ParticlePhysical ModelsTransistor Sizing

Physical Models

• Models used during simulations•Shockley-Read-Hall Model - SRH •Auger Recombination Model - AUGER •Carrier-Carrier Scattering Mobility Model - CCSMOB •Bang-Gap Narrowing Model - BGN

SRH AUGER

(SCHOCKLEY, 1952) (LANDSBERG, 1964)

(LUNDSTROM, 2000)

(SLOTBOOM, 1977)

26

Transistor Sizing

5

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions27

Physical ModelsTransistor Sizing TechniqueTransistor Sizing Electric Evaluation

Transistor Sizing Technique

TRIPV

PULSEPNCOUPLETOTALcrit TIndVCCQ0

,)2(

)1)(()(

)()(

pJSWPDPJAPNJSWNDNJAN

pGDLPGDOPnGDLNGDONPGOPNGONTOTAL

wCACwCAC

wCCwCCACACC

where VTRIP is the standard voltage of technology, CTOTAL is the total front-end capacitor, CCOUPLE is the coupling capacitance, CGON and CGOP

are gate capacitances of N/P transistors, AN and AP are gate area of N/P transistors respectively, CGDON and CGDP are bias-independent part of the overlap capacitance, and CGDLN and CGDLP are bias-dependent overlap capacitance. Source and drain junction capacitance are CJAN

and CJAP, and sidewall capacitances are CJSWN and CJSWP respectively

The idea behind the transistor sizing technique is based on the increase of the Critical Charge of the node. The critical charge is given by the following equation..

* Basically the transistor width is increased making the total capacitance of the node increase and so the critical charge.

(ZHOU, IEEE CAD Design of Integrated Circuits Systems, 2006)28

The technique was evaluated by (ZHOU & LAZZARI) at electric level using the double exponential equation to model the SEE.

Transistor Sizing TechniqueTransistor Sizing Electric Evaluation3D NMOSFET Device

Transistor Sizing Electric Evaluation

Iin (t) I0 e

t

e

t

(MESSENGER, NSREC, 1982)

The current modeled by the equation is injected in a node of the circuit and results are collected.

The problem :With the increase of the transistor width, the geometry of the device is increased and the effect of the ion particle for this new geometry is not evaluated when using this technique.

A device level simulations is required!

29

Transistor Sizing Electric EvaluationDevice Under TestResults: Alpha Particle

Device Under Test

(a) NOT gate – Input 0(b) NAND gate – Input 01(c) NAND gate – Input 10(d) NOR gate – Input 00

(a) (b)

(c) (d)

30

Transistor Sizing Electric EvaluationDevice Under TestResults: Alpha Particle

Device Under Test

Sizes

NMOS

transistors

Wn(nm)

PMOS

transistors

Wp(nm)

W0 220 880

W1 510 880

W2 1.020 880

SizesNMOS

Wn(nm)

PMOS

Wp(nm)

W0 220 390

W1 510 880

W2 1.020 1.760

W2_3 2.040 3.508

W3 3.060 5.263

W4 4.080 7.017

W5 5.100 8.772

Table 1 – Asymmetric Sizing Table 2 – Symmetric Sizing

Name Capacitance Name Capacitance

C1 10f F C6 500f F

C2 20f F C7 1p F

C3 40f F C8 10p F

C4 80f F C9 20p F

C5 160f F

Table 3 - Output Capacitances

31

Device Under TestResults: Alpha ParticleConclusion: Alpha Particle

Results: Alpha Particle

Both sizing methodologies increase the collected charge.

The SEE pulse peak decreases which means that the pulse is getting worst.

The symmetric sizing simulations will be extended due a possible recovery.

1.101.03

0.830.971.03

1.02

Asymmetric Symmetric

Co

llect

ed

Ch

arge

(C

)

SEE

Pu

lse

Pe

ak (

V)

W0 W1 W2

9.9227E-15

1.6323E-14 2.0048E-14

1.590E-15

1.6323E-14

2.246E-14

W0 W1 W2

1,31 MeV/(mg/cm2) Asymmetric

1,31 MeV/(mg/cm2) Symmetric

32



Collected charge of symmetric sizing continues increasing…

But the SEE pulse peak shows the recovery of the transistor, indicating that the technique is working for symmetric sizing.

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

W0 W1 W2 W2_3 W3 W4 W5

SEE

Pu

lse

Pe

ak(V

)

0.000E+00

1.000E-14

2.000E-14

3.000E-14

4.000E-14

5.000E-14

6.000E-14

W0 W1 W2 W2_3 W3 W4 W5

Co

llect

ed

Ch

arge

(C

)

33



SEE

Pu

lse

Increasing the output capacitance…

34

Results: Alpha ParticleConclusion: Alpha ParticleResults: Heavy Ion (Cu & Kr)

Conclusion: Alpha Particle

• Asymmetric sizing: the SEE pulse has not shown signs of recovering for the transistors that were increased.

• Symmetric sizing: the SEE pulse was reduced with the increase of the transistor width.

Notice that for both methodologies the transistor width was increased, but just symmetric sizing shows recovery.

This indicates that the recovery of the symmetric size happens more due to the increase of the capacitance and drive current

of the pull-up transistors.35

Conclusion: Alpha ParticlesResults: Heavy Ion (Cu & Kr)Conclusion: Heavy Ion (Cu & Kr)

Results: Heavy Ion (Cu & Kr)

0.102

-0.282

-0.628-0.06

-0.28-0.49

Asymmetric Symmetric -0.101

-0.279

-0.610

-0.18-0.28 -0.50


W0 W1 W2

Cu: 26.5 MeV/(mg/cm2) Kr: 40.5 MeV/(mg/cm2)

2.177E-132.953E-13 3.176E-13

1.246E-13

3.065E-13

6.340E-13

W0 W1 W2


3.457E-135.432E-13

6.317E-13

2.073E-13

5.484E-13

1.259E-1240,5 MeV/(mg/cm2) Asymmetric

40,5 MeV/(mg/cm2) Symmetric

SEE

Pu

lse

Pe

ak (

V)

Co

llect

ed

Ch

arge

(C

)

Heavy ion simulations presents the same behavior for Cu and Kr.The SEE pulse peak is reduced (getting worst) and the collected charge increases in both methodologies.

W0 W1 W2

36



Cu: 26.5 MeV/(mg/cm2) Kr: 40.5 MeV/(mg/cm2)

4.831E-102.787E-09

1.134E-08

1.858E-092.787E-09 5.357E-09

Asymmetric

Symmetric

5.80E-103.03E-09

1.28E-08

1.86E-093.03E-09 5.36E-09

W0 W1 W2


Pu

lse

Wid

th (

s)

W0 W1 W2

The SET pulse width also present similar behavior for both ions.

The SET pulse width increases for both methodologies having the asymmetric sizing the worst results.

37



-0.80

-0.60

-0.40

-0.20

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-2.3000E-22 5.0000E-09 1.0000E-08 1.5000E-08 2.0000E-08

Vo

ltag

e (

V)

Time (S)

C1-Drain Voltage

C2-Drain Voltage

C3-Drain Voltage

C4-Drain Voltage

C6-Drain Voltage

C7-Drain Voltage

C8-Drain Voltage

C9-Drain Voltage

Using a fixed

Wn=220nm

Pulse Width

Wp=0.390nm 5,066e-9

Wp=0.880nm 1,095e-9

Table 5 – Pull-up transistor sized

Increase the pull-up transistors will reduce the pulse if the transient happens in the pull-down devices.

SEE

Pu

lse

38

• Asymmetric sizing: for both ions the methodology was not able to restore the pulse.

• Symmetric sizing: the technique was not able to restore the pulse.

Results: Heavy Ion (Cu & Kr)Conclusion: Heavy Ion (Cu & Kr)Related Work

Conclusion: Heavy Ion (Cu & Kr)

Due the high amount of charge injected by heavy ions, the increase of the capacitance of the node do not help much the recovery of the transistor.

Notice that for both technologies there is no sign of possible recovery. Even when simulations are extended to evaluate larger widths, the pulse continue

to get worst.

39

• Shin, (SHIN, 1990) shows that the increase of the junction area imposes an increase of the funneling of the electric field

• Baumann, (BAUMANN, 2005) reports that large junctions areas are efficient in collecting radiation induced charge.

Conclusion: Heavy Ion (Cu & Kr)Related WorkConclusions

Related Work

(SHIN, H. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999)(BAUMANN, R.C. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005)

40

• The efficiency of transistor sizing technique had show to be dependent of the ion that is hitting the device.– For alpha particles the technique had shown to be

able to allow the recovery of the device due the small amount of charge transferred by the ion to the device.

– For heavy ions the technique had not shown to be efficient due the large amount of charge generated by the ion.

• The asymmetric sizing had show the worst results when compared with symmetric sizing.

Related WorkConclusionsTransistor Folding

Conclusions

41

Transistor Folding

6

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions42

ConclusionsTransistor FoldingTransistor Folding – Alpha Particle

Transistor Folding

Transistor folding…

(HER, 1993)

43

ConclusionsTransistor FoldingTransistor Folding – Alpha Particle

Transistor Folding

Sizes PMOSWp(um)

NMOSWn(um)

SizesFolding

PMOSWp(um)

NMOSWn(um)

W0 3.52 2.040 W0_S 2x1.760 2x1.020

W1 5.28 3.06 W1_S 3x1.760 3x1.020

W2 7.04 4.08 W2_S 4x1.760 4x1.020

W3 8.8 5.1 W3_S 5x1.760 5x1.020

W4 10.56 6.12 W4_S 6x1.760 6x1.020

Sizes PMOSWp(um)

NMOSWn(um)

Wn1 1x8.8 1x5.1

Wn2 2x4.4 2x2.55

Wn3 3x2.933 3x1.7

Wn4 4x2.2 4x1.275

NOT: without Folding NOT: with Folding

Folding rate

44

ConclusionsTransistor Folding – Alpha ParticleTransistor Folding – Copper

Transistor Folding – Alpha Particle

0.900

0.950

1.000

1.050

1.100

1.150

1.200

1.250

W0 W1 W2 W3 W4

Folding

No Folding

0.00E+00

1.00E-14

2.00E-14

3.00E-14

4.00E-14

5.00E-14

6.00E-14

w0 w1 w2 w3 w4

No Folding

Folding

Co

llect

ed C

har

ge (

C)

SEE

Pu

lse

Pe

ak (

V) Both techniques allows a better recovery..

Using folding the collected charge is controlled during the increase…

45

ConclusionsTransistor Folding – Alpha ParticleTransistor Folding – Copper

Transistor Folding – Alpha Particle

(SHIN, H. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999)(BAUMANN, R.C. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005)

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

1.09

1.10

Wn1 Wn2 Wn3 Wn4

SEE

Pu

lse

Pe

ak (

V)

Number of partitions of the transistor…..

Recovery is seen…This is the first partition.1 drain area is shared by 2 transistors.

46

ConclusionsTransistor Folding – CopperTransistor Folding – Krypton

Transistor Folding - Copper

-0.80

-0.60

-0.40

-0.20

0.00

Folding No Folding

0

1E-09

2E-09

3E-09

4E-09

5E-09

6E-09

Folding

No Folding

0.00E+00

1.00E-11

2.00E-11

3.00E-11

4.00E-11

5.00E-11

Folding No Folding

W0 W1 W2 W3 W4

W0 W1 W2 W3 W4

W0 W1 W2 W3 W4

Co

llect

ed C

har

ge (

C)

SEE

Pu

lse

Pe

ak (

V)

Pu

lse

Wid

th (

s)

The drop of the bias is reduced when folding devices are used..

Folding allows an small increase of the collected charge..

The pulse width of the SET is drastically reduced..

47

ConclusionsTransistor Folding – CopperTransistor Folding – Krypton

Transistor Folding - Copper

0.00E+00

1.00E-11

2.00E-11

3.00E-11

4.00E-11

5.00E-11

Wn1 Wn2 Wn3 Wn4

-0.80

-0.70

-0.60

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

Wn1 Wn2 Wn3 Wn4

0.00E+00

1.00E-09

2.00E-09

3.00E-09

4.00E-09

5.00E-09

6.00E-09

7.00E-09

8.00E-09

9.00E-09

Wn1 Wn2 Wn3 Wn4

Co

llect

ed

Ch

arge

(C

)

SEE

Pu

lse

Pe

ak (

V)

Pu

lse

Wid

th (

s)

Increasing the number of partitions allows the reduce of the pulse

Both pulse width and amplitude are reduced….

48

ConclusionsTransistor Folding – KryptonTransistor Folding – Conclusions

Transistor Folding - Krypton

-0.80

-0.70

-0.60

-0.50

-0.40

-0.30

-0.20

-0.10

0.00

Folding No Folding

0

2E-09

4E-09

6E-09

8E-09

1E-08

Folding No Folding

0.00E+00

1.00E-11

2.00E-11

3.00E-11

4.00E-11

5.00E-11

6.00E-11Folding

No Folding

W0 W1 W2 W3 W4

W0 W1 W2 W3 W4

W0 W1 W2 W3 W4

Co

llect

ed C

har

ge (

C)

SEE

Pu

lse

Pe

ak (

V)

Pu

lse

Wid

th (

s)

The drop of the bias is reduced when folding devices are used..

The pulse width of the SET is drastically reduced..

Folding allows an small increase of the collected charge..

49

ConclusionsTransistor Folding – KryptonTransistor Folding – Conclusions

Transistor Folding - Krypton

0

1E-11

2E-11

3E-11

4E-11

5E-11

6E-11

Wn1 Wn2 Wn3 Wn4

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

Wn1 Wn2 Wn3 Wn4

0

2E-09

4E-09

6E-09

8E-09

1E-08

1.2E-08

Wn1 Wn2 Wn3 Wn4

Co

llect

ed

Ch

arge

(C

)

SEE

Pu

lse

Pe

ak (

V)

Pu

lse

Wid

th (

s)

Increasing the number of partitions allows the reduce of the pulse

Both pulse width and amplitude are reduced….

50

• For alpha particles

– The partition of the transistor had allow the recovery of the ionization as transistor sizing.

• For heavy ions profile like Co and Kr ions the transistor folding had allow a better recovery when compared with transistor sizing.

– The SET pulse width is drastically reduced when the device is folded

• The higher the number of partitions the larger is the reduce over the effects of the ionization.

ConclusionsTransistor Folding – ConclusionsCase Study – 6T SRAM Cell

Transistor Folding - Conclusions

51


7

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions 52

ConclusionsCase Study – 6T SRAM CellConclusions


[nm] M1 M2 M3 M4 M5 M6 Mload

SRAMStandard

175 125 175 125 125 125 12.5um

SRAM+Sizing

350 250 350 250 250 250 25um

SRAM+Folding

2*175 2*125 2*175 2*125 2*125 2*125 25um

(RA

BA

EY, 2

00

3).

53



6T SRAM Cell – Write operation

Cell rate for write (PR)M6*PR = M3

PR=1.4

54



6T SRAM Cell – Write operation

55



6T SRAM Cell – Read operation

Cell rate for read (CR)M5*CR = M1

PR=1.4

The 1.4 cell rate (PR & CR) was recommended by(AGARWAL, 2006)

56



6T SRAM Cell – Read operation

57



Ion Energy LET

(MeV/mg/cm2)

Radial

Distribution

He 1 MeV 1.31 50nm

X X0 5 50nm

Y Y0 10 50nm

Z Z0 10 110nm

Cu 395 MeV 26.5 0.5um

Kr 270 MeV 40.5 0.65um

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

He X Y Z Cu Kr

Vo

ltag

e (

V)

STD-SET Pulse Peak (V)

Folding-SET Pulse Peak (V)

Sizing-SET Pulse Peak (V)

SEU is mitigated…

58

Conclusions

8

Introduction

Single Event Effect

3D NMOSFET Device

Ion Profile

Transistor Sizing

Transistor Folding


Conclusions59

• The efficiency of transistor sizing technique had show to be dependent of the ion that is hitting the device.

– For alpha particles the technique had shown to be able to allow the recovery of the device.

– For heavy ions the technique had not shown to be efficient due the large amount of charge generated by the ion.

• For transistor folding both heavy ions and sea level profiles had shown a reduction in their effect.

Case Study – 6T SRAM CellConclusionsPublications

Conclusions

60

• Technology Scale

–Doping profile• +doping -> Increase electric field strength

– More charge collected due Drift Current

• -doping -> Decrease electric field strength– Less charge collected due Drift Current

–Device geometry

• Drain area

– Reducing the size

» Allows less charge to be collected

» More devices in the impact region

• Multiple collected charge


Conclusions

61

• Future Works– Investigate others layout topologies like:

• Enclosed Layout Transistors

– Silicon on Insulator (SOI)


Conclusions

62

• PublishedASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . Measuring the Effectiveness of Symmetric and Asymmetric

Transistor Sizing for Single Event Transient Mitigation in CMOS 90nm Technologies. In: 10th IEEE Latin-American TestWorkshop, 2009, Buzios. 10th IEEE Latin-American TestWorkshop, 2009.

ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . Avaliando a eficiência do redimensionamento simétrico e assimétrico de transistores para a redução de Single Event Effects em uma tecnologia 90nm CMOS. In: IBERCHIP XVWorkshoop, 2009, Buenos Aires. IBERCHIP XV Workshoop, 2009.

LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits. In: European Test Symposium, 2008, Verbania. European Test Symposium 2008, 2008.

LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . Asymmetric and Symmetric Transistor Sizing to Reduce SET Sensitivity in Integrated Circuits. In: 23th South Symposium on Microelectronics, 2008, Bento Gonçalves. 23th South Symposium

ASSIS, T. R. ; WIRTH, G. ; KASTENSMIDT, F.L.G ; REIS, R.A. . Modeling of a NMOS 90 nm device to Multiple Event Transient Simulation. In: 23th South Symposium on Microelectronics, 2008, Bento Gonçalves. 23th South Symposium on Microelectronics, 2008.

ASSIS, T. R. ; WIRTH, G. ; KASTENSMIDT, F.L.G ; REIS, R.A. . DESIGN AND EVALUATION OF A NMOS 90 nm 3D DEVICE. In: 8th Microelectronic Students Forum 2008 - SBCCI 2008, 2008, Gramado. 8th Microelectronic Students Forum 2008, 2008.

LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. ; ANGHEL, L. . An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits. In: IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale Integration, 2008,, 2008, Rhodes. IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale Integration., 2008. v. 1.

ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; REIS, R.A. . ANALYSIS OF SINGLE EVENT EFFECTS FOR DIFFERENT ANGLES AND IMPACT REGIONS AT A NMOS 90nm 3D DEVICE. In: Second International Workshop on Dependable Circuit Design, 2008, Playa del Carmen. Second International Workshop on Dependable Circuit Design - 2008, 2008.

LAZZARI, C. ; ASSIS, T. R. ; KASTENSMIDT, F.L.G ; WIRTH, G. ; ANGHEL, L. ; REIS, R.A. . Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits. In: First International Workshop on Dependable Circuit Design, 2007, Buenos Aires. First International Workshop on Dependable Circuit Design, 2007. v. 1.

First author: 5 Second author: 4

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• Submitted

– European Symposium on Reliability of Electron Devices, Failure Physics and Analysis 2009

• Influence of Carriers Spatial Distribution Generated During Ionization to Soft Errors Simulation

• To Submit

– Transistor folding results

• Others activities– Chairman of IEEE Circuits & System Society Student Branch

• 2008/200964

Thanks…

65

Analysis of Transistor Sizing and Folding Effectiveness to

Mitigate Soft ErrorsThiago Rocha de Assis

Advisor: Ricardo Augusto da Luz ReisCo-Advisor: Fernanda Gusmão de Lima Kastensmidt

maste thesis ap thiago assis

Technology

d nmosfet device ion

ion profile3d nmosfet

ptm l54ion profile vs

single event latchup

nm ziegler

transistor sizing transistor

single event gate rupture

nm nonesubstrate