main documentation of batch 13

8/2/2019 Main Documentation of Batch 13

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CHAPTER 1

Introduction to Embedded Systems

1.1Introduction

Embedded systems are electronic devices that incorporate microprocessor with in their

implementation. The main purpose of the microprocessor is to simplify the system design andprovide flexibility. This system may not have a disk driver and so the software is often stored in

a ROM chip. Embedded systems often have several things to do at once. They must respond to

external events (eg: someone pushes an elevator button).

An Embedded system is any computer system hidden inside a product other than a

computer. Embedded systems are found in wide range of applications like expensive industrial

control applications. As the technology brought down the cost of dedicated processors. They

began to appear in moderately expansive applications such as automobiles, communications and

office equipment, televisions. Today‘s embedded system is so inexpensive that they are used in

almost every electronic product in our life.

Many embedded systems have to run 24 hours a day you can‘t just ―reboot‖ when

something goes wrong. For this reason a good coding practices and thorough testing take on a

new level of realm of embedded processors.

Performance goals will force us to learn and apply new techniques such as multitasking

and scheduling. The need to communicate directly with sensors actuators, keypads, displays etc

will require programmers to have a better understanding of how alternative methods for

performing input and output provide opportunities to trade speed, complexity and cost.



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How powerful are embedded processors

The embedded system found in most consumer products employs a single chip

controller. That includes the microprocessor, a limited amount of memory and simple input

output devices. By far the vast majority of the embedded systems in production today are based

on the 4bit, 8bit, or 16bit processors. Although 32bit processors account for relatively small

percentage of the current market, their use in embedded systems is growing at the fastest rate.

What programming languages are used

Although it is occasionally necessary to code some small parts of an embedded application

program in assembly language, rest of the code in even the simplest application is written in a

high level language. Traditionally the choice of the language has been ‗C‘. Programs written in

‗C‘ are very portable from one compiler and/or target processor to another. C compilers are

available for a number of different target processors, and they generate very efficient code.

Despite the popularity of C++ and Java for desktop application programming, they are

rarely used in embedded systems because of the large run-time overhead required to support

some of their features. For example, even a relatively simple C++ program will produce about

twice as much code as the same program written in C and the situation is Much worse for large

program that makes extensive use of the run-time library.

Despite the popularity of C++ and Java for desktop application programming, they are

rarely used in embedded systems because of the large run-time overhead required to support

some of their features. For example, even a relatively simple C++ program will produce about

twice as much code as the same program written in c and the situation is much worse for large

program that makes extensive use of the run-time library.

How is building an embedded application unique?

You should already be familiar with the tools and soft ware components used to build a

desktop application program and load it into memory for execution. Desktop Application

program is as shown in fig. 1.1.



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Desktop application programs:

Fig 1.1 desktop application programs

Embedded Application Program

Fig.1.2 Embedded Application Program

Image

File

Executab

le image

file

Compiler

Assembler

Linker

loader

Read writeMemory(RAM)

Read only

Memory(ROM)

Rom―burner‖

file

Program

initialization

Re entrant library

Run time kernel

Ob ect Files

Object files

Exec

Image

file

Compiler

Linker

Loader

Boot rocess

Assembler

RAM

Executable image file

Operating system image

Run time library



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A compiler and/or an assembler are used to build one or more object files that are linked to

gather with a run-time library to form an executable image that‘s stored as a file on the disk.

When we want run a desktop application program, its executable image is loaded from a disk

into memory by a part of the operating system known as the ―Loader‖.

The operating system itself is already in memory, put there during the boot process.

The desktop system is intended to run a number of different application programs.

Thus, read-write main memory is used so that an entirely different application program canbe quickly and easily loaded into memory, replacing the previous application whenever

necessary.

Unlike general desktop systems embedded systems are designed to serve a single purpose.

Once the embedded software is in memory, there is usually no reason to change it. This allows a

less expansive read only memory to be used for permanent storage of the program. Since there is

no need to store the program on disk, a significant amount of software can be eliminated that

would otherwise be necessary to support a file system.

Both the embedded application‘s software and a real-time kernel are stored in the same

read only memory as a single program image, with no need for a file system.

In general the same kind of software development tools are used to build both embedded

and desktop applications. Although tools suites designed especially for embedded applications

developments are commercially available, in many cases it‘s possible to use same compiler,

assembler and linker that you use for desktop applications. There are two important differences,

however. First, the run time library that comes with compilers for desktop applications is usually

not intended for multitasking applications and must be replaced by one that is reentrant. Second,

additional software called a locator is required to convert the linkers out put to a form suitable

for storing in read only memory.



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1.2 Embedded Software Development Tools

Application programmers typically do their work on the same kind of computer on which

the application will run. If programmers edit the program, compiles its links it, tries it out anddebugs it, all on the same machine

The tactic has to change for embedded systems. In the first place, most embedded systems

have specialized hardware to attach to special sensors or to drive special controls, and the only

way to try out the software is on the specialized hardware.

In the second place, embedded systems often use microprocessors that have never been

used as the basis of workstations. Obviously, programs do not get magically compiled into the

instruction set for whatever microprocessor you happen to have chosen for your system, and

programs do not magically jump into the memory of your embedded system for execution

Host and Target Machines

Most programming work for embedded systems is done on a host, a computer system on

which all the programming tools run. Only after the program has been written, compiled,

assembled and linked is it moved to target, the system that is shipped to customers. Some people

use the word workstation instead of host; the word target is almost universal (See in Figure given

below).

Cross compilers

Most desktop system used as host comes with compilers, assemblers, and linkers and so on

for the building to the programs that will run on the host. These tools are called as the native

tools‖. The need of a compiler that needs run on the host system but produce the binary

instructions that will be understand by the target microprocessor. Such a program is called a

cross compiler.

The fact that program works on your host machine and compiles cleanly with your cross

compiler is no assurance that will work on your target system. The same problem that haunts

every other effort to port C programs from machine another apply. The variables declared has int



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may be one size on the host and a different size on the target. Structures may be packed

differently on the two machines.

Because of this, we should expect a different collection of warnings from cross compiler.

For eg: if the code cast a void pointer to an int, the native compiler may know that the twoentities are the same size and not issue a warning.

Fig. 1.3 Cross Compilers

EC

Cross

.O

Assembl

Cross

.O

Link

HOST

Target

Locat



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Cross Assemblers

Another tool that will need if we must write any of the program in assembly language is a

cross assembler. As we might imagine from the name, a cross assembler is an assembler that run

on host but produces binary instructions appropriated for the target. The input to the cross

assembler must be assembly language appropriated for the target (since that is the only assembly

language that can be translated into binary instructions for the target).

Linker/Locators for Embedded Software

The first difference between a native linker and locator is the nature of the output files that

they create. The native linker creates a file on the disk drive of the host system that is read by apart of the O.S called the loader. The locator creates file that will be used by some program that

copies the output to the target system. Later, the output from the locator will have to run it‘s

own.

In an embedded system, there is no separate O.S. Linkers for embedded system is often

called as locators.

1.3 Embedded Design Methodology

The fast growing complexity and short time to market of today's real-time embedded

systems necessitates new design methods and tools to face the problem of specification, design,

analysis, scheduling, simulation, integration and validation of complex systems. In the project, a

system level method for embedded real-time systems design is developed exploiting SystemC

strength for system level dan co-design modeling. In order to support the methodology, some

extensionto SystemC are proposed starting form RTOS modeling and framework for scheduling

simulation.

http://www.systemc.org/

http://www.systemc.org/



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1.4 Schematic Diagram:

Fig 1.4 schematic diagram



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CHAPTER 2

EMBEDDED MICROCONTROLLER AND HARDWARE

2.1 Introduction

2.1.1 MICROCONTROLLER AT89S52:

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8k

bytes of in-system programmable Flash memory. The device is manufactured using Atmel‘s

high-density nonvolatile memory technology and is compatible with the industry-standard 80C51

instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed

in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-

bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a

powerful microcontroller which provides a highly-flexible and cost-effective solution to many

embedded control applications. The AT89S52 provides the following standard features: 8K bytes

of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit

timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip

oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for

operation down to zero frequency and supports two software selectable power saving modes. The

Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt

system to continue functioning. The Power-down mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next interrupt or hardware reset.

2.2 FEATURES:

• COMPATIBLE WITH MCS-51®

PRODUCTS

• 8K BYTES OF IN-SYSTEM PROGRAMMABLE (ISP) FLASH MEMORY

– ENDURANCE: 1000 WRITE/ERASE CYCLES

• 4.0V TO 5.5V OPERATING RANGE



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• FULLY STATIC OPERATION: 0 HZ TO 33 MHZ

• THREE-LEVEL PROGRAM MEMORY LOCK

• 256 X 8-BIT INTERNAL RAM

• 32 PROGRAMMABLE I/O LINES

• THREE 16-BIT TIMER/COUNTERS

• EIGHT INTERRUPT SOURCES

• FULL DUPLEX UART SERIAL CHANNEL

• LOW-POWER IDLE AND POWER-DOWN MODES

• INTERRUPT RECOVERY FROM POWER-DOWN MODE

• WATCHDOG TIMER

• DUAL DATA POINTER

• POWER -OFF FLAG

PIN CONFIGURATION:

Figure 2.1 Pin Description of AT89S52 Microcontroller



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2.3 Pin Diagram & Port Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs.

When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be

configured to be the multiplexed low-order address/data bus during accesses to external program and data

memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash

programming and outputs the code bytes during program verification. External pull-ups are required

during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source

four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can

be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL)

because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2

external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown

in the following table. Port 1 also receives the low-order address bytes during Flash programming and

verification



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Table1:port1 pin declaration

Port 2:

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled

low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external data memory

that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-

ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses

(MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also

receives the high-order address bits and some control signals during Flash programming and

verification.

Port 3:

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source

four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can

be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL)

because of the pullups. Port 3 also serves the functions of various special features of the AT89S52, as

shown in the following table. Port 3 also receives some control signals for Flash pro-gramming and

verification.



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Table2:pin declaration of port 3

RST:

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO

bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit

DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG:

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during Flash

programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator

frequency and may be used for external timing or clocking purposes. Note, however, that one

ALE pulse is skipped during each access to external data memory. If desired, ALE operation can

be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a

MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable



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bit has no effect if the microcontroller is in external execution mode. weakly pulled high. Setting

the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN:

Program Store Enable (PSEN) is the read strobe to external program memory. When the

AT89S52 is executing code from external pro-gram memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external data

memory. Program Store Enable (PSEN) is the read strobe to external program memory. When

the AT89S52 is executing code from external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external data

memory. Note, however, that if lock bit 1 is programmed, EA w internally latched on reset. EA

should be strapped to VCC for internal programming. This pin also receives the 12-volt

programming enable age (VPP) during Flash programming.

XTAL1:

Input to the inverting oscillator amplifier and input internal clock operating circuit.

XTAL2:

Output from the inverting oscillator amplifier.

Special Function Registers:

A map of the on-chip memory area called the Special Function Register (SFR) space is. Note that

not all of the addresses are occupied, and unoccupied addresses may not be implemented on the

chip. Read accesses to these addresses will in general return random data, and write accesses will

have an indeterminate effect. User software should not write 1s to these unlisted locations, sincethey may be used in future products to invoke new features. In that case, the reset or inactive

values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained

in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register

pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or



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16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE

register. Two priorities can be set for each of the six interrupt sources in the IP register.

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer

Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS =

0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the

DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power off Flag:

The Power off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to ―1‖during power up. It can be set and rest under software control and is not affected by reset.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes

each of external Program and Data Memory can be addressed.

Program Memory:

If the EA pin is connected to GND, all program fetches are directed to external memory. On the

AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are

directed to internal memory and fetches to addresses 2000H through FFFFH are to external

memory.

Data Memory:

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128 bytes have the

same addresses as the SFR space but are physically separate from SFR space. When an

instruction accesses an internal location above address 7FH, the address mode used in the

instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space.



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Instructions which use direct addressing access of the SFR space. For example, the following

direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H,

#data:

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the

following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at

address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data:

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data

RAM are available as stack space.

Watchdog Timer:

(One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations

where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and

the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset.

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while

the oscillator is running. The WDT timeout period is dependent on the external clock frequency.

There is no way to disable the WDT except through reset (either hardware reset or WDT over-

flow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT:

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH

and 0E1H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches

8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every

machine cycle while the oscillator is running. This means the user must reset the WDT at least

every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST.

WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT



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overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is

96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in

those sections of code that will periodically be executed within the time required to prevent a

WDT reset. WDT During Power-down and Idle In Power-down mode the oscillator stops, which

means the WDT also stops. While in Power-down mode, the user does not need to service the

WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-

activated external interrupt which is enabled prior to entering Power-down mode. When Power-

down is exited with hardware reset, servicing the WDT should occur as it normally does

whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different.

The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought

high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt

pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the

WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To

ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to

reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the

WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if

enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To

prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set

up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With

WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon

exit from IDLE.

UART:

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52.

For further information on the UART operation, refer to the ATMEL Web site

(http://www.atmel.com). From the home page, select ‗Products‘, then ‗8051-Architecture Flash

Microcontroller‘, then ‗Product Overview‘.

Timer 0 and 1:



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Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the

AT89C51 and AT89C52. For further information on the timers‘ operation, refer to the ATMEL

Web site (http://www.atmel.com). From the home page, select ‗Products‘, then ‗8051-

Architecture Flash Microcontroller‘, then ‗Product Overview‘.

Timer 2:

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type

of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three

operating modes: capture, auto-reload (up or down counting), and baud rate generator. The

modes are selected by bits in T2CON Timer 2 consists of two 8-bit registers, TH2 and TL2. In

the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle

consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

Table 3: Timer 2 Operating Modes:

In the Counter function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T2. In this function, the external input is sampled during S5P2

of every machine cycle. When the samples show a high in one cycle and a low in the next cycle,

the count is incremented. The new count value appears in the register during S3P1 of the cycle

following the one in which the transition was detected. Since two machine cycles (24 oscillator

periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the

oscillator frequency. To ensure that a given level is sampled at least once before it changes, the

level should be held for at least one full machine cycle.



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CHAPTER 3

HARDWARE DESCRIPTION

3.1 REGULATED POWER SUPPLY

A variable regulated power supply, also called a variable bench power supply, is one

where you can continuously adjust the output voltage to your requirements. Varying the output

of the power supply is the recommended way to test a project after having double checked parts

placement against circuit drawings and the parts placement guide. This type of regulation is ideal

for having a simple variable bench power supply. Actually this is quite important because one of

the first projects a hobbyist should undertake is the construction of a variable regulated power

supply. While a dedicated supply is quite handy e.g. 5V or 12V, it's much handier to have a

variable supply on hand, especially for testing. Most digital logic circuits and processors need a 5

volt power supply. To use these parts we need to build a regulated 5 volt source. Usually you

start with an unregulated power supply ranging from 9 volts to 24 volts DC (A 12 volt power

supply is included with the Beginner Kit and the Microcontroller Beginner Kit.)

To make a 5 volt power supply, we use a LM7805 voltage regulator IC .The LM7805 is

simple to use. You simply connect the positive lead of your unregulated DC power supply

(anything from 9VDC to 24VDC) to the Input pin, connect the negative lead to the Common pin

and then when you turn on the power, you get a 5 volt supply from the Output pin.

Fig 3.1 regulated power supply top view



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CIRCUIT DIAGRAM

Fig3.1.3 circuit diagram of regulated power supply

BASIC POWER SUPPLY CIRCUIT

Above is the circuit of a basic unregulated dc power supply. A bridge rectifier D1 to D4

rectifies the ac from the transformer secondary, which may also be a block rectifier such as WO4

or even four individual diodes such as 1N4004 types. (See later re rectifier ratings).

The principal advantage of a bridge rectifier is you do not need a centre tap on the

secondary of the transformer. A further but significant advantage is that the ripple frequency at

the output is twice the line frequency (i.e. 50 Hz or 60 Hz) and makes filtering somewhat easier.

As a design example consider we wanted a small unregulated bench supply for our

projects. Here we will go for a voltage of about 12 - 13V at a maximum output current (I L) of

500ma (0.5A). Maximum ripple will be 2.5% and load regulation is 5%.

Now the RMS secondary voltage (primary is whatever is consistent with your area) for our

power transformer T1 must be our desired output Vo PLUS the voltage drops across D2 and D4 (

2 * 0.7V) divided by 1.414.



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This means that Vsec = [13V + 1.4V] / 1.414 which equals about 10.2V. Depending on the

VA rating of your transformer, the secondary voltage will vary considerably in accordance with

the applied load.

If we accept the 2.5% ripple as adequate for our purposes then at 13V this becomes 13 *0.025 = 0.325 Vrms. The peak to peak value is 2.828 times this value. Vrip = 0.325V X 2.828 =

0.92 V and this value is required to calculate the value of C1.

Also required for this calculation is the time interval for charging pulses. If you are on a

60Hz system it is 1/ (2 * 60 ) = 0.008333 which is 8.33 milliseconds. For a 50Hz system it is

0.01 sec or 10 milliseconds.

Remember the tolerance of the type of capacitor used here is very loose. The important

thing to be aware of is the voltage rating should be at least 13V X 1.414 or 18.33. Here you

would use at least the standard 25V or higher (absolutely not 16V).With our rectifier diodes or

bridge they should have a PIV rating of 2.828 times the Vsec or at least 29V. Don't search for

this rating because it doesn't exist. Use the next highest standard or even higher. The current

rating should be at least twice the load current maximum i.e. 2 X 0.5A or 1A. A good type to use

would be 1N4004, 1N4006 or 1N4008 types.

These are rated 1 Amp at 400PIV, 600PIV and 1000PIV respectively. Always be on the

lookout for the higher voltage ones when they are on special.

TRANSFORMER RATING –

In our example above we were taking 0.5A out of the Vsec of 10V. The VA required is 10

X 0.5A = 5VA. This is a small PCB mount transformer available in Australia and probably

elsewhere.

This would be an absolute minimum and if you anticipated drawing the maximum currentall the time then go to a higher VA rating.

The two capacitors in the primary side are small value types and if you don't know

precisely and I mean precisely what you are doing then OMIT them. Their loss won't cause you

heartache or terrible problems.



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THEY MUST BE HIGH VOLTAGE TYPES RATED FOR A.C USE

The fuse F1 must be able to carry the primary current but blow under excessive current, in

this case we use the formula from the diagram. Here N = 240V / 10V or perhaps 120V / 10V.

CONSTRUCTION

The whole project MUST be enclosed in a suitable box. The main switch (preferably

double pole) must be rated at 240V or 120V at the current rating. All exposed parts within the

box MUST be fully insulated, preferably with heat shrink tubing.

Rectifiers:

A rectifier is an electrical device that converts alternating current (AC) to direct current

(DC), a process known as rectification. Rectifiers have many uses including as components of

power supplies and as detectors of radio signals. Rectifiers may be made of solid-state diodes,

vacuum tube diodes, mercury arc valves, and other components.

A device that it can perform the opposite function (converting DC to AC) is known as an

inverter.

When only one diode is used to rectify AC (by blocking the negative or positive portion

of the waveform), the difference between the term diode and the term rectifier is merely one of

usage, i.e., the term rectifier describes a diode that is being used to convert AC to DC. Almost all

rectifiers comprise a number of diodes in a specific arrangement for more efficiently converting

AC to DC than is possible with only one diode. Before the development of silicon semiconductor

rectifiers, vacuum tube diodes and copper (I) oxide or selenium rectifier stacks were used.

Half-wave rectification:

In half wave rectification, either the positive or negative half of the AC wave is passed,

while the other half is blocked. Because only one half of the input waveform reaches the output,

it is very inefficient if used for power transfer. Half-wave rectification can be achieved with a

single diode in a one-phase supply, or with three diodes in a three-phase supply.



24

Input Output

Fig 3.1.4:Half wave rectifier circuit.

The output DC voltage of a half wave rectifier can be calculated with the following two

ideal equations.

Full wave rectifier:

Full wave rectifier is available in two ways like center-tapped full-wave rectifier and

bridge full-wave rectifier.

The Bridge rectifier is a circuit, which converts an ac voltage to dc voltage using both

half cycles of the input ac voltage. The Bridge rectifier circuit is shown in the figure. The circuit

has four diodes connected to form a bridge. The ac input voltage is applied to the diagonally



25

opposite ends of the bridge. The load resistance is connected between the other two ends of the

bridge.

For the positive half cycle of the input ac voltage, diodes D1 and D3 conduct, whereas

diodes D2 and D4 remain in the OFF state. The conducting diodes will be in series with the load

resistance RL and hence the load current flows through RL.

For the negative half cycle of the input ac voltage, diodes D2 and D4 conduct whereas,

D1 and D3 remain OFF. The conducting diodes D2 and D4 will be in series with the load

resistance RL and hence the current flows through RL in the same direction as in the previous half

cycle. Thus a bi-directional wave is converted into a unidirectional wave.

Input Output

Fig 3.1.5 : full-wave rectifier using 4 diodes



26

Center Tapped Full wave rectifier:

For single-phase AC, if the transformer is center-tapped, then two diodes back-to-back

(i.e. anodes-to-anode or cathode-to-cathode) can form a full-wave rectifier. Twice as many

windings are required on the transformer secondary to obtain the same output voltage compared

to the bridge rectifier above.

For the positive half cycle of the input ac voltage, diodes D1 will conducts, whereas

diodes D2 is in the OFF state. The conducting diodes D1 will be in series with the load resistance

RL and hence the load current flows through RL.

For the negative half cycle of the input ac voltage, diodes D2 will conduct, whereas

diodes D1 is in the OFF state. The conducting diodes D2 will be in series with the load resistance

RL and hence the load current flows through RL.

Input Output

Fig 3.1.6 : Center tapped Full-wave rectifier using a transformer and 2 diodes.



27

DB107:

Now a days Bridge rectifier is available in IC with a number of DB107. In our project we

are using an IC in place of bridge rectifier.

FEATURES:

Good for automation insertion

Surge overload rating - 30 amperes peak

Ideal for printed circuit board

Reliable low cost construction utilizing molded

Glass passivated device

Polarity symbols molded on body

Mounting position: Any

Weight: 1.0 gram

Fig 3.1.7: DB107

Filters:

Electronic filters are electronic circuits, which perform signal-processing functions,

specifically to remove unwanted frequency components from the signal, to enhance wanted ones.

Passive filters:

Passive implementations of linear filters are based on combinations of resistors (R),

inductors (L) and capacitors (C). These types are collectively known as passive filters, because

they do not depend upon an external power supply and/or they do not contain active components

such as transistors.



28

Inductors block high-frequency signals and conduct low-frequency signals, while

capacitors do the reverse. A filter in which the signal passes through an inductor, or in which a

capacitor provides a path to ground, presents less attenuation to low-frequency signals than high-

frequency signals and is a low-pass filter. If the signal passes through a capacitor, or has a path to

ground through an inductor, then the filter presents less attenuation to high-frequency signals

than low-frequency signals and is a high-pass filter. Resistors on their own have no frequency-

selective properties, but are added to inductors and capacitors to determine the time-constants of

the circuit, and therefore the frequencies to which it responds.

The inductors and capacitors are the reactive elements of the filter. The number of

elements determines the order of the filter. In this context, an LC tuned circuit being used in a

band-pass or band-stop filter is considered a single element even though it consists of twocomponents.

At high frequencies (above about 100 megahertz), sometimes the inductors consist of

single loops or strips of sheet metal, and the capacitors consist of adjacent strips of metal. These

inductive or capacitive pieces of metal are called stubs.

Regulators:

A voltage regulator (also called a ‗regulator‘) with only three terminals appears to be a

simple device, but it is in fact a very complex integrated circuit. It converts a varying input

voltage into a constant ‗regulated‘ output voltage. Voltage Regulators are available in a variety

of outputs like 5V, 6V, 9V, 12V and 15V. The LM78XX series of voltage regulators are

designed for positive input. For applications requiring negative input, the LM79XX series is

used. Fig. 1 shows the pin configuration of a 5V 7805 regulator. Using a pair of ‗voltage-divider‘

resistors can increase the output voltage of a regulator circuit.

It is not possible to obtain a voltage lower than the stated rating. You cannot use a 12V

regulator to make a 5V power supply. Voltage regulators are very robust. These can withstand

over-current draw due to short circuits and also over-heating. In both cases, the regulator will cut

off before any damage occurs. The only way to destroy a regulator is to apply reverse voltage to

its input. Reverse polarity destroys the regulator almost instantly.



30

Besides replacing fixed regulators, the LM117 is useful in a wide variety of other

applications. Since the regulator is ―floating‖ and sees only the input-to-output differential

voltage, supplies of several hundred volts can be regulated as long as the maximum input to

output differential is not exceeded, i.e., avoid short-circuiting the output.

Also, it makes an especially simple adjustable switching regulator, a programmable

output regulator, or by connecting a fixed resistor between the adjustment pin and output, the

LM117 can be used as a precision current regulator. Supplies with electronic shutdown can be

achieved by clamping the adjustment terminal to ground, which programs the output to 1.2V

where most loads draw little current.

3.2 MAX 232:

GENERAL DESCRIPTION:

Serial RS-232 (V.24) communication works with voltages (-15V ... -3V for high

[sic]) and +3V ... +15V for low [sic]) which are not compatible with normal computer logic

voltages. On the other hand, classic TTL computer logic operates between 0V ... +5V (roughly

0V ... +0.8V for low, +2V ... +5V for high). Modern low-power logic operates in the range of 0V

... +3.3V or even lwer.

Fig 3.2: MAX 232 I.C

http://en.wikibooks.org/wiki/Image:Max232.jpg



31

When a processor communicates with the outside world, it provides data in byte sized chunks.

Computers transfer data in two ways: parallel and serial. In parallel data transfers, often more

lines are used to transfer data to a device and 8 bit data path is expensive. The serial

communication transfer uses only a single data line instead of the 8 bit data line of parallel

communication which makes the data transfer not only cheaper but also makes it possible for two

computers located in two different cities to communicate over telephone.

Serial data communication uses two methods, asynchronous and synchronous. The

synchronous method transfers data at a time while the asynchronous transfers a single byte at a

time. There are some special IC chips made by many manufacturers for data communications.

These chips are commonly referred to as UART (universal asynchronous receiver-transmitter)

and USART (universal synchronous asynchronous receiver transmitter). The AT89C51 chip has

a built in UART.In asynchronous method, each character is placed between start and stop bits.

This is called framing. In data framing of asynchronous communications, the data, such as ASCII

characters, are packed in between a start and stop bit. We have a total of 10 bits for a character: 8

bits for the ASCII code and 1 bit each for the start and stop bits. The rate of serial data transfer

communication is stated in bps or it can be called as baud rate.

To allow the compatibility among data communication equipment made by various

manufacturers, and interfacing standard called RS232 was set by the Electronics industries

Association in 1960. Today RS232 is the most widely used I/O interfacing standard. This

standard is used in PCs and numerous types of equipment. However, since the standard was set

long before the advent of the TTL logic family, its input and output voltage levels are not TTL

compatible. In RS232, a 1 bit is represented by -3 to -25V, while a 0 bit is represented +3 to +25

V, making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system

we must use voltage converters such as MAX232 to connect the TTL logic levels to RS232

voltage levels and vice versa. MAX232 ICs are commonly referred to as line drivers.



32

Fig 3.2.1: Port declaration of I.C MAX 232

The RS232 cables are generally referred to as DB-9 connector. In labeling, DB-9P refers to the

plug connector (male) and DB-9S is for the socket connector (female). The simplest connection

between a PC and microcontroller requires a minimum of three pin, TXD, RXD, and ground.

Many of the pins of the RS232 connector are used for handshaking signals. They are bypassed

since they are not supported by the 8051 UART chip.

IBM PC/ compatible computers based on x86(8086, 80286, 386, 486 and Pentium)

microprocessors normally have two COM ports. Both COM ports have RS232 type connectors.

Many PCs use one each of the DB-25 and DB-9 RS232 connectors. The COM ports are



33

designated as COM1 and COM2. We can connect the serial port to the COM 2 port of a PC for

serial communication experiments. We use a DB9 connector in our arrangement.

The AT89C52 has two pins that are used specifically for transferring and receiving data

serially. These two pins are called TXD and RXD and are part of the port3 (P3.0 and P3.1).These pins are TTL compatible; therefore they require a line driver to make them RS232

compatible. One such line driver is the MAX232 chip. One advantage of MAX232 chip is that it

uses a +5v power source which is the same as the source voltage for the at89c51. The MAX232

has two sets of line drivers for receiving and transferring data. The line drivers for TXD are

called T1 and T2 while the line drivers for RXD are designated as R1 and R2. T1 and R1 are

used for TXD and RXD of the 89c51 and the second set is left unused. In MAX232 that the TI

line driver has a designation of T1 in and T1 out on pin numbers 11 and 14, respectively. The T1

in pin is the TTL side and is connected to TXD of the microcontroller, while TI out is the RS232

side that is connected to the RXD pin of the DB9 connector.

To allow data transfer between PC and the microcontroller system without any error, we

must mak e sure that the baud rate of the 8051 system matches the baud rate of the PC‘s COM

port.

When communicating with various microprocessors one need convert the RS232 levels

down to lower levels, typically 3.3 or 5.0v.

RS232 TTL logic

-15v .. -3v +2v.. +5v HIGH

+3v .. +15v 0v..+8v LOW



34

Thus the RS232 signal levels are far too high TTL electronics, and the negative RS232

voltage for high cant be handle at all by computer logic. To receive serial data from an RS232

interface the voltage has to be reduced. Also the high and low voltages are to be inverted.

This level converter uses MAX232 and five capacitors. The MAX232 from Maxim was the firstIC which in one package contains the necessary drivers and receivers to adapt the RS232 signal

voltage levels to TTL logic .It became popular because it just needs one voltage(+5v or +3.3v)

and generates the necessary RS232 levels.

1 x female serial port connector

1 x MAX232

4 x 1uf capacitor



35

1 x 10uf capacitor

soldering iron,wires,breadboard etc

RXD and TXD pins in the 8052:

The 8052 has two pins that are used specifically for transferring and receving data serially. These

two pins are called TXD and RXD and are part of the port 3 group. Pin 11 of the 8052 is assigned

to TXD and pin 10 is designated has RXD these pins are TTL compatible, therefore, they require

a line driver to make them RS232 compatiable. One such line driver is the MAX232 chip.

3.3 GPS – GLOBAL POSITIONING SYSTEM

Allow GPS receiver to determine its exact POSITION in longitude and latitude, velocity,

direction etc.

What is GPS?

Developed by the U.S. Department of Defense for the military, the Global Positioning System

(GPS) is a worldwide, satellite-based, radio navigation system that will give you the exact

position of your vehicles, no matter where they are, what time it is, or what the weather is like. Atotal of 24 satellites orbit the Earth, monitored continuously by earth stations. The satellites

transmit signals that can be detected by GPS receivers located in your vehicles and used to

determine their location with great accuracy.

HOW DOES GPS WORK?

Each GPS satellite transmits radio signals that enable the GPS receivers to calculate

where its (or your vehicles) location on the Earth and convert the calculations into geodetic

latitude, longitude and velocity. A receiver needs signals from atleast three GPS satellites to

pinpoint your vehicle‘s position. GPS Receivers commonly used in most Vehicle tracking

systems can only receive data from GPS Satellites. They cannot communicate back with GPS or

any other satellite.



36

GPS Receiver can only Receive data and cannot send data to Satellite A system based on

GPS can only calculate its location but cannot send it to central control room. In order to do this

they normally use GSM-GPRS Cellular networks

connectivity using additional GSM modem/module.

GPS satellites do not know the position of a GPS Receiver. GPS Receiver calculate its

position using data from 3-4 satellites and no single satellite know the calculations done by GPS

receiver or its position.

GPS Satellite service is freely available throughout the world, anyone anywhere can

receive GPS data by buying any off-the-shelf GPS receivers.GPS satellites are different satellites

and can only send small and week radio signals to earth.GPS Satellite signals are weak and can

be received normally with GPS antenna (external or integrated with GPS receiver) facing open

sky. GPS signals cannot be received inside the home, building, garage, bridges. Even clouds and

Trees can prevent GPS signals from reaching GPS receiver. Hence no GPS receiver can

guarantee performance. Certain advanced and sensitive GPS receivers can receive signals in

above situations but performance is still not satisfactory.

GPS receivers have cannot give accurate position, Normally errors from plus/minus

5meters to 25 meters are possible.GPS receiver only give Latitude, Longitude and Velocity

calculated. To know your location you need highly accurate map. If maps are not accurate you

will have much high error in location. Normally accuracy of Maps is considered more important

then accuracy of GPS Receiver

GPS Architecture

The GPS system is divided into three segments:

The Space Segment The Control Segment

The User Segment



37

The Space Segment

GPS uses more than two dozen operational satellites, with an additional three satellites in orbit as

redundant backup.

GPS uses NAVSTAR satellites manufactured by Rockwell International. Each NAVSTAR

satellite is approximately 5 meters wide (with solar panels extended) and weighs approximately

900Kg.

GPS satellites orbit the earth at an altitude of approximately 20,200Km.

Each GPS satellite has an orbital period of 11 hours and 58 minutes. This means that each GPS

satellite orbits the Earth twice each day. Highly accurate atomic clocks are installed on these

satellites, operating at a fundamental frequency of 10.23MHz each. With the help of theseclocks, signals are generated from the satellite, to be broadcast to the Earth.

These twenty-four satellites orbit in six orbital planes, or paths. This means that four GPS

satellites operate in each orbital plane.

Each of these six orbital planes is spaced sixty degrees apart. All of these orbital planes are

inclined fifty-five degrees from the Equator.

The Control Segment

The Control Segment is comprised of a master control station, 5 monitor stations and 4 ground

antennas. All of these are strategically located along the Equator.

The Master Control Station (MCS) of the GPS system is operated at Schriever Air Force Base in

Colorado Springs, Colorado. The United States Air Force maintains redundant Master Control

Stations in Rockville, Maryland and Sunnyvale, California.

The Air Force also maintains monitoring stations in Colorado Springs, Hawaii, The Ascension

Islands, Diego Garcia, and Kwajalein.

Key Functions of the Control Segment

The Control Segment keeps track of the orbiting position of the GPS satellites, calibrating and

synchronizing their clocks.



38

It also predicts the path of each satellite for the following 24 hours, and uploads this information

to each satellite.

Communications with the space segment are conducted through ground antennas in the

Ascension Islands, Diego Garcia, and Kwajalein. The satellite signals are read here and themeasurements sent to the Master Control Station in Colorado. The signals are processed there to

determine any errors, and sent back to the four monitor stations with ground antennas, after

which the information is uploaded back to the satellites.

The User Segment

The GPS user segment is constituted by a GPS receiver, with the help of which the user can

determine his/her location.

3.4 GSM-GLOBAL SYSTEM MONITORING

Throughout the evolution of cellular telecommunications, various systems have been

developed without the benefit of standardized specifications. This presented many problems

directly related to compatibility, especially with the development of digital radio technology. The

GSM standard is intended to address these problems.

From 1982 to 1985 discussions were held to decide between building an analog or digital

system. After multiple field tests, a digital system was adopted for GSM. The next task was to

decide between a narrow or broadband solution. In May 1987, the narrowband time division

multiple access (TDMA) solution was chosen. A summary of GSM milestones is given in Table

Table GSM Milestones

Year Milestone

1982 GSM formed

1986 field test



39

1987 TDMA chosen as access method

1988 memorandum of understanding signed

1989 validation of GSM system

1990 preoperation system

1991 commercial system start-up

1992 coverage of larger cities/airports

1993 coverage of main roads

Why has GSM been successful?

The success of GSM is that its development was founded on the delivery of a specific

user benefit - international roaming. The demands of international roaming had profound

changes on GSM‘s architecture and mandated an open future-proof standard that ensured

interoperability, without stifling competition, and innovation among suppliers. This lowered

barriers to entry, promoted compatibility between systems which, in turn, lowered development

costs and set the stage for better choice and innovation. The unparalleled economies of scale and

competition that resulted brought convenience and falling prices to manufacturers, network

operators and consumers.

The adoption of a digital system offered improved mobility, spectrum efficiency,

better quality transmission and new services over the first generation systems. The

use of Very Large Scale Integration (VLSI) microprocessor technology and other low

cost IC architectures paved the way for more efficient and affordable pocket-sized



40

mobile phones. This resulted in a profound change in users‘ mobile communication

style from vehicular-based to personal, opportunity-based communications.

Although GSM is only one of the pieces in the cluster of current and future

telecommunications networks, its ability to provide anytime, and almost anywhere,

communications has resulted in tremendous economic and social consequences.

Without GSM the pace of development of mobile telephony would have pared

dramatically and that additional revenue streams, such as roaming (estimated globally at $1.78bn

in 2003), would not have been as successful.

The GSM Network:

GSM provides recommendations, not requirements. The GSM specifications define the

functions and interface requirements in detail but do not address the hardware. The reason for

this is to limit the designers as little as possible but still to make it possible for the operators to

buy equipment from different suppliers. The GSM network is divided into three major systems:

the switching system (SS), the base station system (BSS), and the operation and support system

(OSS). The basic GSM network elements are shown.



41

GSM Network Elements

Fig 3.4: GSM Network elements

The Switching System:

The switching system is responsible for performing call processing and subscriber-

related functions. The switching system includes the following functional units.

home location register (HLR) — The HLR is a database used for storage and

management of subscriptions. The HLR is considered the most important database, as it

stores permanent data about subscribers, including a subscriber's service profile, location

information, and activity status. When an individual buys a subscription from one of the

PCS operators, he or she is registered in the HLR of that operator.

mobile services switching center (MSC) — The MSC performs the telephony switching

functions of the system. It controls calls to and from other telephone and data systems. It



42

also performs such functions as toll ticketing, network interfacing, common channel

signaling, and others.

visitor location register (VLR) — The VLR is a database that contains temporary

information about subscribers that is needed by the MSC in order to service visiting

subscribers. The VLR is always integrated with the MSC. When a mobile station roams

into a new MSC area, the VLR connected to that MSC will request data about the mobile

station from the HLR. Later, if the mobile station makes a call, the VLR will have the

information needed for call setup without having to interrogate the HLR each time.

authentication center (AUC) — A unit called the AUC provides authentication and

encryption parameters that verify the user's identity and ensure the confidentiality of each

call. The AUC protects network operators from different types of fraud found in today's

cellular world.

equipment identity register (EIR) — The EIR is a database that contains information

about the identity of mobile equipment that prevents calls from stolen, unauthorized, or

defective mobile stations. The AUC and EIR are implemented as stand-alone nodes or as

a combined AUC/EIR node.

The Base Station System (BSS):

All radio-related functions are performed in the BSS, which consists of base station

controllers (BSCs) and the base transceiver stations (BTSs).

BSC — The BSC provides all the control functions and physical links between the MSC

and BTS. It is a high-capacity switch that provides functions such as handover, cell

configuration data, and control of radio frequency (RF) power levels in base transceiver

stations. A number of BSCs are served by an MSC.

BTS — The BTS handles the radio interface to the mobile station. The BTS is the radio

equipment (transceivers and antennas) needed to service each cell in the network. A

group of BTSs are controlled by a BSC.



43

The Operation and Support System:

The operations and maintenance center (OMC) is connected to all equipment in the

switching system and to the BSC. The implementation of OMC is called the operation and

support system (OSS). The OSS is the functional entity from which the network operator

monitors and controls the system. The purpose of OSS is to offer the customer cost-effective

support for centralized, regional, and local operational and maintenance activities that are

required for a GSM network. An important function of OSS is to provide a network overview

and support the maintenance activities of different operation and maintenance organizations.

GSM Subscriber Services:

There are two basic types of services offered through GSM: telephony (also referred to as

teleservices) and data (also referred to as bearer services). Telephony services are mainly voice

services that provide subscribers with the complete capability (including necessary terminal

equipment) to communicate with other subscribers. Data services provide the capacity necessary

to transmit appropriate data signals between two access points creating an interface to the

network. In addition to normal telephony and emergency calling, the following subscriber

services are supported by GSM,

dual-tone multifrequency (DTMF) — DTMF is a tone signaling scheme often used for

various control purposes via the telephone network, such as remote control of an

answering machine. GSM supports full-originating DTMF.

facsimile group III — GSM supports CCITT Group 3 facsimile. As standard fax

machines are designed to be connected to a telephone using analog signals, a special fax

converter connected to the exchange is used in the GSM system. This enables a GSM –

connected fax to communicate with any analog fax in the network.

short message services — A convenient facility of the GSM network is the short message

service. A message consisting of a maximum of 160 alphanumeric characters can be sent

to or from a mobile station. This service can be viewed as an advanced form of

alphanumeric paging with a number of advantages. If the subscriber's mobile unit is

powered off or has left the coverage area, the message is stored and offered back to the



44

subscriber when the mobile is powered on or has reentered the coverage area of the

network. This function ensures that the message will be received.

cell broadcast — A variation of the short message service is the cell broadcast facility. A

message of a maximum of 93 characters can be broadcast to all mobile subscribers in a

certain geographic area. Typical applications include traffic congestion warnings and

reports on accidents.

voice mail — This service is actually an answering machine within the network, which is

controlled by the subscriber. Calls can be forwarded to the subscriber's voice-mail box

and the subscriber checks for messages via a personal security code.

fax mail — With this service, the subscriber can receive fax messages at any fax machine.

The messages are stored in a service center from which they can be retrieved by the

subscriber via a personal security code to the desired fax number

GSM ADVANTAGES AS PERCEIVED BY PROPONENTS:

Already deployed as a worldwide standard

o 35 million subscribers today

o 150 million subscribers in 1999 (est.), outnumbering CDMA 7 to 1

National/International roamingo PCS1900 architecture supports full network interoperability

Total system specified in standard

o ―CDMA is just an air interface‖

Voice quality comparable to wireline

o Enhanced full rate vocoder (13 Kbps)

Subscriber Identity Module (SIM) card

o Increased flexibility and utility

o Allows worldwide roaming

o Stores personal phone numbers, missed calls, voice mail notification, text

messages



45

GSM’S economic impact:

It is estimated that global subscribers will exceed 1.5bn in 2004 and reach 2.3bn by 2010.

And expectations are that at least 85% of the world's next-generation wireless customers utilise

the GSM family of technologies for both voice and data services. Mobile network operator

revenues alone totaled $426bn in 2003 (based on current exchange rates), an increase of 19%

versus 2002. Beliefs are that GSM accounted for 65% of this total. Returns analysis suggests that

the sector is highly profitable. In addition, estimates are that mobile telephony has created 4.1m

jobs worldwide and within this GSM itself accounts for 75%. Following a couple of weaker

years, beliefs are that job creation will recommence and expect the industry to reach 10m

employees by 2010.

GSM’s social impact:

Probably no single telecommunication system in recent history has had as profound an

impact on global society than the GSM mobile phone. Its unprecedented growth in the world has

paved the way for increased mobile telephone usage and brought badly needed modern

telecommunications services to undeserved communities in thedeveloping world.

GSM’s future key success factors (KSFs):

Over the next five years, several KSFs for the mobile industry will influence the market as

we transition to the new 3G environment. These include:

Enabling convergence with other wireless technologies

Developing mobile centric applications

Evolving the mobile business model

Introducing mobile terminal enhancements and variety

Fostering industry partnerships and co-operations

Interoperability and intergenerational roaming between various platforms



46

3.5 MEMS:( Microelectromechanical systems)

The MMA7260QT low cost capacitive micro-machined accelerometer features signal

conditioning, a single-pole low pass filter, temperature compensation and g-Select which allows

for the selection among 4 sensitivities. Zero-g offset full scale span and filter cut-off are factoryset and require no external devices. Includes a Sleep Mode that makes it ideal for handheld

battery powered electronics.

Features:

• Selectable Sensitivity (1.5g/2g/4g/6g)

• Low Current Consumption: 500 μA

• Sleep Mode: 3 μA

• Low Voltage Operation: 2.2 V – 3.6 V

• 6mm x 6mm x 1.45mm QFN

• High Sensitivity (800 mV/g @ 1.5g)

• Fast Turn On Time

• Integral Signal Conditioning with Low Pass Filter

• Robust Design, High Shocks Survivability

• Pb-Free Terminations

• Environmentally Preferred Package

• Low Cost

Typical Applications:

• HDD MP3 Player: Freefall Detection

• Laptop PC: Freefall Detection, Anti-Theft

• Cell Phone: Image Stability, Text Scroll, Motion Dialing, E-Compass

• Pedometer: Motion Sensing

• PDA: Text Scroll

• Navigation and Dead Reckoning: E-Compass Tilt Compensation

• Gaming: Tilt and Motion Sensing, Event Recorder

• Robotics: Motion Sensing



47

ORDERING INFORMATION

Device Name Temperature

Range

Package

Drawing

Package

MMA7260QT – 40 to +105°C 1622-02 QFN-16, TrayMMA7260Q

R2

– 40 to +105°C 1622-02 QFN-16,Tape &

Reel

MMA7260QT: XYZ AXIS

ACCELEROMETER

±1.5g/2g/4g/6g

Bottom View top veiw



49

Table 5. Operating Characteristics

Unless otherwise noted: – 40°C < TA < 105°C, 2.2 V < VDD < 3.6 V, Acceleration = 0g, Loaded

output

Characteristic Symbol Min Typ Max UnitOperating Range(2) Supply Voltage(3)

Supply Current

Supply Current at Sleep Mode(4)

Operating Temp Range Acceleration Range,

X-Axis, Y-Axis, Z-Axis

VDD

IDD

IDD

TA

gFS gFS gFS

2.2

—

—

40

—

3.3 500

3.0

±1.5

±2.0

±4.0

±6.0

3.6

800

10

+105

— — —

V

μA

μA

°C

g g g

Output Signal

Zero-g (TA = 25°C, VDD = 3.3 V)(5) Zero-g(4)

X-axis

Y-axis

Z-axis Sensitivity (TA = 25°C, VDD = 3.3 V)

1.5g

VOFF VOFF, TA

S1.5g

S2g

S4g

S6g S,TA

f-3dB f-3dB

1.485

±2 6(6)

±5.8(6)

±1.0(6)

740

555

277.5

1.65

±0.6

±5.8

±0.8

800 600

300 200

±0.02

1.815

±3 8(7) ±5

9(7)

±0.8(7)

860

645

322.5

V

mg/°C

mV/g

mV/g

mV/g

mV/g

%/°C

Hz Hz

Noise

RMS (0.1 Hz – 1 kHz)(4)

nRMS nPSD — — 4.7 350 — — mVrms

l^g/Hz

Control Timing

Power-Up Response Time(8)

Enable Response Time(9)

tRESPONSE

tENABLE

fGCELL

— —

— —

—

1.0 0.5

6.0 3.4

11

2.0 2.0

— — —

ms ms

kHz

kHz

kHzOutput Stage Performance VFSO VSS+0.

— VDD – 0.25 V

Nonlinearity, XOUT, YOUT, ZOUT NLOUT – 1.0 — +1.0 %FSO

Cross-Axis Sensitivity(10) VXY, XZ, YZ — — 5.0 %

Ratiometric Error(11) error — — — %



50

1. For a loaded output, the measurements are observed after an RC filter consisting of a 1.0

kΩ resistor and a 0.1 µF capacitor on VDD-GND.

2. These limits define the range of operation for which the part will meet specification.

3. Within the supply range of 2.2 and 3.6 V, the device operates as a fully calibrated linear

accelerometer. Beyond these supply limits the device may operate as a linear device but is

not guaranteed to be in calibration.

4. This value is measured with g-Select in 1.5g mode.

5. The device can measure both + and – acceleration. With no input acceleration the output is

at midsupply. For positive acceleration the output will increase above VDD /2. For negative

acceleration, the output will decrease below VDD /2.

6. These values represent the 10th percentile, not the minimum.

7. These values represent the 90th percentile, not the maximum.

8. The response time between 10% of full scale VDD input voltage and 90% of the final

operating output voltage.

9. The response time between 10% of full scale Sleep Mode input voltage and 90% of the

final operating output voltage.

10. A measure of the device‘s ability to reject an acceleration applied 90 from the true axis of

sensitivity.

11. Zero-g offset ratiometric error can be typically >20% at VDD = 2.2 V. Sensitivity

ratiometric error can be typically >3% at VDD = 2.2. Consult factory for additional

information.



51

CHAPTER 4

INTRODUCTION TO KEIL SOFTWARE

Software tools used

Pcb wizard for schematic

Keil micro vision for writing source code

Micro c flash for dumping the code

4.1KEIL µVision IDE Overview

4.1.1 What's New in µVision3

µVision3 adds many new features to the Editor like Text Templates, Quick Function Navigation, Syntax

Coloring with brace highlighting Configuration Wizard for dialog based startup and debugger setup.

µVision3 is fully compatible to µVision2 and can be used in parallel with µVision2.

4.1.2 What is µVision3?

µVision3 is an IDE (Integrated Development Environment) that helps you write, compile, and debug

embedded programs. It encapsulates the following components:

A project manager.

A make facility.

Tool configuration.

Editor.

A powerful debugger.

To help you get started, several example programs (located in the \C51\Examples, \C251\Examples,

\C166\Examples, and \ARM\...\Examples) are provided.

HELLO is a simple program that prints the string "Hello World" using the Serial Interface.



53

1. Select Debug - Start/Stop Debug Session.

2. Use the Step toolbar buttons to single-step through your program. You may enter G, main in the

Output Window to execute to the main C function.

3. Open the Serial Window using the Serial #1 button on the toolbar.

Debug your program using standard options like Step, Go, Break, and so on.

4.1.6 Starting µVision2 and Creating a Project

µVision2 is a standard Windows application and started by clicking on theprogram icon. To create a new

project file select from the µVision2 menu

Project - New Projec. This opens a standard Windows dialog that asks you

We suggest that you use a separate folder for each project. You can simply use the icon Create New

Folder in this dialog to get a new empty folder. Then select this folder and enter the file name for the new

project, i.e. Project1.

µVision2 creates a new project file with the name PROJECT1.UV2 which contains a default target and

file group name. You can see these names in the Project

4.1.7 Window – Files.

Now use from the menu Project – Select Device for Target and select a CPU for your project. The Select

Device dialog box shows the µVision2 device database. Just select the microcontroller you use. We are

using for ourexamples the Philips 80C51RD+ CPU. This selection sets necessary tool options for the

80C51RD+ device and simplifies in this way the tool Configuration

4.1.8 Building Projects and Creating a HEX Files

Typical, the tool settings under Options – Target are all you need to start a new application. You may

translate all source files and line the application with a click on the Build Target toolbar icon. When you

build an application with syntax errors, µVision2 will display errors and warning messages in the Output

Window – Build page. A double click on a message line opens the source file on the correct location in a

µVision2 editor window. Once you have successfully generated your application you can start debugging.

After you have tested your application, it is required to create an Intel HEX file to download the

software into an EPROM programmer or simulator. µVision2 creates HEX files with each build process

when Create HEX file under Options for Target – Output is enabled. You may start your PROM



54

programming utility after the make process when you specify the program under the option Run User

Program #1.

4.2 CPU Simulation

µVision2 simulates up to 16 Mbytes of memory from which areas can be mapped for read, write, or code

execution access. The µVision2 simulator traps and reports illegal memory accesses. In addition to

memory mapping, the simulator also provides support for the integrated peripherals of the various 8051

derivatives. The on-chip peripherals of the CPU you have selected are configured from the Device

4.2.1 Database selection

you have made when you create your project target. Refer to page 58 for more information about

selecting a device. You may select and display the on-chip peripheral components using the Debug menu.

You can also change the aspects of each peripheral using the controls in the dialog boxes.

4.2.2 Start Debugging

You start the debug mode of µVision2 with the Debug – Start/Stop Debug Session command. Depending

on the Options for Target – Debug configuration, µVision2 will load the application program and run the

startup code µVision2 saves the editor screen layout and restores the screen layoutof the last debug

session. If the program execution stops, µVision2 opens an editor window with the source text or shows

CPU instructions in the disassembly window. The next executable statement is marked with a yellow

arrow. During debugging, most editor features are still available.

For example, you can use the find command or correct program errors. Program source text of your

application is shown in the same windows. The µVision2 debug mode differs from the edit mode in the

following aspects:

_ The ―Debug Menu and Debug Commands‖ described on page 28 are available. The additional debug

windows are discussed in the following.

_ The project structure or tool parameters cannot be modified. All build commands are disabled.

4.2.3 Disassembly Window

The Disassembly window shows your target program as mixed source and assembly program or just

assembly code. A trace history of previously executed instructions may be displayed with Debug – View

Trace Records. To enable the trace history, set Debug – Enable/Disable Trace Recording.



55

If you select the Disassembly Window as the active window all program step commands work on CPU

instruction level rather than program source lines. You can select a text line and set or modify code

breakpoints using toolbar buttons or the context menu commands.

STEPS FOR SOURCE CODE CREATION:

1. Click on the Keil uVision Icon on Desktop

2. The following fig will appear

3. Click on the Project menu from the title bar

4. Then Click on New Project



56

5. Save the Project by typing suitable project name with no extension in u r own folder sited in

either C:\ or D:\

6. Then Click on save button above.

7. Select the component for u r project. i.e. Atmel……

8. Click on the + Symbol beside of Atmel



57

9. Select AT89C51 as shown below

10. Then Click on ―OK‖

11. The Following fig will appear

12. Then Click either YES or NO………mostly ―NO‖

13. Now your project is ready to USE

14. Now double click on the Target1, you would get another option ―Source group 1‖ as shown

in next page.



58

15. Click on the file option from menu bar and select ―new‖

16. The next screen will be as shown in next page, and just maximize it by double clicking on its

blue boarder.



59

17. Now start writing program in either in ―C‖ or ―ASM‖

18. For a program written in Assembly, then save it with extension ―. asm‖ and for ―C‖ based

program save it with extension ― .C‖

19. Now right click on Source group 1 and click on ―Add files to Group Source‖



60

20. Now you will get another window, on which by default ―C‖ files will appear.

21. Now select as per your file extension given while saving the file

22. Click only one time on option ―ADD‖

23. Now Press function key F7 to compile. Any error will appear if so happen.



61

24. If the file contains no error, then press Control+F5 simultaneously.

25. The new window is as follows

26. Then Click ―OK‖

27. Now Click on the Peripherals from menu bar, and check your required port as shown

in fig below



62

28. Drag the port a side and click in the program file.

29. Now keep Pressing function key ―F11‖ slowly and observe.

30. You are running your program successfully.



63

4.3 PCB Wizard 3

PCB Wizard 3 is a highly innovative package for designing single-sided and double sided printed

circuit boards. It provides a comprehensive range of tools covering all the traditional steps in PCB

production, including schematic drawing, schematic capture, component placement, automatic routing,and bill of materials reporting and files generation for manufacturing.

Designing circuit boards

PCB Wizard 3 is both easy to learn and easy to use. To design a circuit board, simple drag and

drop components onto your document and connect them together using the intelligent writing tool. Then

select the menu option ―convert to PCB‖ and leave PCB Wizard 3 to do the rest for you. If you want to

simulate your design before turning it into a circuit board, PCB Wizard 3 offers tight integration.

Component placing and automatic routing

Strategic component placement is critical to achieving successful routing and PCB Wizard 3 has

been greatly enhanced in this area. The process is now fully automated and it is able to calculate an

optimum board size for you and intelligently position components in preparation for automatic routing.

Style views

Styles are a powerful PCB Wizard 3 feature that greatly simplifies the process of viewing circuits.They are particularly useful when assembling and soldering circuit boards. The styles themselves are

simply combinations of various display options that after how the circuit looks, by clicking on the

different preset style settings.



64

Fig 4.3 PCB Wizard Window in Real Time

4.4 Flash Magic

4.4.1 Introduction

Flash Magic is Windows software from the Embedded Systems Academy that allows easy access

to all the ISP features provided by the devices. These features include:

• Erasing the Flash memory (individual blocks or the whole device)

• Programming the Flash memory

• Modifying the Boot Vector and Status Byte

• Reading Flash memory



65

• Performing a blank check on a section of Flash memory

• Reading the signature bytes

• Reading and writing the security bits

• Direct load of a new baud rate (high speed communications)

• Sending commands to place device in Boot loader mode

Flash Magic provides a clear and simple user interface to these features and more as described in the

following sections. Under Windows, only one application may have access the COM Port at any one

time, preventing other applications from using the COM Port. Flash Magic only obtains access to the

selected COM Port when ISP operations are being performed. This means that other applications that

need to use the COM Port, such as debugging tools, may be used while Flash Magic is loaded.

The screenshot of the main Flash Magic window is as shown in the figure. The appearance may

differ slightly depending on the device selected. It contains five blocks. The five blocks are explained as

follows:

4.4.2 Five Step Programming

Step 1 – Connection Settings Select the desired COM port from the drop down list or type the desired

COM port directly into the box. If you enter the COM port yourself then you must enter it in one of the

following formats:

• COM n

• n

Select the baud rate to connect at. Try a low speed first. The maximum speed that can be used

depends on the crystal frequency on your hardware.

Recommendation: Try 9600 baud first. If it does not work or

does not work reliably then try 7200 baud.

Select the device being used from the drop down list.

Ensure you select the correct one as different devices have

different feature sets and different methods of setting up the



66

serial communications.

Select the interface being used, if any. An interface is a device that connects between your PC

and the target hardware. If you simply have a serial cable or USB to serial cable connecting your COM

port to the target hardware, then chooses "None (ISP)". Choosing the correct interface will automatically

configure Flash Magic for that interface, along with enabling and disabling the relevant features.

Enter the oscillator frequency used on the hardware. Do not round the frequency, instead enter it

as precisely as possible. Some devices do not require the oscillator frequency to be entered, so this field

will not be displayed.

Step 2 – Erasing

This step is optional, however if you attempt to

program the device without first erasing at least one Flash

block, then Flash Magic will warn you and ask you if you are

sure you want to program the device. Select each Flash block

that you wish to erase by clicking on its name. If you wish to

erase all the Flash then check that option. If you want to erase a Flash block and all the Flash then the

Flash block will not be erased individually. If you wish to erase only the Flash blocks used by the hex file

you are going to select, then check that option.

Step 3 – Selecting the Hex File

This step is optional. If you do not wish to program a Hex File then do not select one. You can

either enter a path name in the text box or click on the Browse button to select a Hex File by browsing to

it. Also you can choose Open… from the File menu. Note that the Hex file is not loaded or cached in any

way. This means that if the Hex File is modified, you do not have to reselect it in Flash Magic. Every

time the Hex File is programmed it is first re-read from the location specified in the main window. This

information is updated whenever the hex file is modified.



67

Step 4 – Options

This section is optional, however Verify After

Programming, Fill Unused Flash and Gen Block

Checksums may only be used if a Hex File is selected(and therefore being programmed), as they all need to know

either the Hex File contents or memory locations used by

the Hex File. Checking the Execute option will cause the

downloaded firmware to be executed automatically after the programming is complete. Note that this will

not work if using the Hardware Reset option or a device that does not support this feature.

Step 5 – Performing the Operations

Clicking the Start button will result in all the selected operations in the main window taking

place. They will be in order:

• Erasing Flash

• Programming the Hex File

• Verifying the Hex File

• Filling Unused Flash

• Executing the firmwar



68

Figure 22 Flash Magic in Real Time

4.5 Programming Language

Programming language used in this project is C. C is a general purpose structured programming

language that is powerful, efficient and compact. It has emerged as the language of choice for most



69

applications due to speed, portability and compactness of code. The C compiler combines the capabilities

of an assembler language with the features of high level language.

C is highly portable. This means that C programs written for one computer can be on another with

little or no modification. Portability is important if we plan to use a new computer with a different

operating system.

C language is well suited for structured programming thus requiring the user to think of a

problem in terms of function modules and blocks. A proper collection of these modules make a complete

program. This modular structure makes program debugging, testing and maintenance easier.

Another important feature of C is its ability to extend itself. A C program is basically a collection

of functions that are supported by the C library. We can continuously add our own functions to the C

library. With the availability of a large number of functions, the programming task becomes simple.



70

CHAPTER 5

MERITS

It occupies less space and less energy

Motor mechanism in elevator is placed in the host way itself

Modernization can greatly improve the operational reliability by replacing the mechanical

relays



71

CHAPTER 6

APPLICATIONS



72

CHAPTER 7

RESULT:

This system is easy to implement and reduce dead percentage of people with the accident occur

using the wireless communication technologies



73

CHAPTER 8

CONCLUSION :



74

CHAPTER 9

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13. ^ Laermer, F.; Urban, A. (2005). Milestones in deep reactive ion etching. 2. .14. ^ J. M. Bustillo, R. T. Howe, and R. S. Muller, "Surface micromachining for

microelectromechanical systems" Proceedings of the IEEE, vol. 86, pp. 1552−1574,1998.

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Approaches to Improve Robustness. pp. 111 ff. ISBN 0387095357. 17. ^ Worldwide MEMS Systems Market Forecasted to Reach $72 Billion by 2011

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main documentation of batch 13

Documents