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MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

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Page 1: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

MagnaChip Semiconductors, Ltd.

The Corporate NPI Process - New Technology & Product Introduction (V 3.0)

January 30, 2010

Page 2: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

2MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

ContentsContents1. General Provisions1.1 Purpose, scope, and standardization committee1.2 Role & responsibility

2. NPI basics2.1 Project & NPI stages2.2 Project type definition2.3 Stepwise progress check2.4 Cross functional project management2.5 Change management2.6 Performance metrics

3. MC brand product development process3.1 Project classification3.2 Key activities3.3 Overall development process3.4 Key review points (P1 ~ P7)3.5 Summary of checkpoint approvers & deliverables3.6 Change management R&R

4. Foundry product development process4.1 ~ 4.6: Same order as section 3.1~3.6

5. MC brand technology development process5.1 Project classification5.2 Key activities5.3 Overall development process5.4 Key review points (T1~ T7)5.5 Summary of checkpoint approvers & deliverables5.6 Change management R&R5.7 DK update process

6. COTT process6.1 ~ 6.6: Same order as section 5.1 ~ 5.6

7. Qualification criteria7.1 Key summary of qualification test criteria7.2 Technology qualification items7.3 Product qualification items7.4 Product re-qualification criteria – general7.5 Product re-qualification criteria – power product7.6 Reliability test checklist

AppendixA1. Yield calculation modelA2. Terminologies

Page 3: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

3MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

Keydeliverables

Keydeliverables

• Project charter

• Kick off material• Work sheet• Key process

module setup• Unit setup

R&D

MFG

DirCP &Approver

T1Planning

T1Planning

T2 Kick off &key process

T2 Kick off &key process

TDRB Dir DirManager TDRB

Communication for productionCommunication for production Equipment CorrelationEquipment Correlation

P7 Yield UpP7 Yield Up

T3Pre DK

T3Pre DK

T4Si verified spec

T4Si verified spec

T5Tech freeze

T5Tech freeze

T6Product level qual

T6Product level qual

StagereviewStagereview

5.4 Key review points (T1 ~ T7)

Full chip design & evaluationFull chip design & evaluation

Yield >70% Yield >70%

ProjectcharterProjectcharter

POR 1.0 review

POR 1.0 review

Product yield CUM ≥ 90%

Product yield CUM ≥ 90%

TDV with IP/Libdesign & eval

TDV with IP/Libdesign & eval

1st POR review

1st POR review

DK 0.0DK 0.0Kick off

Kick off

Key process module setupKey process module setup

POR 0.8

POR 0.8

Product level qualProduct

level qual

TDRBpassreject

TCP

MDV designMDV

design

CP

CP

PDK 0.1

PDK 0.1

CP

TCP TDRB

TuningTuning

RevisionRevisionCP

Internalreview

Internalreview

SpecSpec

CP

• DR doc• Tooling

spec• Pre DK

v 0.0• POR 0.0

• Si verified spec• 1st POR data• PDK v 0.1

• Development report• Qualification data

- Product, IP/Lib qual- 2nd & 3rd WLR data

• POR 1.0 review• PDK 1.0

• Product yield trend

• Equipment multiplication

• Tech maintenance

TDRB TCPCPTCP TCP

WBSWBS

CP CPCP CP CP CP CP

Device checklistDevice

checklistIP / Lib qual passIP / Lib qual passPlatform

reviewPlatform review

Biz impact review

Biz impact review

DRDR

TCP

Si verified specPOR 0.1

Si verified specPOR 0.1

Process freeze

Process freeze

1ST WLRpass

1ST WLRpass

CP

PDK 0.9

PDK 0.9

ESD ruleESD rule

CP

Final WLRpass

Final WLRpass

CP

Tech maintenance

Tech maintenance

PDK 1.0

PDK 1.0

PDK 1.x

PDK 1.xTP planTP plan

MilestoneRisk reviewMilestone

Risk review

TDRB

Unit process setup

Unit process setup

• Tech setup report- TDV (w IP/Lib) evaluation data- POR v 0.8

• 1st WLR data• FMEA• PDK & POR 0.9

Page 4: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

4MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.1.1 T1 – deliverables (platform / derivative / option)

• Marketability (Marketing)

Category

Project code(PM)

Deliverables Key contents

• Technical feasibility & risks (PM)

• Market trend & competitiveness• Business impact analysis• Target customer & spec

Project charter

(Marketing, PM, & QRA)

• Technical issues- equip capability, patent, etc

• Lesson learned

• Project priority (Marketing)

• NPV (ROI) data• Strategic importance• Project priority setting

• Project code generation • Code generation request

Timeline

AfterT1 TDRB approval

BeforeT1 TDRB review• Development plan (PM)

• Key milestones, development cost• Risk assessment

• Qualification plan (QRA)• Qualification criteria• Key milestones• Risk assessment

• For Option project: Some owners can be changed (Project manager Div PE, Marketing account manager)

Page 5: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

5MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.2.1 T2 – deliverables (platform / derivative)

CategoryDeliverables Key contents

Kick off material

(PM)

Timeline

At T2kick off meeting

• Target spec & schedule (PM)

• Device implementation target• Development schedule• Project staffing & organization

• Technical issues (PM)

• Risk assessment (patent, etc)• Equipment / measurement capability review (PM / MEC)

• Reliability test methodology (QRA)• Customer urgency, implementation difficulties, etc

Work sheet(PM)

• Work breakdown structure

• Key activities & deliverable listof each NPI stage

At T2 TCP review

Key process module setup

report (PM)

• Key process module setup review

• Implementation target, risks, and resultsAt T2 TCP review

(if exist)Unit process setup report

(PM)

• Unit process & OPC review

• New unit process & equipment review• OPC rule review

Page 6: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

6MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.3 T3 Preliminary design kit – CP (platform / derivative)

• Design rule doc & tooling spec (v 0.0)

CategoryDeliverables Key contents

• DR doc v 0.0• Preliminary tooling spec

DR & tooling(CE tech)

Timeline

At T3 CP review• Spice model v 0.0• Preliminary rule deck

• Preliminary design kit

• Control plan & e-sheet v 0.0• Control plan

Pre DK(CE infra)

POR 0.0 (CE tech)

Page 7: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

7MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.4.1 T4 – deliverables (platform / derivative)

• Device checklist• TCAD simulation result• MDV description & evaluation data

• Fab data (inline, PCM)

CategoryDeliverables Key contents

• Device checklist• TCAD simulation result• MDV description & evaluation data• Equipment capability review• DR margin review- TP readiness checkup

• Fab data - inline data, PCM data

Si verified spec(PM)

Timeline

At T4 TCPFE design review

meeting• Control plan & e-sheet

• 1st POR which is reviewed with Div PE & MEC

• Control plan & E-sheet

POR v 0.1(PM)

• Si verified DR & tooling• Si verified E-para• Si verified Spice model• Rule deck & Pcell• Bit cell data (if exist)

• DR doc (v 0.1)• Si verified mask tooling spec• Si verified E-parameters• Si verified model• Si verified rule deck • Preliminary Pcell & symbol• Bit cell ready (if exist)

PDK v 0.1(Infra)

Page 8: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

8MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.5.3 T5 – deliverables (platform / derivative)

CategoryDeliverables Key contents Timeline

• Device checklist• TDV plan & evaluation

• Device checklist• TDV (with ESD TP, IP/Lib, etc) plan & evaluation data

• E-test data – DR margin reviewTech setup

report(PM)

At T5 TCP review

• 1st WLR test data• WLR test condition & pass/fail criteria• WLR test data

1st WLR(QRA)

• DR doc• Tooling spec• PCM spec• E-para• Interconnect para• Spice model• Rule deck • Pcell & symbol• Bit cell ready (if exist)

• DR doc (core & ESD)• Mask tooling & reverse tooling spec• PCM spec• E-parameters• Interconnect parameters• Basic, matching, noise, etc.• DRC, LVS, XRC, auto JDV rule deck• Pcell & symbol• SRAM, 1T, NVM, etc.

PDK v 0.9(Infra)

• Control plan & e-sheet • Control plan & e-sheetPOR v 0.9

(PM)

• FMEA (technical issues) • Technical issues review dataFMEA(PM)

• Fab data– Inline, PCM data

• In-line data, PCM data• Equipment capability review

Page 9: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

9MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.5.4 T5 – deliverables (option)

CategoryDeliverables Key contents Timeline

Device setup report(PE)

At T5 TCP review• 1st WLR test data

• WLR test condition & pass/fail criteria• WLR test data

1st WLR(if exist)(QRA)

• DR doc (core & ESD)• Mask tooling spec• PCM spec• E-parameters• Interconnect parameters• Basic, matching, noise, etc.• DRC, LVS, XRC• Pcell & symbol

PDK v 0.9(Infra)

• Control plan & e-sheet • Control plan & e-sheetPOR v 0.9

(PE)

• FMEA (technical issues) • Technical issues review dataFMEA(PE)

• DR doc• Mask tooling spec• PCM spec• E-para• Interconnect para• Spice model• Rule deck • Pcell & symbol

• Device target spec• TP plan & evaluation• TCAD simulation result

• Device target spec review• TP description & & evaluation data• TCAD result – DR margin review• E-test data

• In-line data, PCM data• Equipment capability review

• Fab data – Inline, PCM data, corner split result

Page 10: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

10MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.6.1 T6 – WLR transfer criteria (to MFG)

• GDS data

itemCategory Key contents

• GDS data

WLR

• E-sheet• Cpk

• E-sheet• Cpk (each layer)• CD measurement sample (each layer)

Process

• 2nd & 3rd WLR test result• WLR test history (with improvement items)• Wafer requirements for each item

Device

• TP description• Keithley program & limit file name• Probe card (with pin number)• W-test spec• PCM capability index

DB

• TP & measurement program

• P-card• PCM spec

• Mask tooling• PG rule file• Mask data

• Mask tooling spec• Mask description (including wafer layout)• Mask revision history• Final mask set

Mask

• WLR maintenance shall start at T7.• After WLR transfer, lot owner of WLR maintenance becomes MEC (MFG).

• Basic rule for WLR transfer to MFG is to pass the 2nd & 3rd WLR test results.• If satisfies WLR items below, WLR owner shall be transferred to MFG

Page 11: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

11MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.6.2 T6 – deliverables (platform / derivative / option)

• Product or IP/Lib qualification data

CategoryDeliverables Key contents

• Reliability test data (QRA)

Development completion report (PM)

Timeline

At T6 TDRBProduct level qualification

review

Project code (PM) • Project code closure • Code close requestAfter T6 TDRB

approval

• WLR data• 2nd & 3rd WLR test data (QRA)• WLR transfer review

• Control plan & e-sheet• Inline spec

• Control plan & e-sheet, Inline spec which are reviewed with MEC (POR 1.0 review)

POR 1.0 (PM)

• Customer promotion material• Core rule & ESD rule• Mask tooling & reverse tooling spec• Final PCM spec• Basic, matching, noise, etc• E-para, Interconnect para• DRC, LVS, XRC, auto JDV rule deck• Pcell & symbol• SRAM, 1T, NVM, etc

PDK v 1.0(Infra)

• Development report• Development completion report• Product or IP/Lib evaluation data (Test)

Performance index (Develop mgnt)

• On-time rate, revision times, revenue hit rate, NPI obedience rate, etc.

Final qualification report (QRA)

• For option project: Div PE can do project manager’s role.

• Presentation material• DR doc• Mask tooling spec• PCM spec• Spice model• E-para, Interconnect para• Rule deck• Pcell & symbol• Bit cell (if exist)

• R&D performance• Market performance

Page 12: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

12MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.4.7.1 T7 Yield up – deliverables

• Yield data• Process data

CategoryDeliverables Key contents

• Yield trend data• Process control data• Lesson learned & PFMEA

Yield trend data

(MEC)

Timeline

During yield up activities

• PCRB data

• Yield trend data• Process control data• Lesson learned & PFMEA• Reason for why platform technology changes

PCRB data

If required for platform change

(MEC)

During yield up activities

• Tech maintenance data

• Tech maintenance data- tech vehicle review- process control data- Fab data review- yield data- issues

• Reason for why platform technology changes

Afterquarterly tech maintenance

• Recipe review data• Process uniformity check

• Equipment model based recipe checkup• Cp / Cpk review

Equipment multiplication

(MEC)Before mass production

Page 13: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

13MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.5 Summary of check point approvers & deliverables

Check point Deliverables Owner Meeting call Approver

Project type Platform Derivative Option P/D O P/D O P/D O

T1 TDRB Project charter TM AM CE planning TDRB

T2 TCP

Kick off materialWork sheetKey process module setup reportUnit process setup reportRisk assessment

CE PMCE tech director

T3 CPPreliminary DR doc & tooling specPre design kit (v 0.0)Preliminary POR (v 0.0)

CE PM PM

T4 TCPSi verified spec1st POR – control plan & e-sheetPDK v 0.1

CEMECCE

PMCE tech director

T5 TCP

Tech / device setup reportFMEA1st WLRPOR v 0.9 – control plan & e-sheetPDK v 0.9

CECE

QRACECE

PEPE

QRAPECE

PM PECE techdirector

Div PE director

T6 TCP

Development completion reportFinal qual report (PQV qual, WLR data)POR 1.0 – control plan & e-sheetPDK 1.0Performance index

CEQRAMECCECE

PEQRAMECCEPE

PM PE TDRB

T7Yield trend dataEquipment multiplicationPCRB data if tech changes

MEC MECMEC mgr

PCRB

* AM: account manager, PM: project manager

Page 14: MagnaChip Semiconductors, Ltd. The Corporate NPI Process - New Technology & Product Introduction (V 3.0) January 30, 2010

14MAGNACHIP CONFIDENTIAL. DO NOT COPY OR DISTRIBUTE.

5.6 Change management R&RCategory Key item Owner Approval Remark

Project type P/D O P/D O

Project initiation

Checkpoint review (TDRB) TM AM TDRB Deliverables registration onto MDCS

Project code generation PM PE CE director AM/PE mgr Use e-approval (Magnaware)

Development

Schedule revision PM PE GM PE directorIf delay to the coming TCP/CP >30%,

compared to the latest plan

Market revision(Biz potential, etc)

TM AMMarketing director

If market change > 30%,compared to the latest plan

Project drop

TM AM GM

Project code closure (e-approval)

Project holdProject inactivated (not counted for delay)

Revisit bimonthly for project drop or resume

Project resume Restarting from hold

Revision mask PM PE GM If revision occurs

Checkpoint review (T2-T5) - TCP - CP

PM PECE director

PMPE dir

PE mgrDeliverables registration onto MDCS

Completion

Final report (T6) PM PE TDRB Development completion & POR 1.0 review

Performance index - R&D performance - Marketing performance

PMTM

PEAM

TDRB Target, cost, & schedule

Revenue, gross margin, & hit ratio forecast

Project code closure PM PE CE director AM/PE mgr Use e-approval

Final DB registration PM PE CE director PE dir DB registration to DT team

Status monitoring

Project status monitoring - on time rate - deliverables status - revision times - NPI obedience status

Development planning part

GM Monthly status review

* AM: account manager, PM: project manager, GM: if CE project, CE head, and if Div project, Div head