ltc6801 - independent multicell battery stack fault monitor€¦ · 6801 ta01b v+ = 43.2v ov =...

LTC6801

16801fc

For more information www.linear.com/LTC6801

APPLICATIONS n Redundant Battery Monitor n Hybrid Electric Vehicles n Battery Backup Systems n Power Systems Using Multiple Battery Cells

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

n Monitors Up to 12 Li-Ion Cells in Series (60V Max) n Stackable Architecture Enables > 1000V Systems n 1% Maximum Overvoltage Detection Level Error n Adjustable Overvoltage and Undervoltage Detection n Self Test Features Guarantee Accuracy n Robust Fault Detection Using Differential Signals n Simple Pin-Strapped Configuration Allows Battery

Monitoring without a Microcontroller n 15.5ms to Monitor All Cells in a System n Programmable Response Time n Two Temperature Monitor Inputs n Low Power Idle Mode n 36-Lead SSOP Package

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

ERRO

R (%

)

1.0

–0.8

0.8

0.4

0

–0.4

0.6

0.2

–0.2

–0.6

–1.0

6801 TA01b

V+ = 43.2VOV = 4.116V

5 TYPICAL UNITS

BLOCK DIAGRAM

DESCRIPTION

Independent Multicell Battery Stack Fault Monitor

The LTC®6801 is a multicell battery monitoring IC in-corporating a 12-bit ADC, a precision voltage reference, sampled comparator, and a high voltage input multiplexer. The LTC6801 can monitor as many as 12 series con-nected battery cells for overvoltage, undervoltage, and overtemperature conditions, indicating whether the cells are within specified parameters. The LTC6801 generates a clock output when no fault conditions exist. Differential clocking provides high noise immunity and ensures that battery stack fault conditions cannot be hidden by frozen bits or short circuit conditions.

Each LTC6801 can operate with a battery stack voltage up to 60V and multiple LTC6801 devices can be stacked to monitor each individual cell in a long battery string. When multiple devices are stacked, the status signal of each LTC6801 can be daisy-chained, without opto-couplers or isolators, providing a single status output for the entire battery string.

The LTC6801 is configurable by external pin strapping. Adjustable overvoltage and undervoltage thresholds sup-port various Li-Ion chemistries. Selectable measurement times allow users to save power.

FEATURES

6801 TA01a

1

2

3

12

1320

22

14

15 16

VREFVTEMP1 VTEMP2

NTC

NTC

C1

C2

C11

C12

V+

V–

NEXT LOWERCELL PACK

NEXT HIGHERCELL PACK

12MUX

“CELLS GOOD”

ENABLEINPUT

ISOLATION

CLOCK SIGNAL INPUT ENABLES THE LTC6801

CLOCK SIGNALOUTPUT INDICATESSYSTEM “OK”

STATUSOUTPUT

CONTROLLOGIC

17

REFERENCE

LTC6801

ADC

0V Detection Level Error

http://www.linear.com/LTC6801


LTC6801

26801fc


PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (V+ to V–) .................................60VInput Voltage (Relative to V–)

C1 ............................................................ –0.3V to 9V C12 ...........................................V+ –0.3V to V+ + 0.3V All Other Pins (Not C Inputs) ................... –0.3V to 7V

Voltage Between Inputs Cn to Cn-1* .............................................. –0.3V to 9V C12 to C8 ............................................... –0.3V to 25V C8 to C4 ................................................. –0.3V to 25V C4 to V– ................................................. –0.3V to 25V

Operating Temperature Range LTC6801I .............................................–40°C to 85°C LTC6801H .......................................... –40°C to 125°C

Specified Temperature Range LTC6801I .............................................–40°C to 85°C LTC6801H .......................................... –40°C to 125°C

Junction Temperature ........................................... 150°CStorage Temperature Range .................. –65°C to 150°C

*n = 2 to 12

(Note 1)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TOP VIEW

G PACKAGE36-LEAD PLASTIC SSOP

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

V+

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

V–

VTEMP1

VTEMP2

VREF

VREG

OV1

OV0

UV1

UV0

HYST

CC1

CC0

SLT

SLTOK

DC

EOUT

EOUT

SIN

SIN

SOUT

SOUT

EIN

EIN

TJMAX = 150°C, θJA = 70°C/W

ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6801IG#PBF LTC6801IG#TRPBF LTC6801G 36-Lead Plastic SSOP –40°C to 85°C

LTC6801HG#PBF LTC6801HG#TRPBF LTC6801G 36-Lead Plastic SSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/


http://www.linear.com/leadfree/

http://www.linear.com/tapeandreel/

LTC6801

36801fc


ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Specifications

VERR Overvoltage (OV) or Undervoltage (UV) Detection Level Error

(Note 2) 2.106V ≤ VCELL ≤ 4.498V 2.106V ≤ VCELL ≤ 4.498V 1.531V ≤ VCELL < 2.106V 1.531V ≤ VCELL < 2.106V VCELL = 0.766V VCELL = 0.766V

l

l

l

–0.8 –1 –1

–1.3 –1.5 –2

0.8 1 1

1.3 1.5 2

% % % % % %

VS Supply Voltage, V+ Relative to V– VERR Specifications Met l 10 50 V

VCELL Cell Voltage Range Full Scale Voltage Range 5 V

VCM Common Mode Voltage Range Measured Relative to V–

VERR Specifications Met Range of Inputs Cn, n = 3 to 11 Range of Input C2 Range of Input C1

l

l

l

1.8 1.2 0

5 • n 10 5

V V V

VTV Temperature Input Detection Level Error (Relative to VREF/2)

10V < V+ < 50V l –13 17 mV

HYS UV/OV Detection Hysteresis Error (Relative to Selected Value)

10V < V+ < 50V l –25 25 %

VREF Reference Pin Voltage VREF Pin Loaded With 100k to V–

l

3.043 3.038

3.058 3.058

3.073 3.078

V V

Reference Voltage Temperature Coefficient 8 ppm/˚C

Reference Voltage Hysteresis 50 ppm

Reference Voltage Long Term Drift 60 ppm/√khr

VREG Regulator Pin Voltage 10V < VS < 50V, No Load LTC6801IG LTC6801HG 10V < VS < 50V, ILOAD = 4mA LTC6801IG LTC6801HG

l

l

l

l

4.5 4.5

4.1 4.1

5 5

4.8 4.8

5.5 5.7

V V

V V

Regulator Pin Short Circuit Current Limit l 5 9 mA

IB Input Bias Current In/Out of Pins C1 Thru C12 When Measuring Cells During Self Test When Measuring Cells When Idle

l

–10

100

1

10

µA µA nA

IM Supply Current, Monitor Mode Current Into the V+ Pin While Monitoring for UV and OV Conditions, FENA = 10kHz Continuous Monitoring Continuous Monitoring Monitor Every 130ms (Note 3) Monitor Every 500ms (Note 3)

l

l

l

600 500 110 50

750 750 200 100

1000 1100 320 160

µA µA µA µA

IQS Supply Current, Idle Current into the V+ Pin When Idle, FENA = 0 LTC6801IG LTC6801HG

l

l

23 20 23 20

30 30 30 30

42 45 42 48

µA µA µA µA

LTC6801 Timing Specifications

TCYCLE Measurement Cycle Time DC = CC1 = CC0 = VREG l 13 15.5 19 ms

FENA Valid EIN/EIN Frequency l 2 40 kHz

TENA Valid EIN/EIN Period = 1/ FENA l 25 500 µs

DCENA Valid EIN/EIN Duty Cycle FENA = 40kHz l 40 60 %


LTC6801

46801fc


ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 43.2V, V– = 0V unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LTC6801 Single Ended Digital I/O Specifications (SLT, SLTOK Pins)

VIH Digital Input Voltage High SLT Pin l 2 V

VIL Digital Input Voltage Low SLT Pin l 0.5 V

VODL Digital Output Voltage Low, Open Drain SLT Pin, 10k to VREG l 0.3 V

VOH Digital Output Voltage High SLTOK Pin, 10k to V– l VREG – 0.3 V

VOL Digital Output Voltage Low SLTOK Pin, 10k to VREG l 0.3 V

IPU-ST Pull-Up Current SLT Pin l 2.5 5 10 µA

LTC6801 Differential Digital Input Specifications (SIN/SIN, EIN/EIN Pins) (See Figure 1)

VIDH Minimum Differential Input Voltage High Differential Voltage Applied Between SIN and SIN or EIN and EIN

l 1.7 V

VIDL Minimum Differential Input Voltage Low l –1.7 V

VIL Valid Input Voltage Low Low Side of Differential Signal, Ref. to V– l 0 1.2 V

VIH Valid Input Voltage High High Side of Differential Signal, Ref. to V– l 2.5 6 V

VDHYS Differential Input Hysteresis 1 V

VOPEN Open Circuit Voltage l 2 2.5 3 V

RINCM Input Resistance, Common Mode l 100 150 kΩ

RINDIFF Input Resistance, Differential Between SIN to SIN, EIN to EIN l 200 300 kΩ

LTC6801 Differential Digital Output Specifications (SOUT/SOUT, EOUT/EOUT Pins)

VODH Digital Output Voltage High Output Pins Loaded With 100k to V– l VREG – 0.4 V

VODL Digital Output Voltage Low Output Pins Loaded With 100k to VREG l 0.4 V

LTC6801 Three-Level Digital Input Specifications (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins)

V3IH Three-Level Digital Input Voltage High l VREG – 0.3 V

V3IM Three-Level Digital Input Voltage Mid l VREF – 0.3 VREF + 0.3 V

V3IL Three-Level Digital Input Voltage Low l 0.3 V

IPU Pull-Up Current Pins DC, CC0, CC1, UV0 and UV1 l 0.5 1 2 µA

IPD Pull-Down Current Pins HYST, OV0 and OV1 l 0.5 1 2 µA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Figure 1. Differential Input Specifications6801 F01

V– = 0V

EIN

EIN

VIDH(VALID HIGH WHEN

EIN – EIN ≥ VIDH)MAX, VIH TENA

MIN, VIH

MAX, VIL

VIDL(VALID LOW WHEN EIN – EIN ≤ VIDL)

Note 2: VCELL refers to the voltage applied across the following pin combinations: Cn to Cn – 1 for n = 2 to 12, C1 to V–.Note 3: Guaranteed by continuous monitoring supply current specifications, not subject to test.


LTC6801

56801fc


V+ (V)10

I SUP

PLY

(µA)

800

620

780

740

700

660

760

720

680

640

600

6801 G01

605020 4030

DC PIN TIED TO VREGfENA = 10kHz

–40°C

25°C

85°C

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current, Monitor Mode Supply Current, Monitor Mode Supply Current, Idle Mode

Supply Current, Monitor Mode Supply Current, Monitor Mode Supply Current, Idle Mode

UV Detection Level Error 0V Detection Level Error Supply Current

V+ (V)10

I SUP

PLY

(µA)

250

200

150

100

50

0

6801 G02

605020 4030

CC1 = CC0 = VREGfENA = 10kHz

DC PIN = V–

DC PIN = VREF

85°C25°C–40°C

V+ (V)10

I SUP

PLY

(µA)

40

5

35

25

15

30

20

10

0

6801 G03

605020 4030

–40°C

25°C85°C

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

I SUP

PLY

(µA)

800

620

780

740

700

660

760

720

680

640

600

6801 G04

DC PIN TIED TO VREGfENA = 10kHz

V+ = 60V

V+ = 35V

V+ = 10V

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

I SUP

PLY

(µA)

250

200

150

100

50

0

6801 G05

CC1 = CC0 = VREGfENA = 10kHz

DC PIN = V–

DC PIN = VREF

V+ = 60VV+ = 35VV+ = 10V

40

5

35

25

15

30

20

10

0–40 20 95–10 50 110 1255 80–25 35 65

TEMPERATURE (°C)

I SUP

PLY

(µA)

6801 G06

V+ = 60V

V+ = 35V

V+ = 10V

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

ERRO

R (%

)

1.0

–0.8

0.8

0.4

0

–0.4

0.6

0.2

–0.2

–0.6

–1.0

6801 G07

V+ = 43.2VUV = 2.106V

5 TYPICAL UNITS

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

ERRO

R (%

)

1.0

–0.8

0.8

0.4

0

–0.4

0.6

0.2

–0.2

–0.6

–1.0

6801 G08

V+ = 43.2VOV = 4.116V

5 TYPICAL UNITS

1 10 100fENA (kHz)

I SUP

PLY

(µA)

800

620

780

740

700

660

760

720

680

640

600

6801 G09

V+ = 43.2VCONTINUOUS MEAS MODE

–40°C

25°C

85°C


LTC6801

66801fc


17.0

16.5

15.5

14.5

16.0

15.0

14.0–40 20 95–10 50 110 1255 80–25 35 65

TEMPERATURE (°C)

MEA

SURE

MEN

T CY

CLE

TIM

E (m

s)

6801 G11

V+ = 60V

V+ = 10V

CONTINUOUS MEAS MODECC1 = CC0 = VREG

EXTERNAL SERIES RESISTANCE, RS (kΩ)0

ERRO

R RE

LATI

VE T

O R S

= 0

(%)

4.0

0.5

3.5

2.5

1.5

3.0

2.0

1.0

0

6801 G10

1082 64

–40°C

RS IN SERIES WITH Cn AND Cn-110nF FROM Cn, Cn-1 TO V–

85°C

25°C


VREF Load Regulation

Cell Input Bias Current, Idle ModeCell Voltage Measurement Hysteresis VREF Line Regulation

UV/OV Detection Level Error Measurement Cycle TimeCell Input Bias Current when Measuring

VREF Output Voltage VREG Line Regulation

CELL VOLTAGE (V)0

SOUT

CLO

CK F

REQU

ENCY

(kHz

)

12

10

6

2

8

4

0

–2

6801 G14

541 32

UNDERVOLTAGEDETECTED

OVERVOLTAGE DETECTED

UV THRESHOLD = 2.106VOV THRESHOLD = 4.116VHYST = VREG

8.0

7.5

6.5

4.5

7.0

6.0

4.0

5.5

5.0

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

C PI

N BI

AS C

URRE

NT (µ

A)

6801 G12

CELL INPUT = 3.6V

50

40

20

30

10

–10

0

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

C PI

N BI

AS C

URRE

NT (n

A)

6801 G13

CELL INPUT = 3.6V

C2 TO C11VTEMP1, VTEMP2

C12

C1

V+ (V)10

V REF

(V)

3.070

3.065

3.060

3.055

3.050

6801 G15

605020 4030

NO LOAD

–40°C

85°C

25°C

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

V REF

(V)

3.070

3.065

3.060

3.055

3.050

6801 G16

NO LOAD

5 TYPICAL UNITS

V+ (V)10

V REG

(V)

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

6801 G17

605020 4030

IDLE MODENO LOAD

–40°C

25°C

85°C

0 100 200 30050 150 250ILOAD (µA)

V REF

(V)

3.070

3.065

3.060

3.055

3.050

6801 G20

–40°C

85°C25°C


LTC6801

76801fc


Status Output Operating at 10kHzUV/OV Detection Level Thermal Hysteresis

UV/OV Detection Level Thermal Hysteresis

VREG Load Regulation VREG Output Voltage


VREG Line Regulation

6801 G22

2V/DIV

20µs/DIV

100k LOAD TO V–

SOUT

SOUT

V+ (V)10

V REG

(V)

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

6801 G18

605020 4030

IDLE MODE4mA LOAD TO V–

–40°C

25°C

85°C

0 1082 64ILOAD (mA)

V REG

(V)

5.5

5.0

4.5

4.0

6801 G19

IDLE MODE

V+ = 60VV+ = 10V

85°C25°C–40°C

–40 20 95–10 50 110 1255 80–25 35 65TEMPERATURE (°C)

V REG

(V)

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

6801 G21

IDLE MODE

NO LOAD

4mA LOAD

V+ = 60VV+ = 35VV+ = 10V

–100 150–50 50 2000 100CHANGE IN DETECTION LEVEL (ppm)

NUM

BER

OF U

NITS

16

14

12

10

8

6

4

2

0

6801 G23

TA = 85°C TO 25°C

–100 150–50 50 2000 100CHANGE IN DETECTION LEVEL (ppm)

NUM

BER

OF U

NITS

20

18

16

14

12

10

8

6

4

2

0

6801 G24

TA = –40°C TO 25°C


LTC6801

86801fc


PIN FUNCTIONSV+ (Pin 1): Supply Voltage. Tied to the most positive po-tential in the battery stack. For example, the same potential as C12 when measuring a stack of 12 cells, or the same potential as C7 when measuring a stack of 7 cells.

C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs. Up to 12 cells can be monitored. The lowest potential is tied to V–. The next lowest potential is tied to C1 and so forth. Due to internal overvoltage protection, each C input must be tied to a potential equal to or greater than the next lower numbered C input. See the figures in the Applications Information section for more details on connecting batteries to the LTC6801. See Electrical Characteristics table for voltage range and input bias current requirements.

V– (Pin 14): Tied to the most negative cell potential (bottom of monitored cell stack).

VTEMP1, VTEMP2 (Pin 15, Pin 16): Temperature Sensor Inputs. The ADC will measure the voltages on VTEMP1 and VTEMP2 relative to V–. The ADC measurements are referenced to the VREF pin voltage. Therefore a simple thermistor and resistor combination connected to the VREF pin can be used to monitor temperature. These pins have a fixed undervoltage threshold equal to one half VREF. A filtering capacitor to V– is recommended. Temperature sensor input pins may be tied to VREF to disable.

VREF (Pin 17): Reference Output, Nominally 3.058V. Re-quires a 1µF bypass capacitor to V–. The VREF pin can drive a 100k resistive load connected to V–. VREF must be buffered with an LT6003 amplifier, or similar device to drive heavier loads. VREF becomes high impedance when the IC is disabled or idle between monitoring events.

VREG (Pin 18): Regulator Output, Nominally 5V. Requires a 1µF bypass capacitor to V–. The VREG pin is capable of supplying up to 4mA to an external load and is continually enabled.

EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A clock signal greater than 2kHz will enable the LTC6801. For operation with a single-ended enable signal (up to 10kHz), drive EIN and connect a 1nF capacitor from EIN to V–.

SOUT, SOUT (Pin 21, Pin 22): Differential Status Output. Swings V– to VREG. This output will toggle at the same frequency as EIN/EIN when a valid signal is detected at SIN/SIN and the battery stack being monitored is within specified parameters, otherwise SOUT is low and SOUT high.

SIN, SIN (Pin 23, Pin 24): Differential status input from the IC above. To indicate that the stack is good, SIN must be the same frequency and phase as EIN. See applications circuits for interfacing SIN to the SOUT above.

EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of EIN/EIN. Swings V– to VREG. Must be capacitively coupled to the EIN/EIN inputs of the next higher voltage LTC6801 in a stack, or looped to SIN/SIN of the same chip (pins 23, 24).

DC (Pin 27): Duty Cycle Three-Level Input. This pin may be tied to VREG, VREF or V–. The DC pin selects the duty cycle of the monitoring function and has an internal pull-up to VREG. See Table 3.

SLTOK (Pin 28): Self Test Logic Output. SLTOK is held HIGH (VREG voltage) upon reset or successful completion of a self test cycle. A LOW output level (V– voltage) indicates the last self test cycle failed.

SLT (Pin 29): Self Test Open Collector Input/Output. SLT initiates a self test cycle when it is pulled low externally. When a high to low transition is detected, the next scheduled measurement cycle will be a self test cycle. SLT indicates a self test cycle is in progress when pulled low internally. A self test is automatically initiated after 1024 measurement cycles. This pin has an internal pull-up to VREG.

CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs. These pins may be tied to VREG, VREF or V–. CC1 and CC0 select the number of cells attached to the device and each pin has an internal pull-up to VREG. See Table 5.

HYST (Pin 32): Hysteresis Three-Level Input. This pin may be tied to VREG, VREF or V–. HYST selects the amount of hysteresis applied to the undervoltage and overvoltage threshold settings and has an internal pull-down to V–. See Table 4.


LTC6801

96801fc


PIN FUNCTIONSUV0, UV1 (Pin 33, Pin 34): Undervoltage Three-Level Inputs. These pins may be tied to VREG, VREF or V–. UV1 and UV0 select the undervoltage threshold and each pin has an internal pull-up to VREG. See Table 2.

OV0, OV1 (Pin 35, Pin 36): Overvoltage Three-Level Inputs. These pins may be tied to VREG, VREF or V–. OV1 and OV0 select the overvoltage threshold and each pin has an internal pull-down to V–. See Table 1.

Table 1. Overvoltage InputsOV1 OV0 OVERVOLTAGE THRESHOLD (V)

VREG VREG 4.498

VREG VREF 4.403

VREG V– 4.307

VREF VREG 4.211

VREF VREF 4.116

VREF V– 4.020

V– VREG 3.924

V– VREF 3.828

V– V– 3.733

Table 2. Undervoltage InputsUV1 UV0 UNDERVOLTAGE THRESHOLD (V)

VREG VREG 2.871

VREG VREF 2.680

VREG V– 2.489

VREF VREG 2.297

VREF VREF 2.106

VREF V– 1.914

V– VREG 1.723

V– VREF 1.531

V– V– 0.766

Table 3. Duty Cycle SelectDC NOMINAL CYCLE TIME*

VREG 15.5ms

VREF Approximately 130ms

V– Approximately 500ms

*Cycle time based on LTC6801 measuring 12 cells and 2 temperatures.

Table 4. Hysteresis SelectHYST UV HYSTERESIS* OV HYSTERESIS

VREG 500mV 200mV

VREF 250mV 100mV

V– 0mV 0mV

*UV hysteresis is disabled when the undervoltage threshold is set to 0.766V.

Table 5. Cell Count SelectCC1 CC0 CELL COUNT

VREG VREG 12

VREG VREF 11

VREG V– 10

VREF VREG 9

VREF VREF 8

VREF V– 7

V– VREG 6

V– VREF 5

V– V– 4


LTC6801

106801fc


BLOCK DIAGRAM

6801 BD

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

V+REGULATOR

DIGITALCOMPARATORS

SELF TESTREFERENCE

(REF2)

REFERENCE

12

+

–

–

+

+–

+–

V–

MUX

VREG

VTEMP1 VTEMP2 VREF OV0 OV1 UV0 UV1

HYST

CC1

CC0

DC

SLT

SLTOK

EIN

EIN

EOUT

EOUT

SIN

SIN

SOUT

SOUT

DECODER

UV/OV FLAGS ANDCONTROL

LOGIC

“GOOD”

ADC

The LTC6801 measures between 4 and 12 cell voltages and 2 temperature inputs. If all measurements are within an acceptable window, the LTC6801 will produce a dif-

ferential clock output signal (SOUT, SOUT). If any of the channels exceed user set upper and lower thresholds, a logic low signal is produced at SOUT.


LTC6801

116801fc


BLOCK DIAGRAM OF ENABLE IN/OUT AND STATUS IN/OUT

THE FREQUENCY MATCH DETECT OUTPUT GOES

HIGH WHEN SIN AND EIN ARE THE SAME FREQUENCY

SOUT IS ACTIVE WHEN1) EIN IS ACTIVE2) SIN AND EIN ARE THE SAME FREQUENCY3) ALL READINGS ARE “GOOD”

THE SIGNAL IS HIGH WHEN

ALL READINGS ARE “GOOD”

THE CLK DETECTOUTPUT GOES

HIGH WHEN EIN IS 2kHz TO 40kHz

6801 BDa

VREG

VREG

–

+

VREG

VREG

FREQUENCYMATCHDETECT

CLKDETECT

–

+

EOUT

SIN300k

300k

300k

300k

300k

300k

300k

300k

EIN

SOUT

EIN

SIN

SOUT

EOUT


LTC6801

126801fc


OVERVIEW

The LTC6801 is designed as an easy to implement, low-cost battery stack monitor that provides a simple indica-tion of correct battery stack operation without requiring a microcontroller interface. For battery stack monitoring with cell voltage read back and discharge circuitry, refer to the LTC6802 battery stack monitor data sheet.

The LTC6801 contains a 12-bit ADC, a precision voltage reference, sampled comparator, high voltage multiplexer and timer/sequencer. During normal operation, the se-quencer multiplexes the ADC inputs between each of the channel input pins in turn, performing a single comparison to the undervoltage and overvoltage thresholds. The VTEMP inputs are also monitored for an undervoltage at a fixed threshold of VREF/2.

The presence of a status output clock indicates the system is “OK”. Because the status output is dynamic, it cannot get stuck in the “OK” state.

STACKED OPERATION

Each LTC6801 monitors a group of up to 12 series con-nected cells. Groups of cells can be connected in series or parallel to form a large battery pack. The LTC6801s can be daisy chained with simple capacitive or transformer coupling. This allows every cell in a large battery pack to be monitored with a single signal. Figure 2 illustrates monitoring of 36 series connected cells.

To cancel systematic duty cycle distortion through the clock buffers, it is recommended that the clock lines are cross-coupled (EOUT goes to EIN etc.) as they route up and down the stack as shown in Figure 2.

APPLICATIONS INFORMATIONINDEPENDENT OPERATION

Figure 3 shows how three groups of 12 cells can be mon-itored independently.

REGULATED OUTPUTS

A regulated voltage is provided at the VREG pin, biased from the battery stack. The VREG pin can supply up to 4mA at 5V and may be used to power small external circuits. The regulated output remains at 5V continually, as long as the total stack voltage is between 10V and 50V.

A low current, precision reference voltage is provided at the VREF pin, which can drive loads of greater than 100k. The VREF output is high impedance when the LTC6801 is idle.

Both the VREG and VREF pins must be bypassed to V– with a 1µF capacitor.

CONTROL INPUTS

The LTC6801 thresholds are controlled by the UV1, UV0, OV1 and OV0 pins. These pins are designed to be tied directly to VREG, VREF or V– in order to set the comparison thresholds for all channels simultaneously. The pins are not designed to be variable. In particular, changes made to the pins while the chip is not in idle mode may result in unpredictable behavior. See Tables 1 and 2 for setting and threshold information.


LTC6801

136801fc


APPLICATIONS INFORMATIONENABLE INPUTS

In order to support stacked operation, the LTC6801 is enabled through a differential signal chain encompassing the EIN/EIN, EOUT/EOUT, and SIN/SIN pins.

The LTC6801 will be enabled if a differential square wave with a frequency between 2kHz and 40kHz is applied at EIN/EIN. Otherwise, the LTC6801 will default to a low power idle mode.

If the differential signal at SIN/SIN is not equal in frequency to the differential signal output at EOUT/EOUT, the LTC6801 will be enabled but SOUT will be held at 0V and SOUT will be held at VREG.

For the simplest operation in a single chip configuration, EOUT should be connected directly to SIN and EOUT should be connected directly to SIN, and a square wave with a frequency between 2kHz and 40kHz should be applied differentially to EIN and EIN. For enable clock frequencies up to 10kHz, a single-ended square wave with a 5V swing may be used at EIN while a 1nF capacitor is connected from EIN to V–.

STATUS OUTPUT

If the chip is properly enabled (EIN/EIN, SIN/SIN are the same frequency), all cells are within the undervoltage and overvoltage thresholds, and the voltage at VTEMP1 and VTEMP2 is over one half VREF, the differential output at SOUT/SOUT will toggle at the same frequency and in phase with the signal at EIN/EIN. Otherwise, SOUT will be low and SOUT will be high.

The maximum delay between when a bad cell voltage occurs and when it is detected depends on the measure-ment duty cycle setting. The SOUT clock turns on or off at the end of each measurement cycle. Figure 4 shows the maximum detection delay in continuous monitor mode (DC pin tied to VREG).

FAULT PROTECTION

Overview

Care should always be taken when using high energy sources such as batteries. There are countless ways that systems can be [mis-]configured during the assembly and service procedures that can impact a battery’s long term performance. Table 6 shows various situations to consider when planning protection circuitry.

Battery Interconnection Integrity

Please note: The last condition shown in the FMEA table could cause catastrophic IC failures. In this case, the battery string integrity is lost within a cell group monitored by an LTC6801. This condition could place excessive stress on certain cell input signal clamp-diodes and probably lead to IC failure. If this scenario seems at all likely in a particular application, series fuses and parallel Schottky diodes should be connected as shown in Figure 5 to limit stress on the IC inputs. The diodes used in this situation need current ratings sufficient to open the protective fuse in the battery tap signal.


LTC6801

146801fc


APPLICATIONS INFORMATION

Figure 2. Serial Connection of Status Lines for Multiple 6801s on the Same PCB (Simplified Schematic, Not All Components Shown)

TOP OFSTACK

BOTTOMOF STACK

CLOCK OUT WHEN ALLCELLS GOOD

USER SUPPLIEDCLOCK IN

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F02

V+

C12C11C10C9C8C7C6C5C4C3C2C1

V–

VTEMP1VTEMP2

VREFVREG

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801V+


V–

VTEMP1VTEMP2

VREFVREG

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801V+


V–

VTEMP1

VTEMP2

VREFVREG

Figure 3. Independent Status Lines for Multiple 6801s on the Same PCB (Simplified Schematic, Not All Components Shown)

TOP OFSTACK

BOTTOMOF STACK

ALL CLOCKS OUT WHEN ALL CELLS GOOD

PROGRAMMED CONDITIONS:CONTINUOUS MONITOR MODEOV = 4.116VUV = 2.106VHYST = 250mV (UV), 100mV (OV)CC = 12

USER SUPPLIEDCLOCK IN

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F03

V+


V–

VTEMP1VTEMP2

VREFVREG

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801V+


V–

VTEMP1VTEMP2

VREFVREG

OV1

OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801V+


V–

VTEMP1

VTEMP2

VREFVREG


LTC6801

156801fc



Figu

re 4

. Cel

l UV/

OV D

etec

tion

Dela

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Con

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us M

onito

r Mod

e

C1C2

C3C4

C5C6

C7

COM

PLET

E M

EASU

REM

ENT

CYCL

E 15

.4 m

s(~

1.1m

s PE

R CE

LL)

SOUT

STA

TUS

UPDA

TED

C8C9

C10

C11

C12

T1T2

C1C2

6801

F04

C3C4

C5C6

C7C8

C9C1

0C1

1C1

2T1

T2C1

C2C3

WOR

ST C

ASE

ERRO

R DE

TECT

ION

DELA

Y ~2

9.7m

s

NOTE

: SOU

T IS

NOT

TO

SCAL

ESE

E EL

ECTR

ICAL

TAB

LE F

OR M

IN/M

AX S

PECI

FICA

TION

S

ALL

CELL

SGO

ODEX

AMPL

ES

SOUT

SOUT

REM

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ACTI

VE

(SIN

CE N

OTHI

NGAB

NORM

AL H

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EN D

ETEC

TED

YET)

LTC6

801

READ

SA

BAD

VOLT

AGE

ON C

ELL

1

SOUT

STO

PSAT

END

OF

MEA

SURE

MEN

TCY

CLE

CELL

1 G

OES

BAD

IMM

EDIA

TELY

AFTE

R IT

IS R

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SOUT

STA

TUS

UPDA

TED


LTC6801

166801fc


Table 6. Failure Mechanism Effect Analysis (FMEA)SCENARIO EFFECT DESIGN MITIGATION

Cell input open-circuit (random) Power-up sequence at IC inputs Clamp diodes at each pin to V+ & V– (within IC) provide alternate PowerPath.

Cell input open-circuit (random) Differential input voltage overstress Zener diodes across each cell voltage input pair (within IC) limit stress.

Top cell input connection loss (V+) Power will come from highest connected cell input

Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT).

Bottom cell input connection loss (V–) Power will come from lowest connected cell input Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT).

Power input disconnection (amongst stacked units)

Loss of supply connections Clamp diodes at each pin to V+ and V– (within IC) provide alternate PowerPath. Error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT).

Status link disconnection (between stacked units)

Break of “daisy chain” communication (no stress to ICs)

Daisy chain will be broken and error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT).

Short between any two configuration inputs Power supplies connected to pins will be shorted If VREF or VREG is shorted to V–, supply will be removed from internal circuitry and error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT). If VREF is shorted to VREG, a self test error will be flagged.

Open connection on configuration input Control input will be pulled towards positive or negative potential depending on pin

Control input will be pulled to a more stringent condition (larger number of channels, higher UV threshold, lower OV threshold, shorter duty cycle, etc. ensuring either more stringent monitoring or error condition will be indicated by all upstream and downstream units (no clock on SOUT/ SOUT).

Cell-pack integrity, break between stacked units Daisy-chain voltage reversal up to full stack potential

Full stack potential may appear across status/enable isolation devices, but will not be seen by the IC. isolation capacitors should therefore be rated to withstand the full stack potential.

Cell-pack integrity, break within stacked unit Cell input reverse overstress Add battery tap fuses and Schottky diodes in parallel with the cell inputs to limit stress on IC. Diode and connections must handle current sufficient to open fuse



LTC6801

176801fc


6801 F06

LTC6801

SLT

HYST

UV0

CC1

CC0

SLTOK

DC

C1

C2

C3

C4

C5

C6

C7

OV0

VREF

VTEMP2

VREG

OV1

UV1

EIN

SOUT

SOUT

EIN

VTEMP1

EOUT

EOUT

SIN

SIN

C8

C9

C10

C11

C12

V+

ZCLAMP

ZCLAMP

ZCLAMP

V–


Figure 5. Using Fuses and Diodes for Cell Input Protection (One Cell Connection Shown)

6801 F05

PROTECTAGAINSTBREAKS

HERE

Cn

Cn – 1

Internal Protection Structure

The LTC6801 incorporates a number of protective struc-tures, including parasitic diodes, Zener-like overvoltage suppressors, and other internal features that provide protection against ESD and certain overstress conditions that could arise in practice. Figure 6 shows a simplified internal schematic that indicates the significant protective structures and their connectivity. The various diodes indi-cate the approximate current versus voltage characteristics that are intrinsic to the part, which is useful in analyzing responses to certain external stresses, such as during a hot-start scenario.

SELF TEST CIRCUITRY

The LTC6801 has internal circuitry that performs a periodic self test of all measurement functions. The LTC6801 self test circuitry is intended to prevent undetectable failure modes. Accuracy and functionality of the voltage reference and comparator are verified, as well as functionality of the high voltage multiplexer and ADC decimation filter. Additionally, open connections on the cell input pins C1 to C11 are detected (Open connections on V– or C12/V+ will cause an undervoltage failure during the normal measurement cycle).

Figure 6. Internal Protection Structures


LTC6801

186801fc


Self Test Pins

The SLT pin is used to initiate a self test. It is configured as an open collector input/output. The pin should be nor-mally tied to VREG with a resistor greater than or equal to 100k or floated. The pin may be pulled low at any time to initiate a self test cycle.

The device will automatically initiate a self test if SLT has not been externally activated for 1024 measurement cycles, and pull down the SLT pin internally to indicate that it is in self test mode.

The SLTOK pin is a simple logic output. If the previous self test failed the output is held low, otherwise the output will be high. The SLTOK pin is high upon power-up. The SLTOK output can be connected to a microcontroller through an isolation path.

The LTC6801 status output will remain active while the SLTOK pin is low. The LTC6801 will continue to monitor cells if the self test fails. If the next self test passes, the SLTOK output returns high.

Reference and Comparator Verification

A secondary internal bandgap voltage reference (REF2) is included in the LTC6801 to aid in verification of the reference and comparator. During the self test cycle, the comparator and main reference are used to measure the REF2 voltage.

To verify the comparator functionality, the upper and lower thresholds are first set in a close window around the expected REF2 voltage and the comparator output is verified. Then the upper threshold is set below the REF2 voltage and the comparator output is verified again. Lastly, the lower threshold is set above the REF2 voltage and the comparator output is verified a third time.

The self test guarantees that VREF is within 5% of the specified nominal value. Also, this test guarantees the analog portion of the ADC is working.

High Voltage Multiplexer Verification

The most dangerous failure mode of the high voltage multiplexer would be a stuck bit condition in the address decoder. Such a fault would cause some channels to be measured repeatedly while other channels are skipped. A skipped channel could mean a bad cell reading is not detectable. Other multiplexer failures, like the simultaneous selection of multiple channels, or shorts in the signal path, would result in an undervoltage or overvoltage condition on at least one of the channels.

The LTC6801 incorporates circuitry to ensure that all requested channels are measured during each measurement cycle and none are skipped. If a channel is skipped, an error is flagged during the self test cycle.

ADC Decimation Filter Verification

The ADC decimation filter test verifies that the digital cir-cuits in the ADC are working, i.e. there are no stuck bits in the ADC output register. During each self test cycle, the LTC6801 feeds two test waveforms into the ADC. The internally generated waveforms were designed to generate complementary zebra patterns (alternating 0’s and 1’s) at the ADC output. If either of the waveforms generates an incorrect output value, an error is flagged during the self test cycle.

Open Cell Connection Detection

The open connection detection algorithm ensures that an open circuit is not misinterpreted as a valid cell reading.



LTC6801

196801fc


APPLICATIONS INFORMATIONIn the absence of external noise filtering, the input resis-tance of the ADC will cause open wires to produce a near zero reading. This reading will cause an undervoltage failure during the normal measurement cycle.

Some applications may include external noise filtering to improve the quality of the voltage comparisons. When an RC network is used to filter noise, an open wire may not produce a zero reading because the comparator input resistance is too large to discharge the capacitors on the input pin. Charge may build up on the open pin during successive measurement cycles to the extent that it could indicate a valid cell voltage reading.

During each self test cycle, the LTC6801 will sink 100µA to V– from each side of the cell being measured. The undervoltage threshold is not checked during the self test because the 100µA pull-down current would cause false failures in some cases. If an input is open, this current will discharge any filtering capacitors and cause the input to float down to approximately 0.7V below the next lower cell input. In most cases, the cell voltage of the cell above the open input will exceed the overvoltage threshold and flag a self test error. During the normal measurement cycle, the LTC6801 will sink 1µA to V– from each side of the cell being measured. If the cell voltages are low enough that an open wire is not detected as an overvoltage during

self test, this current will cause the cell input to settle to a voltage low enough to trigger an undervoltage condition during the normal measurement cycle.

Note, an open cell connection may not be detected when the UV = 0.766V setting is used. For all other UV settings, an open cell connection will result in either a self test error or no SOUT clock.

Using The LTC6801 with Other Battery Monitors

When used in combination with an LTC6802-1, it is possible to check the LTC6801 self test result via the LTC6802-1 and its isolated SPI. As shown in Figure 7, the SLTOK output is tied to the GPIO2 pin on the LTC6802-1. SLTOK will remain high as long as it is passing the self test. A self test will occur automatically every 1024 measurement cycles (17 seconds to 9 minutes, depending on measurement duty cycle). A self test can be initiated by a falling edge on SLT, via the LTC6802-1 GPIO1 line. A self test will start after the current measurement cycle is complete, and the SLTOK status will be valid when the self test completes. The worst case delay before SLTOK is valid in continuous monitor mode is approximately 15ms for the current cycle to complete plus 17ms for the self test to complete.

The 6802-1 can measure the LTC6801 reference, which will independently test the analog circuitry of the LTC6802.

Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test.

CSBOSDOISCKOV+C12S12C11S11C10S10C9S9C8S8C7S7C6S6C5S5C4S4

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3C2C1

CSBISDOSDI

SCKIVMODEGPIO2GPIO1WDTBMMBTOS

VREGVREF

VTEMP2VTEMP1

NCV–S1C1S2C2S3C3

LTC6802-1

6801 F07

V+C12C11C10C9C8C7C6C5C4C3C2C1V–VTEMP1VTEMP2VREFVREG


OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

IN

OUT

1µF

1M

1µF

100k

VREF

CMPD6263


LTC6801

206801fc


2.2k

10kNTC

B = 3380

10kNTCB = 3380

2.2k

0.5µF


OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F10

0.5µF

+

–

LT6003

APPLICATIONS INFORMATIONCELL-VOLTAGE FILTERING

The LTC6801 employs a sampling system to perform its analog-to-digital conversions and provides a conversion result that is essentially an average over the 0.5ms conver-sion window. If there is significant noise at frequencies near 500kHz there may be aliasing in the delta-sigma modulator. A lowpass filter with 30dB attenuation at 500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not be lower than this to assure accurate conversions.

Series resistors of 1k may be inserted in the input paths without introducing measurement error. Shunt capacitors may be added from the cell inputs to V–, creating RC filter-ing as shown in Figure 8. The combination of 1k and 10nF is recommended as a robust, cost effective noise filter.

MEASURING VARIOUS CELL COUNTS

The LTC6801 is designed to measure up to 12 cells de-pending on the state of the CC pins (See Table 5). When using an LTC6801 configured for measuring less than 12 cells, for instance choosing to measure 8 cells by

Figure 10. Buffering VREF for Higher-Current Sensors. Two Independent Probes With a +70°C Trip Point

Figure 9. Driving Thermistors Directly from VREF. Two Independent Probes With a +60°C Trip Point

100k

500kNTC

B = 4567

500kNTCB = 4567

100k

1µF


OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F09

1µF

Figure 8. Adding RC Filtering to the Cell inputs

6801 F08

V–

C1

C2

C31k

10nF1k

10nF1k

10nF

tying both CC1 and CC0 to the VREF pin, the highest cell potential (in this case C8) must be connected to the V+

pin for proper operation. Unused cell connection pins (in this case C9 to C12) may be left floating or may also be tied to the highest cell potential.


LTC6801

216801fc


READING EXTERNAL TEMPERATURE PROBES

The LTC6801 includes two channels of ADC input, VTEMP1 and VTEMP2, that are intended to monitor thermistors (tempco about –4%/°C generally) or diodes (–2.2mV/°C typical) located within the cell array. Sensors can be powered directly from VREF as shown in Figure 9 (up to 30µA typical).

The temperature measurement inputs (VTEMP1, VTEMP2) of the LTC6801 are comparator input channels with a voltage threshold of one-half VREF. Input voltages above half VREF are considered good. Voltages below the one-half VREF threshold are considered a fault condition. The inputs may be used in combination with resistors, thermistors, or diodes to sense both an upper and lower temperature limit. Figure 9, Figure 10 and Figure 11 illustrate some possibilities. To ignore these inputs simply connect VTEMP1 and VTEMP2 to VREF. A filtering capacitor to V– is recom-mended to minimize the error caused by the approximately 700k input impedance of the ADC.

For sensors that require higher drive currents, a buffer amplifier may be used as shown in Figure 10. Power for the sensor is actually sourced indirectly from the VREG pin in this case. Probe loads up to about 1mA maximum are supported in this configuration. Since VREF is shut down while the LTC6801 is idle between measurement cycles, the thermistor drive is also shut off and thus power dis-sipation is minimized. Since VREG remains always-on, the buffer op amp (LT6003 shown) is selected for its ultralow current consumption (10µA).

For circuits that include filtering capacitance, note that only the fastest DC setting (VREG connection) will keep VREF steady and allow the VTEMP voltages to settle. To use the lower power DC settings, VREF must be buffered (see Figure 10), so that a low impedance is presented to the ADC, with a time constant of no more than about 1ms.

ADVANTAGES OF DELTA-SIGMA ADCs

The LTC6801 employs a delta-sigma analog to digital converter for voltage measurement. The architecture of delta-sigma converters can vary considerably, but the common characteristic is that the input is sampled many times over the course of a conversion and then filtered or averaged to produce the digital output code.

Figure 11. Sensing Both Upper and Lower Temperature Thresholds. This Example Monitors a –20°C to +60°C Window Detector. The Thermistors Should Be in Close Proximity

100k

500kNTC

B = 4567

100kNTCB = 4250

1150k1µF


OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F11

1µF



LTC6801

226801fc


For a given sample rate, a delta-sigma converter can achieve excellent noise rejection while settling completely in a single conversion. This is particularly important for noisy automotive systems. Other advantages of delta-sigma converters are that they are inherently monotonic, meaning they have no missing codes, and they have excellent DC specifications.

The LTC6801’s ADC has a second order delta-sigma modulator followed by a SINC2, finite impulse response (FIR) digital filter, with a lowpass bandwidth of 1kHz. The front-end sample rate is 512ksps, which greatly reduces input filtering requirements. A simple 16kHz, 1 pole filter composed of a 1k resistor and a 10nF capacitor at each input will provide adequate filtering for most applications. These component values will not degrade the DC accuracy of the ADC.

Each conversion consists of two phases – an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greatly improving CMRR.

USING TRANSFORMERS FOR GALVANIC ISOLATION

As shown in Figure 12, small gate-drive signal transform-ers can be used to interconnect devices and transport the enable and sense signals safely across an isolation barrier. Driving a transformer with a squarewave requires transient currents of several mA and frequency of operation at 20kHz or higher. Since the output pins of the LTC6801 are current limited at <1mA, a small external gate pair (NC7WZ17 dual buffer) is used to provide the needed drive current. 330Ω resistors are placed in series with each buffer output to optimize current flow into the transformer primary and a coupling capacitor provides prevention of current flow in static conditions. The secondary side is wired in a cen-ter-tapped configuration to terminate the common mode voltage and thus suppress noise pickup. The differential signal is terminated into 1500Ω to optimize the peak signal swing for the IC input (to about ±4VP-P). Internal biasing features of the IC inputs maintain an optimal DC common mode level at the transformer secondary.

INTERCOMMUNICATION USING DATA ISOLATORS

As shown in Figure 13, an inexpensive and compact 2-channel data isolator is used to communicate the enable and the sense clocking signals between devices. The wiring carries isolator power and return plus two single-ended logic signals that are completely isolated at the upper device interface, so the signals are effectively differential from a common mode ingress perspective. The isolator provides excellent rejection of noise between battery groups, but consumes a few mA when operating, so a conventional opto-coupler and a few discretes provide a power-down scheme for periods where no monitoring is needed. Since the required current would load down VREG if used directly, the NPN transistor is used to form a quasi-regulated 4.3V supply drawing from the full battery group potential, also moving significant thermal loading outside the IC. The PMOS FET is a low resistance switch controlled by the opto-coupler output. Since the opto-coupler is used to switch only a small current, the LED need only be driven with ~500µA. Powering down the bottom-of-stack isolator on the host µP side automatically powers down the entire isolator chain.

DEMO BOARD CIRCUIT

An LTC6801 demonstration circuit is shown in Figure 14. The circuit includes a 10kHz oscillator (U2) for the enable excitation and an LED (D15, driven by Q1) to indicate the state of the status outputs, plus an assortment of important protection components to ensure robust operation and hot-plugging of cell connections.

Series resistors (R14 to R21) provide a controlled coupling capacitor (C14 to C17) current in the inter-IC connections during startup or other abrupt potential changes, and as-sociated clamp diodes (D13 and D14 quad array devices) redirect charge/surge current around the IC.

Input filters to each cell (R1, C1 to R12, C12) also use 6.2V Zener diodes (D1 to D12) to prevent overstress to the internal ESD clamps.

The V+ input filter (R13, C13) has the same time constant as the ADC input filters so that the V+ and C12 pins tend to track during start-up or transients, minimizing stress and ADC error.



LTC6801

236801fc


Figure 12. Using Transformers for Galvanic Isolation


OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

V+

C12C11C10C9

V+

NC7WZ17P0544NL

P0544NL

GND

C8C7C6C5C4C3C2C1V–

VTEMP1VTEMP2VREFVREG

10nF

10nF

330Ω

330Ω

V+

NC7WZ17

GND

330Ω

330Ω

ENC2+

ENC2–

S2+

S2–1.5k

6801 F12

S_HOST+

EN_HOST–

S_HOST–

EN_HOST+

•

•

•

1µF

100nF

100nF

1.5k

TO NEXTCIRCUIT

OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

V+

C12C11C10C9

P0544NL

C8C7C6C5C4C3C2C1V–


10nF

V+

NC7WZ17

GND

330Ω

330Ω

ENC1+

ENC1–

S1+

S1–1.5k

•

•

•

1µF

100nF

•

•

•


LTC6801

246801fc


Figure 13. IC to IC Communication Using Data Isolators

TO NEXTCIRCUIT

OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

V+

C12C11C10C9

VDD2

B1

B2GND2

Si8421

MOC207-M

SI2351DS

VDD1

A1

A2GND1

C8C7C6C5C4C3C2C1

1µF

1nF

CZT5551

1nF1µF

V–


1µF

100Ω

33k

100Ω

6.8k

COM2ENABLE2SENSE2VISO2

OV1OV0UV1UV0

HYSTCC1CC0SLT

SLTOKDC

EOUTEOUT

SINSIN

SOUTSOUT

EINEIN

LTC6801

6801 F13

V+

C12C11C10C9

VDD2

B1

B2GND2 COMHOST

ENABLEHOST

SENSEHOST

VCCHOST

Si8421

MOC207-M

SI2351DS

VDD1

A1

A2GND1

C8C7C6C5C4C3C2C1

1µF

1nF

CZT5551

1nF1µF

V–


1µF

100Ω

33k

100Ω

6.8k

COM1ENABLE1SENSE1VISO1



LTC6801

256801fc



1 3 5

SE DIFF

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1C1

91µ

F50

V

C18

1µF

50V

C21

1nF

100V

R26

1.15

MR2

510

0kNT

C

C20

1nF

100V

R23

22.6

k

R24

100k

NTC

R22

1.5k

1%R2

710

k1%

D15

LED1

(GRN

)

C22

10nF

50V

P1ED

GE F

INGE

R

J1HE

ADER

C1 10nF

100V

C2 10nF

100V

D1 T

O D1

2: B

ZT52

C6V2

8

C3 10nF

100V

D1R1 1kD2R2 1kD3

1

1

1

3

2

2

R3 1k

C4 10nF

100V

D4R4 1k

C5 10nF

100V

D5R5 1k

C6 10nF

100V

D6R6 1k

C7 10nF

100V

D7R7 1k

C8 10nF

100V

D8R8 1k

C9 10nF

100V

D9R9 1k

C10

10nF

100V

D10

R10

1k

C11

10nF

100V

D11

R11

1k

C12

10nF

100V

D12

R12

1k

1 3 5

1 2 3

2 4 6

6 5 4

OUT

GND

DIV

V+

GRD

SET

1 3 5

ON OFF

1 3 5

2 4 6

LTC6

801

1 3 5

2 4 6

1 3 5 7 9 11 13

2 4 6 8 10 12 14

V REF

JP8

DCJP

7CC

0JP

6CC

1JP

5HY

STJP

4UV

0JP

3UV

1JP

2OV

0JP

1OV

1

LTC6

801I

G

E1

V REG

GND

NOTE

: IF

THE

DC P

IN IS

TIE

D TO

VRE

F OR

V– ,

V TEM

P1 A

ND V

TEM

P2 W

ILL

HAVE

ADD

ITIO

NAL

MEA

SURE

MEN

T ER

ROR

DUE

TO IN

SUFF

ICIE

NTSE

TTLI

NG (S

EE R

EADI

NG E

XTER

NAL

TEM

PERA

TURE

PRO

BES)

V–

E2

SLT

E3SLTO

K

JP12

OSC

JP10

EINX

JP11

LE0

Q1 2N70

02K

D16

CMHD

457

OFF

ON

U2LT

C690

6CS6

R29

1M

R28

1M

E4E5

E6E7

SOUT

EINX

EIN

SOUT

X

D13

PRTR

5VOU

4D

J3 TOP

JP9

TOPI

/O

LOOP

LINK

R14

100Ω

R15

100Ω

R16

100Ω

R17

100Ω

6801

F12

OV1

OV0

UV1

UV0

HYST CC

1

CC0

SLT

SLTO

K DC

EOUT

EOUT SI

N

SIN

SOUT

SOUT EIN

EIN

V+ C12

C11

C10

C9 C8 C7 C6 C5 C4 C3 C2 C1 V– V TEM

P1

V TEM

P2

V REF

V REG

C23

1nF

C13

100n

F10

0V

R13

100Ω

1 3 5

2 4 6

R18

100Ω

R19

100Ω

R20

100Ω

R21

100Ω

1 3 5

2 4 6

1 3 5 7 9 11 13

2 4 6 8 10 12 14

J2BO

TTOM

1 3 5

2 4 6

1 3 5

2 4 6

1 3 5

2 4 6

1 3 5

2 4 6

1 2 3

6 5 4

1 2 3

6 5 4

D14

PRTR

5VOU

4D

C17

820p

F50

0V

C16

820p

F50

0V

C15

820p

F50

0V

C14

820p

F50

0V

Figu

re 1

4.Sc

hem

atic

of L

TC68

01 D

emo

Circ

uit


LTC6801

266801fc


PACKAGE DESCRIPTION

G36 SSOP 0204

0.09 – 0.25(.0035 – .010)

0° – 8°

0.55 – 0.95(.022 – .037)

5.00 – 5.60**(.197 – .221)

7.40 – 8.20(.291 – .323)

1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 1813

12.50 – 13.10*(.492 – .516)

2526 22 21 20 19232427282930313233343536

2.0(.079)MAX

0.05(.002)MIN

0.65(.0256)

BSC0.22 – 0.38

(.009 – .015)TYPMILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.77.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

G Package36-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.


LTC6801

276801fc


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 5/10 H-grade part added. Reflected throughout the data sheet. 1 to 28

B 7/10 Updated VREG Conditions.Updated Table 3

39

C 8/15 Web links addedTypo correction in Overview section

ALL12


LTC6801

286801fc

For more information www.linear.com/LTC6801 LINEAR TECHNOLOGY CORPORATION 2010

LT 0815 REV C • PRINTED IN USALinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6801

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC6802-1 Multi-Cell Battery Stack Monitor with a Stackable Serial Interface

Complete Battery Monitoring IC with 0.25% Cell Measurement Accuracy. Level-Shifting Serial Interface Allows Multiple LTC6802-1 Devices to be Daisy-Chained without Opto-Couplers or Isolators

LTC6802-2 Multi-Cell Battery Stack Monitor with an Individually Addressable Serial Interface

Functionally Equivalent to LTC6802-1: Parallel Connection Between Microcontroller and Multiple LTC6802-2 Devices

Figure 15. Alarm Qualification Filter/Status Indicator

6801 F15

FILTERED STATUS(LOW = OK)

2N7002

1.5k

10k

VREG5V

SOUT

LED_GREEN

CMHD4571M10nF



http://www.linear.com/LTC6802-1

http://www.linear.com/LTC6802-2

ltc6801 - independent multicell battery stack fault monitor€¦ · 6801 ta01b v+ = 43.2v ov =...

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