loop stability analysis of voltage mode buck regulator ... · pdf fileapplication report...

Application ReportSLVA301–April 2008

Loop Stability Analysis of Voltage Mode Buck RegulatorWith Different Output Capacitor Types – Continuous and

Discontinuous ModesDaniel Meeks ............................................................................... PMP - Power Supply Control Products

ABSTRACTThe buck dc/dc converter is probably the single most common voltage converter in use.Many design resources are available: application reports, text books, and many datasheets contain comprehensive design procedures for the continuous-conduction modeof operation. For discontinuous mode, however, the same solutions do not exist in asingle-source, useful format.

The purpose of this application report is to provide a complete set of design equationsfor calculating the buck converter loop gain and phase in both continuous anddiscontinuous modes. Because most modern systems use more than one type ofoutput capacitor, and because this can affect the power system stability, solutions arepresented for up to three different types of capacitors.

Contents1 Introduction .......................................................................................... 2

1.1 Stability Criteria ............................................................................ 31.2 Modulator ................................................................................... 51.3 Continuous- and Discontinuous-Mode Operation ..................................... 61.4 DCM Modulator Gain...................................................................... 81.5 Output Filter ................................................................................ 91.6 Output Filter in Discontinuous Mode .................................................. 121.7 Compensator ............................................................................. 141.8 A Design Example ....................................................................... 161.9 DCM Response of the Example Design .............................................. 21

2 Using a SPICE Simulator to Analyze Loop Stability.......................................... 222.1 Conclusions ............................................................................... 272.2 Acknowledgments........................................................................ 272.3 References................................................................................ 27

Appendix A Filter Transfer Functions ............................................................... 28

List of Figures

1 Buck DC/DC Regulator Control Block Diagram ................................................ 32 Buck Converter Schematic ........................................................................ 43 Voltage Mode Modulator........................................................................... 54 Inductor Current in (a) CCM, (b) Critical Conduction Point, and in (c) Forced CCM ..... 75 Modulator Output and Inductor Current in DCM................................................ 76 Duty Cycle of a Modulator as Load Current Transitions Between CCM and DCM ........ 87 Simplest LC Filter Schematic (a), Transfer Function (b), and Bode Plot (c). ............. 108 Real LC Filter Schematic (a), Transfer Function (b), and Bode Plot (c) ................... 119 Lossy Output Filter in CCM With Two Capacitor Types: Schematic (a) and Transfer

Function (b) ........................................................................................ 1210 Lossy Filter in DCM: Schematic (a), Transfer Function (b), and Gain / Phase

Characteristics for Two Values of Load Resistance (c) ...................................... 13

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1 Introduction

Introduction www.ti.com

11 Increasing Modulator Gain Raises Crossover Frequency and Reduces Phase Margin . 1412 Type 3 Compensator Schematic (a), and Transfer Function (b)............................ 1513 An Example of a Type 3 Compensator Response............................................ 1614 Block Diagram of Example Design with Compensation. ..................................... 1915 Gain and Phase Response of Example Design. Crossover frequency is about

17kHz and the phase margin is about 60 degrees (as calculated, not optimized) ....... 2016 Improving Loop Response by Changing R2 to 7.5k.......................................... 2117 Loop Response of the Design Example at Light Load. (a) CCM and DCM

Comparison at Critical Conduction; (b) DCM Operation at Minimum Load Current of20 mA............................................................................................... 22

18 TINA SPICE Simulation Schematic of the Example Circuit (CCM Version)............... 2319 TINA SPICE Simulation Schematic of the Example Circuit (DCM Version)............... 2420 Loop Gain and Phase for the Example Circuit, Using Both TINA (SPICE) and the

Equations........................................................................................... 25A-1 Vorperion’s Model of the Modulator and Filter in DCM....................................... 28A-2 Vorperion’s DCM Model With an Ideal Voltage Source ...................................... 29A-3 General Block Diagram of a Buck Converter With DCM Modulator and Filter

Transfer Functions ................................................................................ 30A-4 CCM and DCM Filter Transfer Functions for Filters with One Type of Output

Capacitor ........................................................................................... 32A-5 CCM and DCM Filter Transfer Functions for Filters With Two Types of Output

Capacitor ........................................................................................... 33A-6 CCM Filter Transfer Functions for Filters With Three Types of Output Capacitor (a, b) 34A-7 DCM Filter Transfer Functions for Filters With Three Types of Output Capacitor (c).... 35

List of Tables

1 Design Parameters for Voltage Mode dc/dc Converters and Controllers.................. 25

In electronic circuits, the basic buck converter is not complicated (see Figure 1). The power section, orplant, consists of a pulse generator and a passive filter. These combine to convert an applied input voltageto a (lower) output voltage. The particular technique of using the pulse source and a reactive(nondissipative) output filter allows the transfer of energy with high efficiency. That is, little power is lost inthe converter itself.

In order to regulate the output voltage, a voltage reference and an error amplifier are added to the circuit.These three basic blocks (the pulse generator, output filter, and error amplifier) combine to form acomplete dc/dc converter (see Figure 1).

Other switch-mode converters are based on this buck topology. The forward converter, includingsingle-transistor, half-bridge, and full-bridge topologies can all be represented by the same block diagramshown in Figure 1.

Implementing a modern buck converter can be accomplished in many ways, using different technologies.The error amplifier and voltage reference usually are integrated along with a voltage-controlled pulsegenerator, or modulator, into a monolithic integrated circuit (IC). The modulator’s pulse output is bufferedby power switches, which may be internal to the IC or external discrete devices. The output filter is almostalways made up of an external inductor and capacitor(s).

The design of the circuit begins by selection of various operating parameters and component values,largely determined by the basic operating requirements, namely:• Input voltage range• Output voltage• Output current range• Operating frequency

2 Loop Stability Analysis of Voltage Mode Buck Regulator SLVA301–April 2008Submit Documentation Feedback


1.1 Stability Criteria

ref out

control

V V

V

Modulator Filter

Compensator

S

( ))(1

)()(

)()()(1

)()( mod

mod

mod

sH

sHsH

sHsHsH

sHsH

V

VsH

Loop

Filter

rCompensatoFilter

Filter

ref

outsystem

+

×=

××+

×==

(1)

observing)(sH LoopÐ

[the phase of HLoop (s)] when its magnitude is unity. This measure of the phase is

the phase margin, and it is the difference between –180° and°+Ð 180)(sH Loop . Mathematically, the

phase margin is )(sH LoopÐ ., and a higher phase margin indicates a more stable control loop. A phase

www.ti.com Introduction

By using these design requirements, the values of the filter components are determined, and the powerswitches are selected. As the method of choosing these parts and the operating frequency are wellcovered by most data sheets and many application reports (SLUP206)[1], it is not discussed in thisdocument.

After selecting the main circuit components, the error amplifier and voltage reference must be added toprovide output voltage regulation. The design of this compensator is described in several places, butusually only in specific terms, and only for specific operating conditions (continuous-conduction mode, withone type of output capacitor). Mathematical models for discontinuous-conduction mode, with severaldifferent capacitor types and parasitic losses, are unavailable.

This application report describes the design of the compensator for the voltage-mode buck converter, withsolutions for complex filter structures and for operation in both the continuous- anddiscontinuous-conduction modes.

A step-by-step design procedure is also given, which can be used as a guideline for compensator designfor any buck converter operating in the continuous and discontinuous modes.

Although the output filter can be infinitely complex (depending on the number and types of outputcapacitors, which are practically unlimited in variation), solutions are presented for some common designs(one, two, and three different types of output capacitor).

The control model of a buck converter can be represented by three basic blocks as shown in Figure 1.

Figure 1. Buck DC/DC Regulator Control Block Diagram

The transfer function of the system shown in Figure 1 is

The denominator of the system transfer function, 1 + HLoop (s), is the characteristic equation of the system,and HLoop (s) is the loop gain – the gain of the loop consisting of the modulator, filter, and compensator [3].By inspection, it is clear that if HLoop (s) = –1, the transfer function of the system, HLoop (s) will becomeinfinite – and that would be an unstable system.

The Nyquist criteria can be used to determine the stability of this system [4]. Because of the relativecomplexity of a typical buck converter, the most convenient way to analyze stability is by the use ofgraphical methods.

A special case of the Nyquist criteria can be applied by plotting the gain and phase of HLoop (s), and

margin of 45° is usually taken as a minimum goal in power supply design, but any positive phase marginwill result in a stable system.

The loop gain is the product of the transfer functions of each block in the loop:


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( ) )()()(mod sHsHsHsH rCompensatoFilterLoop ××= (2)

Modulator

V

V V

0V 0V

in

out

in in

Control

Voltage V

LoadC

L

Error Amplifier and Frequency Compensator

out

),,,(Loadfilter

RCLfA

),(mod controlin

VVA

outV


Each of these transfer functions must be determined in order to calculate HLoop (s). Therefore, each blockis treated separately. Before doing this, the contents of each block is described in order to make clearerthe comparison of the general block diagram to an actual schematic of a converter.

For this discussion, a generic schematic is used in order to avoid clutter and confusion. An actual circuitcontains additional components, including an actual control integrated circuit (IC), but that level of detail isunnecessary for this discussion. Although some details are controller dependent, the concepts presentedhere are general. In a later example, it becomes clear how the controller properties affect the solution, anda list of controllers is presented along with their characteristics to aid in the calculations for specificdesigns.

For this derivation of the loop stability equations, the following block diagram represents a non-isolatedbuck converter (see Figure 2):

Figure 2. Buck Converter Schematic

Loop Stability Analysis of Voltage Mode Buck Regulator4 SLVA301–April 2008Submit Documentation Feedback


1.2 Modulator

that the output is connected to ground, and the duty cycle is defined as offon

on

tt

tD

+

=

.

V

V

V

V

V

V

V

in

control

control

mod

mod

ramp

ramp

òò ==on

t

in

T

outdtV

Tdttv

TV

00mod

1)(

1

(3)

DVtt

tVV in

offon

oninout ×=

+

×=

(4)

control

out

V

VA

D

D=

mod

(5)


Of the three blocks that make up the buck converter, the modulator is the only one with no frequencydependence. The modulator is basically a voltage-controlled rectangle wave generator: In response to acontrol voltage, the modulator produces a repeating rectangular output waveform, with limits of 0 V andVcc. This rectangle wave is produced by connecting the output to either the input voltage (Vcc) or toground. The duty cycle of the output is defined as the time spent at Vcc divided by the total period of therepetitive waveform. As such, ton is defined as the time that the output is connected to Vcc, toff is the time

Internally, the most basic modulator consists of a voltage comparator and a sawtooth generator. Theseblocks are combined to produce the desired result as shown in Figure 3.

Figure 3. Voltage Mode Modulator

As the control voltage increases, the duty cycle of the output increases as well. When the control voltageequals (or is greater than) the peak voltage of the ramp signal, the output is continuously high. In otherwords, toff = 0 and the duty cycle is 1 (or 100%).

Conversely, if the control voltage is at or below the minimum of the ramp voltage, the output of thecomparator is continuously low. This means that ton = 0 and the duty cycle is 0 (or 0%).

Notice that the frequency of the ramp signal determines the frequency of the modulator output, which isthe switching frequency of the converter.

The modulator’s output is a rectangle wave. This rectangle is averaged by the output filter and applied tothe load as a dc voltage. The dc voltage is therefore the average of the rectangular pulse waveform, or

Here, T is the period of repetitive pulse waveform ( T = ton + toff), so

In terms of the transfer function of the modulator, this is defined as the averaged value of the pulse trainoutput divided by the control voltage input, or:

This refers to the change in output voltage as a result of a change in the control voltage. Rememberingthat the control voltage is bounded by the ramp voltage (which is considered a part of the modulator), andincluding the fact that the range of Vout is 0V to Vin.



ramp

in

ramp

controlin

controlcontrol

outCCM

V

V

V

VV

dV

d

dV

dVA =

÷÷

ø

ö

çç

è

æ==-mod

(6)

1.3 Continuous- and Discontinuous-Mode Operation


This is the gain of the modulator. On a Bode plot, Amod-CCM is a constant gain and it causes no phase shift.In reality, this block has time delays, which cause phase shift. However, for the purpose of calculating theloop gain and phase, these phase shifts usually are not a problem.

When the inductor current is continuous in a buck converter, it is operating in the continuous-conductionmode, or CCM. Otherwise, the inductor current returns to zero during each cycle, and this is thediscontinuous-conduction mode, or DCM.

In the block diagram of Figure 1, the filter and compensator blocks have linear transfer functions. Themodulator, however, is nonlinear. The modulator responds to a continuous control voltage input andproduces a pulse train output with the required duty cycle. At light loads, when the load current is belowthe critical current, the modulator may be commanded to produce pulses that are narrower than thoserequired in CCM. This occurs when the modulator output is incapable of sinking current (thenonsynchronous power stage is one such structure). When the inductor current reaches zero, themodulator output disconnects from the output filter, and the voltage rises to Vout until the next cycle beginsand the input voltage is applied to the modulator output again. Figure 4 shows cases of CCM, the criticalconduction point, and forced CCM, where the modulator is forced to sink current. This forced CCM isusually a characteristic of the controller IC being used and has some advantages over allowing theconverter to revert to DCM.

Figure 5 shows the modulator output of a converter operating in DCM. When the inductor current reacheszero, the modulator output becomes high impedance, and this node can be seen floating up to Vout untilthe next cycle starts.



I L

I out

I out

I out

VModulator

I L

I L

t

t

t

t

0

0

0

0

a.

b.

c.

(Continuous Conduction Mode)

(Critical Conduction)

(Forced Continuous Conduction Mode)

VModulator

VOut

VIn

t0

I L

t0


Figure 4. Inductor Current in (a) CCM, (b) Critical Conduction Point, and in (c) Forced CCM

Figure 5. Modulator Output and Inductor Current in DCM

During the analysis of the loop stability, it is necessary to know if the converter is operating in CCM orDCM, or both (over a range of load current, the converter can enter both modes). If the controller operatesin the forced PWM, forced CCM, or forced continuous mode (these all mean the same thing), then italways operates in CCM. Otherwise, the operating mode must always be known, so that the correctmodulator gain and filter transfer functions are used.



( )( )

swin

outinout

sw

in

outoutin

criticalfLV

VVV

fL

V

VVV

CurrentRippleInductorIout

222

-=

-

»=(7)

1.4 DCM Modulator Gain

When the converter is operating in CCM, the duty cycle is approximately in

out

CCM

V

VD =

. However, when

112

8

2

-÷÷ø

öççè

æ-

=

out

in

sw

DCM

V

V

R

fL

D

(8)

1 10 100 1.1030

0.1

0.2

0.3

0.4

0.5

0

1

2

3

4

5

Load Resistance

Du

ty C

yc

le

Lo

ad

Cu

rre

nt

-A

V = 12 V,

V = 5 V,

R = 11

IN

OUT

critical W

Duty Cycle

Load Current


The operating point that lies exactly at the threshold of DCM and CCM operation is usually referred to asthe critical conduction point. At critical conduction, the dc output current is equal to half of the inductor’speak-to-peak ripple current:

When Iout < Ioutcritical, the converter operates in DCM (unless it is in forced PWM mode as previouslydescribed), and when Iout ≥ Ioutcritical it operates in CCM.

the output current is below the critical current given in Equation 7, and when the converter is not in theforced PWM mode (that is, when the controller allows DCM), the duty cycle of the modulator reduces inorder to maintain regulation. The modulator’s duty cycle in DCM is given in SLVA057[2], and it includes theinductor series resistance RL. Recognizing that RL << R in DCM, the modulator duty cycle is:

WhereRL is the load resistanceL is the value of the inductorVin is the input voltageVout is the output voltageƒsw is the regulator’s switching frequency

Noting that DDCM is now a function of the load resistance R, it clearly also depends on the load current.This is in contrast to CCM, where the duty cycle depends only on Vin and Vout. Figure 6 shows the dutycycle of a modulator, as the load current decreases and it transitions from CCM to DCM.

Figure 6. Duty Cycle of a Modulator as Load Current Transitions Between CCM and DCM

In DCM, the modulator does not produce a continuous pulse stream. It has three states: Vin, 0 V (ground),or open-circuit (high impedance), as shown in Figure 5. The transfer function of the modulator plus filterbecomes more complicated than the CCM case. The modulator gain (the term gain is used loosely; seeAppendix A for development) is:


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÷÷ø

öççè

æ-

÷÷ø

öççè

æ-

==-

in

outDCMramp

in

outout

control

outDCM

V

VDv

V

VV

Vd

VdA

2

12

mod

(9)

Equation 9 is only valid in DCM, meaning that critical

out

Iout

VR >

. Otherwise, the converter operates in CCM,

1.5 Output Filter


Where:DDCM is the duty cycle in DCM from Equation 8

and the modulator gain is given by Equation 6.

The modulator provides a pulse train, bounded by the input voltage, whose duty cycle is determined by anapplied control voltage. The output filter performs the averaging function that converts this pulse train intothe output voltage of the converter.

Because the goal of a dc/dc converter is to have high efficiency, the output filter consists of reactivecomponents, which do not (to first order) dissipate any power. This filter operates as a low-pass filter inthe frequency domain, suppressing the ac components of the modulator’s pulse train. It is a simplesecond-order L-C section, terminated by the load resistance. Therefore, the load resistance is a criticalcomponent of the filter. It must be known in order to predict the filter’s performance, the loop response,and the stability of the converter.

As described so far, the output filter is a simple second-order passive structure. Its transfer function nowcan be written and used in the stability calculations. However, some important caveats must be noted inorder to attain useful and accurate results. These are addressed in the following paragraphs.

A discussion of the transfer function of the simple L-C filter, terminated by the load resistance R follows(see Figure 7).



a.

b.

c.

L

RC

V Vin out

RLCsLsR

RsH

RLC 2)(

++

=


Figure 7. Simplest LC Filter Schematic (a), Transfer Function (b), and Bode Plot (c).

The cutoff frequency in this example (L = 10 µH, C = 100 µF, and R = 1 Ω) is approximately 5 kHz, andthe ultimate phase shift settles at –180°, whereas the gain slope is –40 dB per decade of frequencyincrease above the LC cutoff frequency.

In many cases, parasitic effects of components are easily ignored and cause little consequence. To firstorder, capacitors and inductors have parasitic resistance, and these are included in this analysis, so thatthe filter transfer function is more accurate. Including some series resistance (usually referred to as ESR)in both the inductor and the output capacitor, results in this modified filter (the Bode plot has the losslessversion superimposed for comparison, see Figure 8):



a.L

R

C

V V

R

R

in out

C

L

b.

c.

21

)(1)(

sCLR

RRs

R

CRRCRCR

R

L

R

R

sRCsH

CCL

LC

L

C

Filter

÷ø

öçè

æ ++÷

ø

öçè

æ+++++

+=


Figure 8. Real LC Filter Schematic (a), Transfer Function (b), and Bode Plot (c)

The effect of the parasitic resistances depends on their values relative to the other circuit values. Thus, itcannot be inferred from this discussion that a lossy filter creates an increasing phase and gaincharacteristic in all cases. The point is that the response of the filter can be changed, sometimes verydramatically, when these parasitics are included. The effect may be so subtle as to be insignificant. Butthe effect may be extremely dramatic, forcing design and component restrictions. Always consider theparasitics, and make an engineering judgment about whether to include them in calculations.

Complicating the filter design is the infinite number of load impedance structures. On a large board, threeor four different types of output capacitors are possible, connected at various points in the power plane.The transfer function of the output filter with even two output capacitor types can become challenging (seeFigure 9):



a.L

R

C C

V V

R R

R

in out

C1 C2

L

1 2

b.

( ) ( )

( ) ( )[ ] ( )

( )[ ]2121213

221112122121212

2122111

3

3

2

21

2

11222211

1

)()(1)(

CCCC

CCCCCCL

L

CC

CCCC

CCMFilter

RRRRRCCR

La

CRCRR

LCCRRRRCCRCCLa

CCR

RCRCR

R

Lawhere

sasasa

sCRCRsCRCRsH

++=

++++++=

++++=

+++

+++=-

1.6 Output Filter in Discontinuous Mode


Figure 9. Lossy Output Filter in CCM With Two Capacitor Types:Schematic (a) and Transfer Function (b)

In order to model more complex output structures, the transfer function can be derived and used in theloop equations to calculate the gain and phase, which is the direction of this discussion. Appendix Acontains transfer functions for filters with one, two, and three output capacitors, if equation-based solutionsare desired. But it may be more convenient to use a SPICE (simulation program with integrated circuitemphasis) simulator to perform the loop analysis for more complicated structures.

In DCM, the output filter response changes because of the discontinuous nature of the modulator’s drivingimpedance. In CCM, the modulator’s output impedance is relatively low, but in DCM it is not. Theequivalent circuit and transfer function of a lossy filter in DCM is shown in Figure 10.



a.

L

R

C

R

R

Vin Vout

C

L

2

211

1)(

sasa

CRssH C

DCMFilter ×+×+

××+=-

where( )

in

out

LC

in

out

V

V

RRCV

VCR

R

L

a

-

++÷÷ø

öççè

æ-+

=2

1

1

÷÷ø

öççè

æ-

=

in

out

V

V

CLa

2

2

W=

W=

=

W=

=

=

=

=

5.7

25

100

50

10

300

5

25

critical

C

L

out

in

R

mR

FC

mR

HL

kHzf

VV

VV

m

m

R x 1 -V

out

Vin

( )


Figure 10. Lossy Filter in DCM: Schematic (a), Transfer Function (b), andGain / Phase Characteristics for Two Values of Load Resistance (c)

Appendix A gives transfer functions for DCM filters with one, two, and three output capacitors.



1.7 CompensatorIntroduction www.ti.com

The modulator and the output filter (including the load resistance) create the forward plant of the buckconverter. These are the two stages that generate a dc output voltage from the dc input voltage. In orderto close the loop, the output voltage is compared to a voltage reference, the error is amplified, and thaterror is applied to the modulator as its control voltage input. As the output voltage approaches thereference voltage, the error produced becomes small, and the system reaches a point of equilibrium: atemporary increase in Vout creates a corresponding decrease in control voltage, which in turn drives theduty cycle of the modulator down, bringing the system back to a new point of equilibrium.

In order for this linear system to be stable, the loop phase delay must be less than 360° while the loopgain is above unity [ |ALoop (s)|≥ 1, or 20log|ALoop (s) | ≥ 0 dB]. While the loop is stable for any phase shiftless than 360°, a critically damped system (a reasonably fast loop response with minimal overshoot) willhave a phase margin (defined as the difference between the actual loop phase delay and 360°) of about60°. Any phase margin above zero degrees is technically stable, but lower values of phase margin areaccompanied by more ringing in the loop after the loop is perturbed (by a change in Vin or Iout, forexample). In power circuit design, 45° is often taken as a minimum goal for the phase margin.

As this is a negative feedback system, the error amplifier has a 180° phase shift (note the connections onthe operational amplifier in Figure 2). That means that the plant (the modulator and output filter) in acritically damped system can only contribute another 120° of total phase shift, while the loop gain is aboveunity. Note that the modulator practically contributes no phase shift to the loop, but it does have gain. Theoutput filter, being at least a second-order structure, can ultimately create at least 180° of phase shift. Ofcourse, a second-order filter’s phase shift reaches 180° only as its frequency approaches infinity —however, depending on the circuit values, it can reach the magic number of 120° quickly as it passesthrough its resonant frequency. In the examples given for the filter in Figure 7 and Figure 8, the insertionphase changes fast around the resonant frequency of the filter. Adding modulator gain to this passive filterincreases the phase shift at the crossover (0 dB) frequency. This does not happen because the filter’sinsertion phase actually increases, but because the additional gain causes the crossover frequency toincrease, as shown in Figure 11.

Figure 11. Increasing Modulator Gain Raises Crossover Frequency and Reduces Phase Margin

In order to close the loop on this converter, the error amplifier is inserted, as previously described,between the regulator output and the modulator control input. This allows the error amplifier to control theduty cycle of the modulator and hold the output voltage constant. Clearly, too much insertion phase is inthe modulator/filter combination to achieve the desired phase margin for the closed loop. Therefore, theerror amplifier is modified to shape the gain and phase of the loop so that the desired crossover frequencyand phase margin can be achieved. The error amplifier is implemented using an operational amplifier inmost cases. This building block can be used to provide the necessary compensation of gain and phase inthe configuration shown in Figure 12.



a.

controlsense

1

1

2

3

2

3

ref

VV

R

C

C

C

R

R

V

b.

÷÷ø

öççè

æ

++÷÷

ø

öççè

æ++

÷÷ø

öççè

æ+÷÷

ø

öççè

æ ++

=

==

=

+=

+==

33122

31

33221

21131

)(

11)(

1

)(

2

1

)(

)()(1

)()(

CRRs

CRsRR

CRs

RCC

CCssCRR

s

PoleonCompensatiOpampf

GainDCOpampA

s

AsH

wheressH

sH

V

VsH

polepole

DC

pole

DCOL

OL

OL

sense

controlrcompensato

b

pv

v

b

dc

poleA

GBWpv 2=

(10)


Figure 12. Type 3 Compensator Schematic (a), and Transfer Function (b)

The equations in Figure 12 require some explanation. The compensator is made up of an operationalamplifier, configured as a complex filter by careful choice of the external passive components. As theoperational amplifier is a part of the circuit, its characteristics may have some effect on the circuit’sbehavior, and this is why the basic operational amplifier parameters are included. The open-loop dc gainof the operational amplifier is represented by Adc and ωpole. ωpole is the frequency of the operationalamplifier’s internal compensation pole. In the case of a discrete operational amplifier with its own datasheet, finding ωpole is a matter of taking it from the open-loop frequency response. In a dc/dc controller, theerror amplifier’s open-loop response is usually not provided.

Another way to arrive at ωpole is to use the operational amplifier’s gain-bandwidth (GBW) and its dc voltagegain, Adc, which are commonly given in a data sheet for a dc/dc converter:

The operational amplifier’s open-loop gain should be higher than the desired compensator gain at allfrequencies. Otherwise, the compensator response depends on the operational amplifier variations. In adc/dc controller, the error amplifier gain is not well controlled (usually only a typical gain is specified); so, itis recommended to design the compensator to be relatively insensitive to variations in the error amplifiergain.



1.8 A Design Example


The modulator plus filter adds considerable phase delay, degrading the loop-phase margin, as has beenshown. The compensator is designed to restore some loop phase, so that the overall loop phase marginmeets our design goals, whatever they may be. The Type 3 compensator that is being discussed canprovide two poles and two zeros in its transfer function. This is usually adequate for achieving criticaldamping (phase margin of about 60°), for example.

As may be expected, the circuit values interact with each other, and the location and behavior of thedesigned poles and zeros also affect each other. It is usually not practical (or necessary) to place thepoles and zeros far enough apart that they do not interact. Fortunately, the desired response can usuallystill be obtained, sometimes with a little trial-and-error or judicious use of a SPICE simulator.

One possible response of this compensator is shown in Figure 13. The designed pole and zero locationsare indicated, and in this case they are fairly easy to see in the actual response (the values were chosenfor enough separation to see the inflections of each pole and zero). In a real-world design, the separationmay not be so clear, but the overall goals for a stable system are usually still achievable.

Figure 13. An Example of a Type 3 Compensator Response

One possible algorithm for placing the poles and zeros is demonstrated by an example. Besides decidingwhere to place the poles and zeros, the compensator gain also determines the crossover frequency of theloop. The crossover frequency selection is based on the switching frequency and the desired looptransient response. No attempt is made to define an optimum compensator, but the example used can beconsidered typical. In this case, the loop crossover is chosen to be near 20 kHz (that is, it is designed for20 kHz, but a result that is reasonably close is acceptable, as errors due to interactions between thedesired poles and zeros are expected). Only the CCM of operation is considered in order to design thecompensator, but the DCM response for the final circuit is calculated.

The loop consists of the modulator, the output filter, and the compensator. The modulator’s gain is afunction of Vin and Vramp when operating in CCM. The filter’s transfer function is a function of thecomponent values, including the load impedance. Although the selection of the filter components have notbeen discussed, they are mainly chosen based on dynamic issues in the circuit design. These choicesand trade-offs are described well in most data sheets and several application reports (see SLUP206), andare not discussed in this document. Usually, the output inductor and capacitor(s) are decided before thecompensator design is started.




2

modmod

1

)(1

)(

sCLR

RRs

R

CRRCRCR

R

L

R

R

sRC

V

V

HHsH

CCLLC

L

C

ramp

in

CCMFilterCCMfilter

÷ø

öçè

æ ++÷

ø

öçè

æ+++++

+×=

= --+

(11)

VVV

V ccramp 85.015.0

20=-=

53.2385.0

20mod

===-

V

V

V

VA

ramp

ccCCM

(or 27.4 dB)

(12)

kV

Vk

V

VRR

ref

outbottom 6.311

696.0

511.51

1=÷

ø

öçè

æ-=

÷÷

ø

ö

çç

è

æ-=

(13)

kHzuFuHCL

fout

LC 20.3247102

1

2

1=

×

=

×

=

pp (14)

nFRfRf

CLCLC

75.18.1

1

9.02

1

11

3==

×

=

pp

(use 1.8 nF)

(15)


This leaves the combined transfer function of the modulator and the output filter, and this response mustbe used to design the compensator. For example, the transfer function of the modulator and output filter ofa design with a single type of output capacitor in CCM is given by:

For this design example, use the following parameters:Vin = 20 VVout = 5 VIout = 20 mA to 3 Aƒsw = 300 kHzL = 10 µHRL = 25 mΩCout = 220 µF Electrolytic with RC1 = 25 mΩ

plus 22 µF Ceramic with RC2 = 5 mΩplus 50 × 0.1 µF Ceramics with 5 mΩ each, so RC3 = 0.1 mΩ

Controller: TPS40200D, a nonsynchronous fixed frequency controller.

Controller Parameters (controller information is summarized in Table 1):

PWM Ramp Amplitude:

Error Amplifier Open-Loop DC Gain: ADC = 10k

Error Amplifier Compensation Pole: 300 Hz

Feedback Reference Voltage: 0.696 V

Step 1: Calculate the modulator gain using Equation 6:

Step 2: Calculate the Resistor Divider Values.Referring to Figure 12:

(5.11k was chosen for the closest match to standard 1% resistor values for the divider)

Step 3: Calculate the filter’s resonant frequency:

Step 4: Place the first zero slightly below the filter’s resonant frequency:

Step 5: Place a pole at the crossover frequency:



kCf

Rcrossover

42.42

1

3

3==

p

(use 4.42 K)

(16)

)61.2(35.1

)2(1)2)((1

)2)((1

1

2

_

dBor

fjCLR

Rfj

R

CRRCRCR

R

L

R

R

fjRC

V

V

H

crossoverC

crossoverCL

LCL

crossoverC

ramp

in

xovercomp

=

÷ø

öçè

æ+++++++

+×

=

pp

p

( ) ( )( ) kkkHRRR xovercomp 23.535.142.46.31_312 ==×= (use 5.23 k)(18)

nFkkHzRf

CLC

56.1023.502.38.1

1

8.1

1

2

2=

××

==

pp

(use 10 nF)

(19)

pFkkHzRf

Ccrossover

15223.52020

1

102

1

2

1=

××

=

×

=

pp

(use 150 pF)

(20)

( ) )()()(mod sHsHsHsH rCompensatoFilterLoop ××= (21)

ïïïïïï

î

ïïïïïï

í

ì

÷÷ø

öççè

æ-

÷÷ø

öççè

æ-

==

=

)(

2

12

)(53.2385.0

20

mod

onlyDCM

V

VDv

V

VV

CCMForcedorCCMV

V

V

V

H

in

outDCMramp

in

outout

ramp

in

(22)

îíì

=A5.FigureA,AppendixinGiven

CapacitorsOutputofTypes3forFunctionsTransferSee(s)HFilter

(23)

)()(1

)()(

ssH

sHsH

OL

OLrcompensato

b+=

(24)


Step 6: Calculate the required gain of the compensator at the desired crossover frequency:

(17)

Step 7: Set the gain of the compensator:

Step 8: Place a second zero just below the filter resonance:

Step 9: Place a second pole about a decade above the crossover frequency:

Step 10: Calculate or simulate the entire loop and adjust if necessary.The loop response can be calculated using Equation 21 through Equation 28.



pole

DCOL s

AsH

v

+

=

1

)(

(25)GainDCOpampADC = (26)

PoleonCompensatiOpampf polepole == pv 2 (27)

÷÷ø

öççè

æ

++÷÷

ø

öççè

æ++

÷÷ø

öççè

æ+÷÷

ø

öççè

æ ++

=

33122

31

33221

21131

)(

11)(

1

)(

CRRs

CRsRR

CRs

RCC

CCssCRR

sb

(28)

Modulator

Error Amp / Compensator

5.11 kW

(0.696 V)

C1150 pF

C210 nF

V

20 VIN

V = 0.85 Vramp

R

25 m

L

W

L

10 Hm

Filter

Vout

R

1.67 WC

50 x 0.1 F

3

m

R

5 m / 50

C3

W

C

22 F

2

m

R

5 m

C2

W

C

220 F

1

m

R

25 m

C1

W

R3

4.42 kW

C31.8 nF

R1

31.6 kW

R2

5.23 kW


Following these steps results in the following final design (see Figure 14):

Figure 14. Block Diagram of Example Design with Compensation.



10 100 1! 103 1! 104 1! 105 1! 10620

10

0

10

20

30

40

50

Complete Loop Gain

Modulator + Filter

Error Amp

CCM Loop Response of Example (Not Optimized)

Ga

in (

dB

)

10 100 1! 103 1! 104 1! 105 1! 106180

135

90

45

0

45

90Complete Loop Phase

Modulator + Filter

Error Amp

Frequency

Ph

ase


Figure 15. Gain and Phase Response of Example Design.Crossover frequency is about 17kHz and the phase margin is about 60 degrees

(as calculated, not optimized)

The calculated gain and phase of the example circuit, with the closest standard component values to thecalculated results, is shown in Figure 15. The crossover frequency is lower than the 20-kHz goal, and theloop phase margin is acceptable at about 60°.

The plots also show the contribution of the output filter and the error amplifier (including compensation).

Increasing the mid-band gain is one way to increase the crossover frequency, to achieve the goal of 20kHz, if necessary (see Equation 18).

In this case, increasing R2 to 7.5k gives the following improved result (see Figure 16).



10 100 1! 10 3 1! 10 4 1! 10 5 1! 10 620

0

10

20

30

40

50

10Complete Loop Gain

Modulator + Filter

Error Amp

CCM Loop Response of Example (Optimized)

Ga

in (

dB

)

10 100 1! 10 3 1! 10 4 1! 10 5 1! 10 6180

135

90

0

45

90

45

Complete Loop Phase

Modulator + Filter

Error Amp

Frequency

Ph

ase

1.9 DCM Response of the Example Design


Figure 16. Improving Loop Response by Changing R2 to 7.5k

In DCM, the discontinuous nature of the modulator causes a damping of the output filter. The modulatorgain is a function of the modulator duty cycle DDCM, as well as the load resistance R (see Equation 7 andEquation 8). When the output current is at or above Ioutcritical (see Equation 6), the converter behavesaccording to the CCM equations previously used in this example. However, when the output current fallsbelow Ioutcritical, the frequency response is different because of this output filter damping effect. At thecritical conduction point, the response abruptly changes, as shown in Figure 17(a). Figure 17(b) shows theresponse of the loop when the output current is at minimum, 20 mA.

Table 1 lists popular TI dc/dc controllers and converters, and gives the values for use in the designEquation 12 through Equation 28.



a.

10 100 1 ! 103

1 ! 104

1 ! 105

1 ! 106

20

10

0

10

20

30

40

180

150

120

90

60

30

0

CCM Loop GainDCM Loop GainCCM Loop PhaseDCM Loop Phase

CCM and DCM Loop Response at Critical Conduction (Iout = 625mA)

Frequency

Gain

(dB

)

Phase

10 100 1 ! 103

1 ! 104

1 ! 105

1 ! 106

20

10

0

10

20

30

40

180

150

120

90

60

30

0

Gain

DCM Loop Response at Iout = 20mA

Frequency

Gain

(dB

)

Phase

b.

2 Using a SPICE Simulator to Analyze Loop Stability

Using a SPICE Simulator to Analyze Loop Stability www.ti.com

Figure 17. Loop Response of the Design Example at Light Load.(a) CCM and DCM Comparison at Critical Conduction;(b) DCM Operation at Minimum Load Current of 20 mA

SPICE simulators are perfect for small-signal ac analysis of linear circuits, and that makes them perfect forcalculating the loop gain and phase of a power supply.

The equations derived and presented in this document are useful for calculation using equation-basedtools such as Mathcad™, Excel™, etc., but when the output filter becomes more complicated aSPICE-based solution makes the work much easier.

Figure 18 shows an example of using TINA [6] to perform the loop analysis for the CCM buck converterused in the preceding example. The advantage of using SPICE for this type of circuit becomes obvious,when comparing the SPICE schematic to the equations in Appendix A. However, SPICE does not designthe compensator, so the design process given in Equation 12 through Equation 20 must still be followed.

TINA allows the use of embedded equations, in an Interpreter block. The Interpreter makes it convenientto perform some calculations based on circuit values and helps with documentation because thecalculation results are a part of the schematic.

Because the design equations (for the modulator) are different in CCM and DCM, another TINA schematicis shown in Figure 19. This gives the solution for the DCM operation of the same circuit. Note that theDCM circuit is used only when the output current is less than the critical current (the calculations areincluded in both TINA circuits).

Using a SPICE simulator like TINA allows more complex output filter structures, including effects ofdistributed power planes, high-frequency filters, ferrites, and other complex load reactances.

These TINA circuits give good results compared to the calculations. Figure 20 shows a comparisonbetween TINA and the calculated results for the example circuit in CCM.



Op

Am

pO

ut

Op

Am

pIn

Op

Am

pIn

Op

Am

pO

ut

Vo

ut

L1

0u

Co

ut1

22

0u

Rc

1 2

5m

R 8

R2

7.5

k

R2

5.1

k

R1

31

.6k

R3

4.4

k

C2

10

n

C1

15

0p

C3

1.8

n

-+

-+

VC

VS

1 2

3.5

Co

ut2

22

u

Rc

2 5

m

Co

ut3

5u

Rc

3 1

00

u

+

VG

1

-+

-+VC

VS

3 -

1

-+

-+

DC

_G

ain

10

k R_

co

mp

1k

C_

co

mp

53

1n

RL

25

m

CC

M C

alc

ula

tio

ns

Vin

:=

20

Vo

ut

:=5

fre

q :

= 3

00

k

Vra

mp

:=

0.8

5

V,

fro

mTa

ble

I

Am

od

_ccm

:=

Vin

/ V

ram

p

Am

od

_ccm

=[2

3.5

29

4]

Ca

lcu

late

Critica

lC

urr

en

t:

Icritica

l :=

((V

in -

Vo

ut)

!V

ou

t) /

(2

!V

in!fr

eq

!L

)

Icritica

l =

[62

5m

]

Iou

t :=

Vo

ut/

R

Iou

t=[6

25

m]

En

su

reth

at

Iou

t >

= I

critica

l fo

r C

CM

op

era

tio

n

Op

am

p M

od

el, in

clu

din

gD

C g

ain

an

d F

irst-

Ord

er

Co

mp

en

sa

tio

nP

ole

Se

eTa

ble

I o

r th

e D

ata

Sh

ee

t fo

r th

e I

C

fpo

le :

= 3

00

H

z

DC

ga

in :

= 1

00

00

1

00

0 =

60

dB

, 1

00

00

= 8

0d

B,

10

00

00

= 1

00

dB

Rco

mp

:= 1

kl

ea

ve

this

fixe

dfo

r th

e m

od

el

Cco

mp

:= 1

/ (

2!p

i!fp

ole

!R

co

mp

)p

lace

sth

e c

om

pp

ole

Cco

mp

=[5

30

.51

65

n]

CC

M L

inear M

od

el

of

Bu

ck

Con

verter

/---

----

-- C

om

pe

nsa

tor

----

----

--/

/---

----

----

----

----

Filt

er

----

----

----

----

----

/C

CM

Mo

du

lato

r

/---

----

----

Op

Am

p M

od

el --

----

----

--/

Lo

ad

Re

sis

tan

ce

(no

te p

ha

se

inve

rsio

n)

www.ti.com Using a SPICE Simulator to Analyze Loop Stability

Figure 18. TINA SPICE Simulation Schematic of the Example Circuit (CCM Version)



Op

Am

pO

ut

Op

Am

pIn

Op

Am

pIn

Op

Am

pO

ut

Vo

ut

L10u

Co

ut1

220u

Rc1 2

5m

R 2

50

Rd

isc 1

87.5

R2 7

.5k

R2 5

.1k

R1 3

1.6

k

R3 4

.4k

C2 1

0n

C1 1

50p

C3 2

.2n

-+

-+

VC

VS

1 1

97

RL

25m

Co

ut2

22u

Rc2 5

m

Co

ut3

5u

Rc3 1

00u

+

VG

1

-+

-+VC

VS

3 1

-+

-+

VC

VS

4 1

0k

R4 1

kC

4 5

31n

Vin

:=

20

Vout :=

5

freq :=

300

k

Vra

mp :

= 0

.85

from

Table

I o

r th

e d

ata

sheet fo

r th

e IC

Ddcm

is the m

odula

tor

duty

cycle

in D

CM

Ddcm

:=

sqrt

((8!

L!fr

eq/R

)/((

(2!V

in/V

ou

t)-1

)^2-1

))

Ddcm

=[4

4.7

214m

]

Am

od_dcm

:=

(2!

Vo

ut!

(1-V

out/V

in))

/(V

ram

p!D

dcm

!(2

-Vout/V

in))

Am

od_dcm

=[1

12.7

42

9]

Icritical :=

Vout!(V

in -

Vout)

/ (

2!fr

eq

!L

!V

in)

Icritical=

[625m

]

Iou

t :=

Vout/R

Iout=

[20m

]

When I

out <

Icritical, the m

odula

tor

opera

tes in D

CM

R_dis

c :=

R!(1

- V

out/V

in)

R_dis

c =

[187.5

]

Opa

mp M

od

el, inclu

din

g D

C g

ain

and F

irst-

Ord

er

Com

pensation P

ole

fpole

:=

30

0

Hz

DC

gain

:=

10000

1000 =

60dB

, 10

000 =

80dB

, 100000 =

100d

B

Rco

mp

:=

1k

leave this

fix

ed for

the m

odel

Cco

mp :=

1 / (

2!pi!

fpole

!R

com

p)

pla

ce

s the c

om

p p

ole

Cco

mp =

[53

0.5

165n]

DC

M L

inear M

od

el

of

Bu

ck

Con

verter

/---

----

Co

mp

en

sa

tor

----

----

/

/---

----

Filt

er

Inclu

din

g D

CM

Da

mp

ing

Re

sis

tan

ce

---

----

-/D

CM

Mo

du

lato

r

/---

----

Op

Am

p M

od

el --

----

--/

Load

Resis

tance


Figure 19. TINA SPICE Simulation Schematic of the Example Circuit (DCM Version)



CCM Spice and Calculated Results

(at Critical Conduction, R = 8 )W

-20dB

-10dB

0dB

10dB

20dB

30dB

40dB

50dB

60dB

70dB

10 100 1000 10000 100000 1000000

Frequency (Hz)

0°

30°

60°

90°

120°

150°

180°

210°

240°

270°

Spice Gain

Calculated Gain

Spice Phase

Calculated Phase

Ga

in

Ph

as

e

V - 3.48 VCC

V - 3.48 VUVLO

2 x(1)


Figure 20. Loop Gain and Phase for the Example Circuit, Using Both TINA (SPICE) and the Equations

Table 1. Design Parameters for Voltage Mode dc/dc Converters and ControllersMODULATOR RAMP ERROR AMP DC ERROR AMP VOLTAGEDEVICE CCM ONLY VOLTAGE VOLTAGE GAIN POLE REFERENCE

Equation Symbol → — Vramp ADC ωpole Vsense

Part numbers in Bold Italic are dual output converters.TPS40000 No 0.93V 18k 550Hz 0.700VTPS40001 Yes 0.93V 18k 550Hz 0.700VTPS40002 No 0.93V 18k 550Hz 0.700VTPS40003 Yes 0.93V 18k 550Hz 0.700VTPS40004 Yes 0.93V 18k 550Hz 0.700VTPS40005 Yes 0.93V 18k 550Hz 0.700VTPS40007 Yes 0.93V 18k 550Hz 0.700VTPS40009 Yes 0.93V 18k 550Hz 0.700VTPS40020 No 0.93V 18k 550Hz 0.690VTPS40021 Yes 0.93V 18k 550Hz 0.690VTPS40040 No 0.87V 18k 550Hz 0.600VTPS40041 Yes 0.87V 18k 550Hz 0.600VTPS40050 No 10k 500Hz 0.700VTPS40051 Yes 10k 500Hz 0.700VTPS40052 Yes 10k 500Hz 0.700VTPS40053 Yes 10k 500Hz 0.700VTPS40054 No 10k 500Hz 0.700VTPS40055 Yes 10k 500Hz 0.700VTPS40056 Yes 10k 500Hz 0.700VTPS40057 Yes 10k 500Hz 0.700VTPS40060 No 10k 1kHz 0.700VTPS40061 Yes 10k 1kHz 0.700V

(1) VUVLO is the programmed value of undervoltage lockout. See data sheet.



V - 0.4 VCC

V - 0.4 VUVLO

2 x(1)


Table 1. Design Parameters for Voltage Mode dc/dc Converters and Controllers (continued)MODULATOR RAMP ERROR AMP DC ERROR AMP VOLTAGEDEVICE CCM ONLY VOLTAGE VOLTAGE GAIN POLE REFERENCE


TPS40070 No 316 31kHz 0.700VTPS40071 Yes 316 31kHz 0.700VTPS40074 Yes 316 31kHz 0.700VTPS40075 Yes 316 31kHz 0.700VTPS40077 Yes 10k 1kHz 0.700VTPS40100 Yes 0.5V 10k 500Hz 0.690VTPS40190 Yes 0.75V 1k 5kHz 0.591VTPS40192 Yes 0.75V 1k 5kHz 0.591VTPS40193 Yes 0.75V 1k 5kHz 0.591VTPS40195 Yes 1.0V 1k 10kHz 0.591VTPS40200 No (Vcc / 20) – 0.15V 10k 300Hz 0.696VTPS43000 Pin Sel 1V ? (GBW = 5MHz) 0.800VTPS51020 Pin Sel 0..35V + 0.017 × VCC 10k 250Hz 0.850VTPS5124 No 0.68V 316 8kHz 0.850VTPS5410 No Internally Compensated (2) 1.221VTPS54110 Yes 1.0V 316k 16Hz 0.891VTPS5420 No Internally Compensated (2) 1.221VTPS5430 No Internally Compensated (2) 1.221VTPS54310 Yes 1.0V 316k 16Hz 0.891VTPS5431x Yes Internally Compensated (2) See (3)

TPS5435x Yes VCC / 8 10k 280Hz 0.891VTPS5450 No Internally Compensated (2) 1.221VTPS5455x Yes VCC / 8 10k 280Hz 0.891VTPS54610 Yes 1.0V 316k 16Hz 0.891VTPS5461x Yes Internally Compensated (2) See (3)

TPS54910 Yes 1.0V 316k 16Hz 0.891VTPS6211x Pin Sel Internally Compensated (2) 1.153VTPS54810 Yes 1.0V 316k 16Hz 0.891VTPS54972 Yes 1.0V 316k 16Hz ExternalTPS54980 Yes 1.0V 316k 16Hz 0.891VTPS54672 Yes 1.0V 316k 16Hz ExternalTPS54680 Yes 1.0V 316k 16Hz 0.891VTPS54010 Yes 1.0V 316k 16Hz 0.891VTPS6220x No Internally Compensated (2) 0.500VTPS6222x No Internally Compensated (2) 0.500VTPS6240x Pin Sel Internally Compensated (2) 0.600VTPS6210x Pin Sel 1.0V 10k 1kHz 0.800VTPS6230x Pin Sel Internally Compensated (2) 0.400VTPS6232x Pin Sel Internally Compensated (2) 0.400VTPS6200x Pin Sel Internally Compensated (2) 0.450VTPS6202x Pin Sel Internally Compensated (2) 0.500VTPS62420 Pin Sel Internally Compensated (2) 0.600V

(2) internally compensated device. Refer to the data sheet for acceptable component values.(3) Fixed output voltage versions, no external resistor divider is used.



2.1 Conclusions

2.2 Acknowledgments

2.3 References


Table 1. Design Parameters for Voltage Mode dc/dc Converters and Controllers (continued)MODULATOR RAMP ERROR AMP DC ERROR AMP VOLTAGEDEVICE CCM ONLY VOLTAGE VOLTAGE GAIN POLE REFERENCE


TPS6205x Pin Sel Internally Compensated (4) 0.500VTPS62350 Pin Sel Internally Compensated (4) ProgrammableTPS6204x Pin Sel Internally Compensated (4) 0.500V

(4) internally compensated device. Refer to the data sheet for acceptable component values.

Stabilizing a buck converter is a complicated control loop problem. The compensation block of a buckdc/dc converter is required to provide an acceptable degree of stability to the regulator circuit. Design ofthe compensator is complicated by the variety of output filter designs possible in modern electronicsystems. Solutions are presented for output filters with one, two, and three different types of capacitors(with different ESRs). A design example is presented which can be used as a template for analysis of anyvoltage mode buck converter. Because of the variety of integrated circuits available for buck converters,and the differences between them, a table is provided to summarize the data needed for the solutionspresented. For other integrated circuits, this data can be taken from the data sheet.

Note that TINA, a SPICE simulator [6] was used to generate several plots, and also to provide transferfunctions for the filter networks.

1. Under the Hood of Low-Voltage DC/DC Converters application report (SLUP206)2. Understanding Buck Power Stages in Switch Mode Power Supplies application report (SLVA057)3. Erickson, R, and Maksimovic, Dragan (2001). Fundamentals of Power Electronics. Assinippi Park,

Massachusetts: Kluwer Academic Publishers.4. Hale, F. J. (1973). Introduction to Control System Analysis and Design. New Jersey: Prentice-Hall, Inc.5. Vorperion, V. (1990).Simplified Analysis of PWM Converters using the Model of the PWM Switch, part

II: Discontinuous Conduction Mode. IEEE Transactions on Aerospace and Electronic Systems. 26,497-505.

6. DesignSoft, Kft. (2007). TINA (Industrial Version 7.0) [Computer software]. New York: Freeman.



http://www-s.ti.com/sc/techlit/SLVA057


Appendix A Filter Transfer Functions

L

R

C

R

VIN

RL

Vout

RC

k dd

2

21

1

1

/1

ˆ

ˆ

sasa

ssH

d

vz

d

o

++

+=

(A-1)

L

o

d

RRr

Rr

D

IH

++

×=2

(A-2)

÷÷ø

öççè

æ-×=

in

out

V

VRr 1

(A-3)

D

Ik

o

d

2=

(A-4)

Appendix A www.ti.com

This appendix gives the mathematical transfer functions as a function of frequency for some commonconfigurations. The output filter consists of an inductor, with loss, plus one or more types of outputcapacitors. When different types of output capacitors are used, the response of the filter can be complex.Adding together the total capacitance, and assuming that the ESRs are all in parallel, although making thefilter simpler, may not give an accurate solution. The ideal circuit model treats each capacitor separately,resulting in a more complex filter solution. The solutions for one-, two-, and three-output capacitor typesare given in the following discussion to be used in the loop response calculations.

Vorperion [5] derives the modulator and output filter transfer functions in DCM. His results are presentedin a form where the modulator and the output filter response are combined, and it may not be entirelyclear where the effects of the modulator end, and the filter begins. It is more convenient to separate theeffects of these two sections of the converter, so that the solution of the filter for CCM may be used to findthe solution of the filter in DCM. This greatly reduces the effort required to deduce the correct model forDCM, given a solution for the CCM filter.

It may be unclear why the filter response is different in CCM versus DCM. The difference lies in the natureof the modulator’s driving impedance. In CCM, the modulator’s output impedance is comparatively low, asit is made up mostly of the power switch losses, which are usually quite low by design (compared to thefilter impedance) at the switching frequency. In DCM, during a portion of each switching cycle, themodulator appears to have infinite impedance (both power switches are off). In this case, the averagemodulator output impedance may not be low enough to be negligible, when considering the filterresponse.

Vorperion’s model of the modulator and output filter is:

Figure A-1. Vorperion’s Model of the Modulator and Filter in DCM.

The transfer function of this DCM model is given as:

28 SLVA301–April 2008Submit Documentation Feedback


R

VI

out

o=

(A-5)

11

1

1

CRs

C

z=

(A-6)

( )[ ]LC

L

RrRRCRrR

La ++×+

++=

111

(A-7)

RrR

RRCLa

L

C

++

+=

1

12

(A-8)

2)()(

)()(

ˆ

ˆ

sCLRRsCRRRCRRCRLRR

sRCRRsH

v

v

CCLLCL

C

Filter

in

out

++××+××+××+++

××+==

(A-9)

L

R

C

rVIN

RL

Vout

RC

k drd

( )

2)(1

1

2

ˆ

ˆ

sRrR

CLRRs

RrR

RRCrRCCRRRCRrCRL

sRC

RrRD

RrI

d

v

L

C

L

LCLCC

C

LDCM

oout

÷÷ø

öççè

æ

+++

+÷÷ø

öççè

æ

+++++++

+

+

×++

=

(A-10)

www.ti.com Appendix A

D = the duty cycle of the modulator

In order to separate Vorperion’s result into a filter component and a modulator component, and show itsrelationship to the CCM case, start with the solution of the loss filter (the inductor and the capacitor eachhave a series resistance) in the CCM case (with an ideal voltage source):

Vorperion’s model uses a current source. If this is converted to an ideal voltage source with resistance,the model becomes:

Figure A-2. Vorperion’s DCM Model With an Ideal Voltage Source

This filter can be analyzed exactly as in the CCM case, exchanging RL for RL + r. Solving Vorperion’sequation in Equation A-1 results in:



result, along with a frequency-independent term÷÷ø

öççè

æ-

in

out

DCM

o

V

VD

rI

2

2

c

outramp

c

out

rampramp

c

outout

vd

Vdv

vd

Vd

vv

vd

Vd

Dd

Vd×=÷÷

ø

öççè

æ×=

÷÷

ø

ö

çç

è

æ=

1

1

(A-11)

( )

2)(1

1

2

ˆ

ˆ

sRrR

CLRRs

RrR

RRCrRCCRRRCRrCRL

sRC

RrRDV

RrI

v

v

L

C

L

LCLCC

C

LDCMramp

o

control

out

÷÷ø

öççè

æ

+++

+÷÷ø

öççè

æ

+++++++

+

+

×++

=

(A-12)

outrefV V

controV

Modulator Filter

Compensator

S

( )LDCMramp

o

RrRDV

RrI

++2

2)(1

1

sRrR

CLRRs

RrR

RRCrRCCRRRCRrCRL

sRC

L

C

L

LCLCC

C

÷÷ø

öççè

æ++

++÷÷ø

öççè

æ++

++++++

+


The second term in Equation A-10 is exactly the same result as the CCM filter response, after changingRL to RL + r. From this result it can be concluded that Vorperion’s DCM result contains the CCM filter

Vorperion’s excitation is taken as the duty cycle of the modulator block, rather than the control voltagewhich is the input to the modulator. It is convenient at this point to modify Vorperion’s result; refer to vc,the error amplifier output and the input to the modulator. The conversion can be made in this way:

Therefore, in order to express Vorperion’s result relative to the control voltage as an input rather than theduty cycle of the modulator, divide the result by vramp. Then Equation A-10 becomes:

Now, Vorperion’s result for the modulator plus filter has been separated into two components:The second term of Equation A-12 can be obtained by knowledge of the transfer function of thepassive output filter, making the substitution RL → RL + r, and then making the substitution for r givenin Equation A-3.The first term in Equation A-12 is frequency independent and can be treated as the modulator voltagegain, with its control input coming from the error amplifier. Although it may not be entirely accurate tocall this the modulator gain, it serves the purpose in that it is the block between the error amplifier andthe output filter, and it behaves as an ideal voltage source. Therefore, referring to this term is more of amathematical convenience for the purposes of using the block diagram of the generalized buckconverter shown in Figure A-3.

Figure A-3. General Block Diagram of a Buck Converter With DCM Modulator and Filter TransferFunctions



( )2

22

1

1

)(1

2

12

ˆ

ˆ

s

V

V

CLs

V

V

RRCV

VRC

R

L

sRC

V

VDv

V

VV

v

v

in

out

in

out

LC

in

out

C

in

outDCMramp

in

outout

control

out

-+

úúúúú

û

ù

êêêêê

ë

é

-

++÷÷ø

öççè

æ-+

+

+

×

÷÷ø

öççè

æ-

÷÷ø

öççè

æ-

=

(A-13)

÷÷ø

öççè

æ-

÷÷ø

öççè

æ-

=

in

outDCMramp

in

outout

DCM

V

VDv

V

VV

A

2

12

mod_

(A-14)

112

8

2

-÷÷ø

öççè

æ-

=

out

in

sw

DCM

V

V

R

fL

D

(A-15)


Another step of simplification can be made to Equation A-12. In DCM, the output (load) resistance isalmost certainly much larger than the dc resistance of the inductor or the capacitor; that is, R >>RC and R>> RL. Making this approximation, and also making a substitution for r as shown in Equation A-3,Equation A-12 reduces to:

In CCM, the assumption that the parasitic resistances are much smaller than R may not be valid.

Equation A-13 is the complete transfer function of the modulator plus output filter for a DCM buckconverter with a single type of output capacitor.

Although this discussion focuses on the output filter, note that the modulator in a DCM converter can bedescribed by the first term in Equation A-13, namely:

where DDCM is the duty cycle in DCM:

This DCM modulator gain is frequency independent and applies to all voltage mode buck designs,regardless of the complexity of the output filter.

In the following examples of DCM and CCM filters, the results are obtained as previously described,including the simplifications resulting from R >> RC and R >> RL in DCM.



a.L

R

C

V

R

in Vout

C

RL

b.

CCM Filter Response

21

)(1)(

sCLR

RRs

R

CRRCRCR

R

L

R

R

sRCsH

CCL

LC

L

C

CCMFilter

÷ø

öçè

æ ++÷

ø

öçè

æ +++++

+=-

c.

DCM Filter Response

2

1

2

1

1)(

s

V

V

CLsa

sCRsH

in

out

C

DCMFilter

-++

+=-

where

( )

in

out

LC

in

out

V

V

CRRV

VCR

R

L

a

-

++÷÷ø

öççè

æ-+

=2

1

1


Figure A-4. CCM and DCM Filter Transfer Functions for Filters with One Type of Output Capacitor



a.L

R

C C

V V

R R

R

in out

C1 C2

L

1 2

b.CCM Filter Response

c.DCM Filter Response

( ) ( )

( ) ( )[ ] ( )

( )[ ]2121213

221112122121212

2122111

3

3

2

21

2

11222211

1

)()(1)(

CCCC

CCCCCCL

L

CC

CCCC

Filter

RRRRRCCR

La

CRCRR

LCCRRRRCCRCCLa

CCR

RCRCR

R

Lawhere

sasasa

sCRCRsCRCRsH

++=

++++++=

++++=

++++++

=

3

3

2

21

2

11222211

1

)(1)(

sasasa

sRCRCRsCRCRsH

CCCC

Filter ++++++

=

( ) ( ) ( )

( ) ( )( ) ( )

( )[ ]

÷÷ø

öççè

æ-

++=

-

+÷÷ø

öççè

æ-+++++

=

-

+÷÷ø

öççè

æ-++++÷÷

ø

öççè

æ-+

=

in

out

CCCC

in

out

CC

in

out

CCCC

in

out

CC

in

out

CC

in

out

V

VR

RRRRRCLCa

V

V

RRCCV

VRCRCRRCRCL

a

V

V

RCRCV

VRCRC

R

L

V

VCCR

awhere

2

2

111

2

11

2121213

212122112211

2

2211221121

1


Figure A-5. CCM and DCM Filter Transfer Functions for Filters With Two Types of Output Capacitor



a.L

R

C C C

V V

R R R

R

in out

C1 C2 C3

L

1 2 3

b.CCM Filter Response

( ) ( )4

4

3

3

2

21

3

112233

2

223311331122332211

1

1

sasasasa

sCRCRCRsCRCRCRCRCRCRsCRCRCRH CCCCCCCCCCCC

CCMfilter ×+×+×+×++×+++×+++

=-

where:

( ) ( )

( )

( )[ ] ( )

( )[ ]( )

LCCCR

RRRRRRRRRa

CRCRCRCRCCRCCRCRCRCRCR

CRCRCRCRRCCRCCRCCRCRCCRCCRCCRCRR

La

CRCRCRR

LCRCRCRCRCRCRCCCL

CCRCCRCCRCRCCRCCRCRa

CRCRCRR

LCCCRa

CCCCCCCCC

CCCCCCCCCL

CCCCCCCCCCCC

CCCCCCCCC

CCCCCCL

CCCL

123

123

2313124

112233112331223311223

2233112223313312211311222311333

221133223311221133321

2331331221131122232

3322111231

×÷ø

öçè

æ +++=

++++

++++++++=

+++++++++

++++++=

++++++=


Figure A-6. CCM Filter Transfer Functions for Filters With Three Types of Output Capacitor (a, b)



c.DCM Filter Response

( ) ( )

in

out

CCCCCCCCCCCCDCMfilter

V

V

sasasasa

sCRCRCRsCRCRCRCRCRCRsCRCRCRH

-

++++

++++×+++=-

2

1

1

4

4

3

3

2

21

3

112233

2

223311331122332211

( ) ( )[ ]

( ) ( ) ( )[ ] ( ) ( )

( )

( ) ( ) ( )[ ]

( )

( )R

LCCCRRRRRRRRRRRRa

RRRRRRCCCV

VR

RRRCCCV

VRRCCRRCCRRCCLa

V

VCRCRCRCRCRCR

CRCRCRR

LCCCLRRCCRRCCRRCC

V

VRa

CRCRCRCCCRV

VCRCRCR

R

La

CCCCCCCCC

CCCCCC

in

out

CCC

in

outCCCCCC

in

outCCCCCC

CCCCCCCCC

in

out

CCC

in

outCCC

123

1232313124

132321321

3213213113211232233

223311221133

2211333213113211232232

3322111233322111

1

2

2

1

1

×+++=

++÷÷ø

öççè

æ-+

÷÷ø

öççè

æ-++++++=

÷÷ø

öççè

æ-+++

+++++++++++÷÷ø

öççè

æ-=

++++÷÷ø

öççè

æ-++++=


Figure A-7. DCM Filter Transfer Functions for Filters With Three Types of Output Capacitor (c)



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