Lab 2: Open Loop Buck Converter

EE 452: Power Electronics Design

Electrical Engineering Department

University of Washington

Section AB

Nasir Elmi 1468579

Daniel Park 1271113

Ki Hei Chan 1368010

October 26, 2015

1 Introduction The purpose of this lab is to use the theory of the buck converter to build one. This lab report is a follow up from the simulations and will focus on the hardware part. The simulation results will be presented again for comparison purposes and then the physical circuit will undergo tests that were similarly ran in simulations. Finally, these results will be presented to check if the built circuit will be able to replicate the results from the simulated circuit.

1.1 Design Specifications a) Input voltage: 10V DC

b) Output voltage: 5V DC

c) Maximum load: 1000 mA

d) Minimum load: 100 mA

e) Output Ripple Voltage 0.2 Vpp

f) Efficiency: > 75 % at Maximum Load

g) Converter frequency: 50 kHz – 200 kHz.

h) Worst case dynamic voltage change: 0.75 V

2 Design Using Simulation

2.1 Inductor Value Selection The following parameter values are given in Table 1 to find the inductor value needed for the design:

Table 1. Given and Set/Chosen Parameters for the Open­Loop Buck Converter

Parameter Value

Input Voltage 10 V (DC)

Output Voltage 5 V (DC)

Max Load Current 1000 mA

Min Load Current 100 mA

Peak­to­peak Ripple Voltage 0.2 V

Converter Frequency 50 kHz (chosen)

In order to find the inductor value needed, delta inductor current had to be found first using the following equation below:

.5 (1)D = V in

V out = 510 = 0

i .2A (2)∆ L = Lf s(V −V )Din out = (5)(0.5)

(50k)(250μH) = 0

Then, the delta inductor current value was used to find the inductor value. Because we chose our design to completely avoid discontinuous mode, the minimum load current was used in the following equation below:

50μH (3)Lcrit = 2I fomin s

(V −V )Din out = (10−5)(0.5)(2)(0.1)(50k) = 2

The end calculations presented that a 250 inductor was needed to fulfill the design.Hμ

2.2 Capacitor Value Selection Using the same parameters given in Table 1 and the delta inductor current, the following equation was used to find the capacitance value needed:

≥ .5μF (4)C ∆iL8V f0 s

= 0.2(8)(0.2)(50k) = 2

With the given equation above, the design needed a capacitor value of at least 2.5 F in parallel μ with the load. However, there are no 2.5 F capacitor values available; thus, a 3.3 F capacitor μ μ was used for the simulation.

3 Open Loop Buck Converter Design Figure 1 is the open loop buck converter design that will be built in this lab. The gate of the MOSFET is connected to a similar representation of the MC­34151 driver as it was not provided in MULTISIM, but is replaced by the drive in the actual circuit.

Figure 1. Open Loop Buck Converter Design (using Multisim)

4 Simulation Tests and Calculations Before building the actual hardware for the lab, some tests had to be run through Multisim to ensure that our design has met the specifications for this lab.

4.1 Varying Load Current

Figure 2. Transient Analysis of the Buck Converter at different currents

For the first set of tests, the load current was varied by putting in different resistors ranging from 5 Ω to 50 Ω. By observing the plots, the steady­state DC voltage is approximately 5V and the voltage ripples are within specifications as shown in Figure 2.

4.2 Inductor Current

Figure 3. Transient Analysis of the Buck Converter at different loads Figure 3 shows two plots of the current load at different loads. The green waveform represents the inductor current at high load current (Rload = 5 Ω) and the blue waveform represents the inductor current at low load current (Rload = 50 Ω). The average, steady­state currents are near what they should be in specifications. 4.3 Rapid Step Load Variation (Maximum to Minimum)

Figure 4. Transient Analysis of the output voltage ripple.

Figure 4 shows the output voltage when there is dynamic loading from maximum loading current to minimum loading current. As of now, this voltage spike is too high and needs to be addressed when building the hardware. One of the suggestions is to add a higher valued capacitor to reduce the dynamic voltage change.

4.4 Rapid Step Load Variation (Minimum to Maximum)

Figure 5. Transient Analysis of the output voltage ripple.

Similarly, Figure 5 shows the output voltage when there is dynamic loading from minimum loading current to maximum loading current. As of now, this voltage spike is too high and needs to be addressed when building the hardware. Mentioned before, adding a capacitor would be able to reduce this dynamic voltage change. 4.5 Maximum Load (Rload = 5 Ω) The sections below are analysis at maximum load current: 4.5.1 Voltage Ripple at Max Load

Figure 6. Transient Analysis of the output voltage ripple.

Figure 6 above shows the output voltage ripple at maximum load current. This plot shows that the voltage ripple ranges from 0 to 4% which is within the acceptable range for the design. 4.5.2 Efficiency at Max Load

Figure 7. Transient Analysis of the Efficiency

Figure 7 displays the efficiency of the circuit, which shows that once in steady state, the efficiency comes to be around 88%, which is above design’s requirement of 75% efficiency. Cursor values: Pin avg = 5.0448 W; Pout avg = 4.436 W

00% 7.93 % (5)η = P inPout * 1 = 8

4.6 MOSFET Waveform

Figure 8. Transient Analysis of the Vgs and Vds of the MOSFET, the voltage of the diode, and the output voltage

Figure 8 displays the drain to source voltage of the MOSFET, the voltage of the diode, and the voltage of the output. MOSFET turns on when the Vds is at least 10.65 V and the Vgs is at least 0.62 V. Thus, these values are the turn on settings for the MOSFET. Additionally, at these voltage settings, the diode is turned off (the blue waveform) and in reverse bias, which would also prove that the MOSFET is on in the buck converter.

5 Hardware Implementation With the simulation results and calculations shown, the hardware test will be presented as follows.

Before starting the hardware testing procedures, the inductor needed to be built using copper wiring and a core. The calculation for the number of turns is as follows:

39.16 (6) N =√ LAl = √ 163 10* −9250 10* −6

=

The result was rounded to 40 turns and the resulting inductance was around 252 uH.

In addition, the capacitance value was increased to 1800 uF to reduce the output voltage ripple and the dynamic voltage change, and a resistor of 1kΩ was added to the gate to smooth the gate voltage and to reduce spiking.

5.1 Varying Load Current

Table 2: Different parameters of the circuit when the load current is varied from minimum to maximum via change in load resistance

Rload(Ω) Vout(V) Iload(A) Vo/Vin

50 5.20 0.104 0.520

30 5.11 0.170 0.511

20 5.01 0.251 0.501

10 4.99 0.499 0.499

5 4.91 0.982 0.491

Table 2 summarizes the values of the load current and the ratio of the output and input voltages when the load current is varied from minimum to maximum via change in load resistance.

Figure 9. Load current vs Vo/Vin

Figure 9 shows the plot of the ratio of the output to the input voltage versus the load current. the above plot is very similar to the theoretical version of the graph. In addition, this plot shows how once load current reaches below a certain threshold, the circuit slowly goes into discontinuous conduction mode.

5.2 Inductor Current Figure 10 and 11 below show the current through the inductor for the highest and lowest load currents. Although our waveform had large spikes for every new switching cycle of the MOSFET due to transient effects of the switching, the ripple voltage without the peaks ranged from 0.1 to 0.2 V, which is within specifications of the design.

Figure 10 shows the inductor current at maximum load

Figure 11 shows the inductor current at minimum load.

5.3 Rapid Step Load Variation (Maximum to Minimum) Figure 12 shows the shows a waveform of Vo versus time for rapid (step) load variation from maximum to minimum. By using a higher capacitor as suggested from simulation, the dynamic voltage change dramatically reduced from 3.6 to 0.75 V.

Figure 12. Rapid load variation from max to min.

5.4 Rapid Step Load Variation (Minimum to Maximum) Figure 13 shows the shows a waveform of Vo versus time for rapid (step) load variation from minimum to maximum. Similarly, using the higher capacitor value reduced the dynamic voltage change from 7.5 V to at most 0.8 V.

Figure 13. Rapid load variation from min to max.

5.5 Maximum Load (Rload = 5 Ω) Similar to the simulation tests, the following are measurements/waveforms of the circuit when the circuit is operating a maximum load. 5.5.1 Output Voltage Ripple Figure 14 shows the Output waveform and output voltage ripple versus time at max load.

Figure 14. Output voltage vs. Time at Max Load.

The calculations for the output voltage ripple are as follows at maximum load:

I 982 .964 A (7)ΔiL = 2 Omax = 2 * . = 1

v 0.0027 V (8)Δ o = ΔiL8Cf s =

1.9648 (50kHz)(1800μF)* =

Although the measured output peak­to­peak voltage ripple are different from the calculated as done above, the measured output peak­to­peak voltage of 0.12 V is within the specifications of the lab.

5.5.2 Max Load Efficiency

Using the following measured parameters given below, the calculations for the efficiency are as follows:

VMaxLoad = 4.91V Vin = 10V Iout = 0.982 A IL = 0.54 A Pout = 4.822 W Pin = 5.4W RLoad = 5 ohm

Pout / Pin = Efficiency = 89.89% (9)

Calculations show that efficiency comes out to be around 89%, which is above the specification requirement of 75%.

5.6 Power Loop Losses

From the max load efficiency section, the measured power loss comes out to be 0.578 W. The following are the power dissipation for each element (note these are values at which the circuit has reached steady state):

MOSFET Dissipation: 0.081 W

Inductor Dissipation: 0.093 W

Capacitor Dissipation(ESR): 0.200 W

Diode Dissipation: 0.373 W

R_Gate Dissipation: 0.126 W

5.7 MOSFET Waveforms

Figure 15. Waveform of Vs(yellow), Vd(blue), and Vds(orange) of the MOSFET

As shown on Figure 15, the waveforms of the Vd, Vs, and Vds of the MOSFET were taken to observe the turn on behavior. Similar to the simulation, the MOSFET turns on when Vds = 10.2V and when the source voltage becomes negative, which would mean that the diode is in reverse bias. Although not pictured in the waveform, through calculations from the measurements of the waveform, the MOSFET turns on when Vgs = 0.58 V.

5.8 Varying Vcc (Supply Voltage)

Figure 16. Output voltage at which Vcc = 10V

Additionally, the test was done to see what effect the output voltage would have if the supply voltage were to decrease. In this case, the supply voltage decreased from 16V to 10V and consequently, the output voltage decreased by 1.6 V (DC). This is the case because this would decrease the output from the driver and in turn decrease Vgs. Consequently, the source current that is fed into the inductor would decrease. Overall, this effectively reduces the current that passes through the load, which in turn decrease the output DC voltage.

5.9 ESR Calculations

Figure 17. Test Circuit to find the ESR of C1

In order to calculate the ESR for one of the capacitor, the test circuit in Figure 17 was used. With the capacitor nearly fully charged, the decay behavior needed to be observed when R2 = 1Ω & 2Ω. Figure 18 and Figure 19 display both decay behaviors. With these graphs, two points were able to be extracted, respectively.

Figure 18. Exponential Decay Behavior with R2 = 1Ω

Figure 19. Exponential Decay Behavior with R2 = 2Ω

Then using the following functions below, the tau values were able to be calculated along with the ESR.

.39Eτ1 = 9 − 4

.41Eτ2 = 1 − 3

R21 = 1Ω, R22 = 2Ω

With all the calculations, ESR value of the 470 uF comes out to be approximately 0.99Ω, which is high and expected of a high­capacitance­valued, electrolytic capacitor.

3 Conclusion By using the current knowledge of the open­loop buck converter, the parameters including the capacitor and the inductor values needed were able to be found. Then we ran simulation tests in order to prove that most of the circuit design was sufficient. The actual circuit was then built with new adjustments as suggested from the simulation, which included adding a gate resistor and a higher valued capacitor. As a result, the dynamic voltage change was greatly reduced to within lab specifications along with the spiking. Overall, running the simulations and testing the actual buck­converter circuit enabled us to learn the intricacies of the design, which helped us improve our initial design and fix most of the problem associated with the hardware.