litho and design: moore close than evermoore close than everispd.cc/slides/2011/8.2_singh.pdf ·...
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![Page 1: Litho and Design: Moore Close Than EverMoore Close Than Everispd.cc/slides/2011/8.2_Singh.pdf · PILOT LINE $1-2 B R&D PROCESS TEAM $0.5-1 B Source: Intel The ... OPC model Illumination](https://reader036.vdocuments.us/reader036/viewer/2022081615/5fdc38dd62e5c41bf4435ef0/html5/thumbnails/1.jpg)
Vivek SinghVivek SinghIntel FellowIntel Fellow
Director, Computational LithographyDirector, Computational Lithography
Technology Manufacturing GroupTechnology Manufacturing Group
Litho and Design: Litho and Design: Litho and Design: Litho and Design: Litho and Design: Litho and Design: Litho and Design: Litho and Design: Moore Close Than Moore Close Than Moore Close Than Moore Close Than Moore Close Than Moore Close Than Moore Close Than Moore Close Than EverEverEverEverEverEverEverEver
Technology Manufacturing GroupTechnology Manufacturing Group
Intel CorporationIntel Corporation
ISPD , March 2011
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Gasp!Gasp!
22V. Singh, ISPD , March 2011
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OutlineOutline
�� The frenetic pace of Moore’s Law, The frenetic pace of Moore’s Law,
and why we put up with it!and why we put up with it!
��How the coHow the co--optimization of design and optimization of design and
lithography have enabled Moorelithography have enabled Moore
33V. Singh, ISPD , March 2011
lithography have enabled Moorelithography have enabled Moore
��How computational lithography is How computational lithography is
squeezing more juice out of stepperssqueezing more juice out of steppers
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The Economics of Moore’s LawThe Economics of Moore’s Law
TheBenefit:
101010101010101055
101010101010101066
101010101010101077
101010101010101088
101010101010101099
10101010101010101010
As the number As the number of transistors of transistors
goesgoes UP
Price per Price per transistor goestransistor goes
DOWN
1010101010101010
1010101010101010--------55
1010101010101010--------44
1010101010101010--------33
1010101010101010--------22
1010101010101010--------11
101010101010101000
$$
44V. Singh, ISPD , March 2011
Source: Source: WSTS/Gartner/IntelWSTS/Gartner/Intel
FAB $4 B
PILOT LINE $1-2 B
R&D PROCESS TEAM $0.5-1 BSource:
Intel
TheCost:
Investment & co-optimized execution required to maximize the benefit
101010101010101033
101010101010101044
’70’70 ’80’80 ’90’90 ’00’00
1010101010101010--------66
1010101010101010
1010101010101010--------77
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Intel’s Silicon R&D PipelineIntel’s Silicon R&D Pipeline
15 15 nmnm 22 22 nmnm 32 32 nmnm 45 45 nmnm
55V. Singh, ISPD , March 2011
Continuous flow of new technologies from
research to development to manufacturing
Pathfinding Development ManufacturingResearch
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OnOn--time 2 Year Cyclestime 2 Year Cycles
32 nm2009
90 nm2003
45 nm2007
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again.
65 nm2005
22 nm2011
66V. Singh, ISPD , March 2011
InIndevelopmentdevelopment
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Defect Density TrendsDefect Density Trends
Defect Density
(Log Scale)
90nm 65nm 45nm 32nm
HigherYield
77V. Singh, ISPD , March 2011
2001 2002 2003 2004 2005 2006 2007 2008 2009
Continuing to improve wafer defect density is crucial to achieving historical yield trends
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Breakthroughs in Technology Information Breakthroughs in Technology Information TurnsTurns
Info
rmat
ion T
urn
s
90nm
65nm
45nm
32nm
88V. Singh, ISPD , March 2011
Info
rmat
ion T
urn
s
20022001 2003 2004 2005 2006 2007 2008
1.7 X improvement in Information turns Faster information back to process development and design teams
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SRAM Cell Size ScalingSRAM Cell Size Scaling
1
10C
ell A
rea
(um
2 )
65 nm, 0.570 um2
99V. Singh, ISPD , March 2011
0.01
0.1
1995 2000 2005 2010 2015
Cel
l Are
a (u
m
0.5x every 2 years
32 nm, 0.171 um 2
45 nm, 0.346 um 2
22 nm, 0.092 um 2
All Patterned with 193nm!!
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TickTick--tock: an example from Intel of process tock: an example from Intel of process and design marching in cadenceand design marching in cadence
2 YEARS
2 YEARS
TOCK Core 2 processor, Xeon processor
TICK Pentium® D, Xeon™, Core™ processor
2 YEARS
2 YEARS
45nm
TICK PENRYN Family
65nm
1010V. Singh, ISPD , March 2011
2 YEARS
2 YEARS
2 YEARS
2 YEARS
TOCK NEHALEM
TOCK SANDY BRIDGE
32nm
TICK WESTMERE
45nm
All product information and dates are preliminary and subject to change without notice
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Design Rule Definition Process:Design Rule Definition Process:How Litho and Design are connectedHow Litho and Design are connected
DR Modeling
And Process evaluation
DOF, MEEF, etc
1 D Pitch target set by density goals
Learning from previous process
extrapolated OPC model
Illumination techniques
OPC/litho test masks
Modify older test chip
1111V. Singh, ISPD , March 2011
DOF, MEEF, etc
Design rules
Photo resist evaluation
techniques
Enhancement techniques
X test chip
Layout
studies
Product Evaluation
CAD
tools
C. Webb, SPIE 2007
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Rule StabilityRule Stability
60.00%
80.00%
100.00%
120.00%
Growth
in
Number
X Chip Tape out
1212V. Singh, ISPD , March 2011
0.00%
20.00%
40.00%
0
Relative Year
Number
of
Rules
-1-2
First Design Debug Ramp
Process Development
+1 +2
C. Webb, SPIE 2007
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130nm 130nm
1313V. Singh, ISPD , March 2011
�� Variable poly pitch and line widths Variable poly pitch and line widths
�� X and Y transistor orientation X and Y transistor orientation
�� Design rule definition was primarily done through simple Design rule definition was primarily done through simple scaling of rules from previous generationscaling of rules from previous generation
�� Limited modeling of layout and design rulesLimited modeling of layout and design rules
SRAM Bit
C. Webb, SPIE 2007
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90nm 90nm 47% increase in number of poly rules47% increase in number of poly rules
1414V. Singh, ISPD , March 2011
�� All Devices in one orientation except SRAMAll Devices in one orientation except SRAM
�� Complex rules did not impact transistor densityComplex rules did not impact transistor density–– Modeling and layout study effort increased from 130nm generationModeling and layout study effort increased from 130nm generation
SRAM Bit
C. Webb, SPIE 2007
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65nm65nm65% increase in number of rules65% increase in number of rules
�� All Devices in one orientation including SRAMAll Devices in one orientation including SRAM
�� Rules to enable phase shift masksRules to enable phase shift masks
�� Different rules for minimum pitch, larger poly pitch and poly routingDifferent rules for minimum pitch, larger poly pitch and poly routing
�� Layout more difficult but no significant density impactLayout more difficult but no significant density impact
1515V. Singh, ISPD , March 2011
SRAM
C. Webb, SPIE 2007
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Problems Problems with 65nm with 65nm poly layoutpoly layout
Poly corners affecting devices
Two direction routing
1616V. Singh, ISPD , March 2011
Multiple poly widths
Variable poly pitch
Could all logic poly layout be simple like the SRAM bit? C. Webb, SPIE 2007
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45nm Logic Layout45nm Logic Layout37% reduction in number of rules37% reduction in number of rules
One direction
Trench contact local routing replaces orthogonal to gate poly
1717V. Singh, ISPD , March 2011
�� No significant density impactNo significant density impact
�� Design had to adapt to limited channel length choices Design had to adapt to limited channel length choices and new layout styleand new layout style
One Pitch with poly on grid
orthogonal to gate poly routing
C. Webb, SPIE 2007
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Layout has adapted to litho constraints, without affecting Moore’s march
65 nm Layout Style 32 nm Layout Style
1818V. Singh, ISPD , March 2011
• Bi-directional features
• Varied gate dimensions
• Varied pitches
• Uni-directional features
• Uniform gate dimension
• Gridded layoutM. Bohr, ISCC, 2009
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0.346 µm2 Cell 193 nm Dry Lithography0.10.1
11
1010
100100
Cell Area Cell Area
(um(um22))
0.5x every 0.5x every 2 years2 years
What matters is Best Total Cost What matters is Best Total Cost
45nm Cell45nm Cell0.346 um20.346 um2
Density reduction at Density reduction at Lowest cost and TTMLowest cost and TTM
SRAM SRAM -- Functional silicon in Jan ‘06Functional silicon in Jan ‘06SRAM Cell SizeSRAM Cell Size
1919V. Singh, ISPD , March 2011
193 nm Dry Lithography0.10.1
19921992 19941994 19961996 19981998 20002000 20022002 20042004 20062006 20082008
Critical Layer Lithography Cost ComparisonCritical Layer Lithography Cost Comparison45nm Node assuming equal yield45nm Node assuming equal yield
0.90.9
11
1.11.1
1.21.2
1.31.3
193nm Dry193nm Dry 193nm Immersion193nm Immersion
ForecastForecast
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MultiMulti--mask patterning mask patterning –– a friend in needa friend in need
�� As wafer dimensions reach optical As wafer dimensions reach optical limits, multilimits, multi--mask patterning came to mask patterning came to rescuerescue
�� Works well for simple repeated Works well for simple repeated patternspatterns
2020V. Singh, ISPD , March 2011
�� Not so well with general patternsNot so well with general patterns
Does not resolve Problem at corners
Overlay issues
Modify design –does it impact performance?
� Need complex design rules to capture multi-mask conflicts
� Design tools need to be multi-mask aware to minimize impact
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One implication of Double-patterningMisalignment
Normalized IDSAT
2121V. Singh, ISPD , March 2011
Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability
Transistor parameters can be affected by asymmetry between the source and drain regions
Print 1 Print 2 Registration (nm) K. Kuhn, ICVC, 2009
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Pitch doubling and gate CD matching
A A
B
A
B BB1266
12641262
860
SR
AM
Vcc
min
2222V. Singh, ISPD , March 2011
Pitch doubling eliminates the close correlation which currently exists between the CDs of
adjacent gates
This has implications for memory cells and other circuits which depend upon this CD
matching
Gate CD mismatch σσσσC. Kenyon, TOK conf., Dec. 2008
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NGL solutions can help contain rising NGL solutions can help contain rising cost of double patterningcost of double patterning
2323V. Singh, ISPD , March 2011
Source: ITRS 2009
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0.1
1
micron 100
1000
nm
193 nm248 nm
LithographyWavelength
65 nmFeature
365 nm
436 nm
Computational lithography Computational lithography –– enabling Mooreenabling Moore
2424V. Singh, ISPD , March 2011
0.011980 1990 2000 2010 2020
10
32 nm45 nmFeature
Size22 nm EUV
13 nm15 nm
Computational lithography innovations and co-optimization with design necessary to
bridge this gap
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2D Effects Become Important2D Effects Become Important
2525V. Singh, ISPD , March 2011
Rule-based serif placement were first instance of on-mask pattern manipulation to deliver design intent
S. Sivakumar, SPIE, 2011
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One CL product: One CL product: pixelatedpixelated masksmasks
Design Pattern Model black-box
2626V. Singh, ISPD , March 2011
Pixelated maskSEM image of wafer
Atomic Force Microscope Picture of the mask
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A FullA Full--Chip View is worth a trillion pixelsChip View is worth a trillion pixels
2727V. Singh, ISPD , March 2011
Note: some cells are not visible due to graphics cullingTop-cell pixels are not displayedOnly 0-deg pixels are displayed
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Convert pixelated mask to more Convert pixelated mask to more manufacturablemanufacturable mask, mask, while while preserving preserving
performanceperformancepixelated mask More manufacturable mask
2828V. Singh, ISPD , March 2011
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Two pronged approach: Two pronged approach:
simplify simplify inverse masksinverse masksimprove improve mask shop capabilitiesmask shop capabilities
2929V. Singh, ISPD , March 2011
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Optimizing Source and MaskOptimizing Source and Mask
Source OptimizationSource Optimization
++
Source Mask OptimizationSource Mask Optimization
3030V. Singh, ISPD , March 2011
Computational Lithography is a key enabler for extracting maximum resolution
from existing technology
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Atomic Force Microscope Picture of Pixelated Phase Mask
SEM Picture of 65nm MT1 resist Pattern from Pixelated Phase Mask
Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic Ultimately, the proof is in the pudding. Exotic techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.techniques need to be viable for production.
3131V. Singh, ISPD , March 2011
Defect free Pixelated Phase Masks produced, Leading 65nm node Microprocessor patterned at MT1 with Pixelated Phase Mask yielded close to manufacturing baseline
Computational lithography is helping extract more resolution from existing technology
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Other things being equal, you can measure Other things being equal, you can measure CL innovation through compute costCL innovation through compute cost
Cost savingsfrom CL innovations
?
Rel
ativ
e co
st
10000000
1000000
100000
10000
A new node increases compute cost due to increase i n:� number of OPC layers� density� required computational accuracy� model accuracy needs� convergence difficulty� Number of OPC features
3232V. Singh, ISPD , March 2011
Technology node
Rel
ativ
e co
st
65 45 32 22 15
1
10
10000
1000
100
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Future Technology DirectionsFuture Technology Directions
More MooreCMOS
3333V. Singh, ISPD , March 2011
2000 2010 2020 2030
New device technology will be needed by 2020M. Bohr, SPIE, 2011
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Future Technology DirectionsFuture Technology Directions
More MooreCMOS
New ApplicationsDigital + analog + optical
Silicon + III-VElectrical + Mechanical
3434V. Singh, ISPD , March 2011
2000 2010 2020 2030
New device technology will be needed by 2020M. Bohr, SPIE, 2011
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Future Technology DirectionsFuture Technology Directions
More MooreCMOS
New ApplicationsDigital + analog + optical
Silicon + III-VElectrical + Mechanical
3535V. Singh, ISPD , March 2011
2000 2010 2020 2030
New TechnologiesCarbon Based?
Spintronics?Magnetic Domains?Molecular Switches?
New device technology will be needed by 2020M. Bohr, SPIE, 2011
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What What will will be printed?be printed?
3636V. Singh, ISPD , March 2011
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3737V. Singh, ISPD , March 2011
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ConclusionConclusion
“No exponential is
forever … but we can
delay ‘forever’.”
3838V. Singh, ISPD , March 2011
Gordon MooreISSCC
2003