lic manual new

7/24/2019 LIC Manual New

1/84

Ex.no:1 APPLICATIONS OF OP-AMP.

A. Inverting amplifier

AIM: To designInverting Amplifier using operational amplifier IC741 and to test itsoperation.

APPAAT!S E"!IE#:

T$EO%:

An inverting amplifier uses negative feedback to invert and amplifya voltage.The Rfresistor allos some of the output signal to be returned to the input. !ince theoutput is 1"#$ out of phase% this amount is effectively subtracted from the input% therebyreducing the input into the operational amplifier. This reduces the overall gain of the

amplifier and is dubbed negative feedback..The gain of the inverting amplifier is&ain 'Av( ) *o + *i ) , Rf + R1-egative !ign indicates a phase shift of 1"#beteen *i and *o.

Therefore *out is eual to

*o ) , Rf + R1 '*in(

POCE#!E:

1.Connections are made as per circuit diagram.

/. !et sine ave input voltage at any fi0ed voltage and fi0ed freuency say% 1* 'p,p( and

1 23 respectively.

. 5bserve the input and output aveform simultaneously using 6ual Trace CR5.

4. Tabulate the readings and verify it using theoretical calculations.

. 6ra the input and output aveforms in &raph sheet.

!.-5 A88ARAT9! RA-&: ;9A-TIT2? 1 CR5 #>2? 1

4 6ual 8oer supply @ 1* 1

Resistor 1#k%1##k 1%1B read oard , 17 Dires , As Reuired
http://en.wikipedia.org/wiki/Amplifierhttp://en.wikipedia.org/wiki/Amplifier


2/84

#ESI&N:

De kno that%*o+*i) ,Rf+Ri

Dhere%*i ) *oltage applied at inverting terminal%*o ) 5utput voltage.Ri ) Input Resistor.Rf ) =eedback Resistor.

Assume%&ain) ,1#%Ri ) 1#k%,1#)Rf+1#k

Rf ) 1##

CIC!IT #IA&AM:

CO

+

-E>741

F1/*

,1/*

/

B

7

4

1' (p-p)

Sine I*P

O+tp+t

I-*:RTI-& A>8EI=I:R

Rf )1##

F&, 1$

Ri ) 1#


3/84

MO#EL EA#IN&:

Inp+t:

Amplit+/e : 0 'Time perio/ : m2

O+tp+t:

Amplit+/e : 0 '

Time perio/ : m2

MO#EL &AP$:

Inp+t:

O+tp+t:


4/84

TA3!LATION: IN'ETIN& AMPLIFIE

Amplit+/e Timeperio/

I-89T /v 1ms

59T89T /v 1ms

ES!LT:

Thus designed the inverting amplifier using IC 741 and testes its operation.


5/84

3. Non-Inverting amplifier

AIM:

To design-on, inverting Amplifier using operational amplifier IC741 and to test itsoperation.

APPAAT!S E"!IE#:

T$EO%:

2ere%the output is in the same as the input signal% i.e. hen the input voltagegoes positive% so does the output. In this circuit the signal is applied to the non,invertinginput of the op,amp. 2oever the feedback is taken from the output of the op,amp via aresistor to the inverting input of the operational amplifier here another resistor is takento ground. It is the value of these to resistors that govern the gain of the operationalamplifier circuit. As the input to the op,amp dras no current this means that the currentfloing in the resistors R1 and R/ is the same.

The voltage at the inverting input is formed from a potential divider consisting ofR1 and R/% and as the voltage at both inputs is the same% the voltage at the inverting inputmust be the same as that at the non,inverting input. This means that

*in ) *out 0 R1 + 'R1 F R/(.

2ence the voltage gain of the circuit Av can be taken asG

Av 4 1 5 0 * 1

!.-5 A88ARAT9! RA-&: ;9A-TIT2? 1 CR5 #>2? 1


Resistor 1#k%1##k 1%1B read oard , 17 Dires , As Reuired


6/84

POCE#!E:

1.Connections are made as per circuit diagram./. !et sine ave input voltage at any fi0ed voltage and fi0ed freuency say% 1* 'p,p( and1 23 respectively.. 5bserve the input and output aveform simultaneously using 6ual Trace CR5.4. Tabulate the readings and verify it using theoretical calculations.. 6ra the input and output aveforms in &raph sheet.

#ESI&N:

*o+*i )1F 'Rf+Ri(here &ain ) *o+*i

Assume &ain ) 11% Eet Ri ) 1#k%11) 1F 'Rf+1#k(Rf ) 1##k

CIC!IT #IA&AM:

F&, 1$

-5-,I-*:RTI-& A>8EI=I:R

Sine I*P

1' (p-p)

+

-E>741

F1/*

,1/*

/

B

7

4

Rf )1##

O+tp+t

Ri ) 1#

CO


7/84

MO#EL EA#IN&:

Inp+t:

Amplit+/e : 0 '

Time perio/ : m2

O+tp+t:

Amplit+/e : 0 '

Time perio/ : m2

MO#EL &AP$:

Inp+t:

O+tp+t:


8/84

TA3!LATION: NON-IN'ETIN& AMPLIFIE


I-89T 4v 1ms

59T89T 4v 1ms

ES!LT:

Thus designed the -on, Inverting amplifier using IC 741 and testes its operation.


9/84


10/84

a( In common mode *1 ) */ ) *

*c ) )*

Ac )

*d) *1,*/ )*,* )#b( In difference mode

*1 ) ,*/ ) * *d ) *1,*/) *F* )/*

Ad )

*c ) ) ) #

CIC!IT #IA&AM:

MO#EL EA#IN&:

Inp+t 1 :

Amplit+/e : 'Time perio/ : m2

Inp+t 0 :

Amplit+/e : 0 '

Time perio/ : m2

O+tp+t:


11/84

Amplit+/e : 0 '

Time perio/ : m2

MO#EL &AP$:

Inp+t:

O+tp+t:

TA3!LATION: #IFFEENTIAL AMPLIFIE


I-89T *5ETA&: 1#mv 1ms

I-89T *5ETA&: mv 1./ms


12/84

59T89T *5ETA&: mv 1.Bms

CALC!LATION:

Input Amplitude)/Jmv)1#mv

Time)1J1ms)1ms

5utput Amplitude)1Jmv)mv

Time)#."J/ms)1.Bms

C>RR)Ad+AcK

Ad)v/, v1+/),1#+/)/.dbK

Ac)v/Fv1+/)F1#+/)7.dbK

C>RR)/.+7.)#. db

ES!LT:

Thus designed the 6ifferential amplifier using IC 741 and tested its operation.

'iva 6+e2tion2 an/ an27er2:

1. >ention some of the linear applications of op L amps G

Adder% subtractor% voltage Lto, current converter% current Lto, voltage converters%instrumentation amplifier% analog computation %poer amplifier% etc are some of thelinear op,amp circuits.

/. >ention some of the non L linear applications of op,ampsGRectifier% peak detector% clipper% clamper% sample and hold circuit% log amplifier%

anti Llog amplifier% multiplier are some of the non L linear op,amp circuits.

. Dhat are the areas of application of non,linear op, amp circuitsG

Industrial instrumentation


13/84

!ignal processing

4. Dhat does 74E! refers toG

74,refers to IC hich can be used for commercial purpose.E!,Eo 8oer!chottky.. Dhat is Einear ICM

IC hich accepts% process and produce analog signal is called linear IC.:gGIC741%IC.B. 6efine C>RR

Common mode reection ratio,it is defined as the ratio beteen the differentialmode gain to the common mode gain


14/84

:0.noG/ INTE&ATO AN# #IFFEENTIATO

A. Integrator

AIM:

To designIntegrator and 6ifferentiator using operational amplifier IC741 and to testthe operation.

APPAAT!S E"!IE#:

T$EO%:

Integrator produces a voltage output proportional to the product

'multiplication( of the input voltage and time. 2ere% the op,amp circuit ould generate an

output voltage proportional to the magnitude and duration that an input voltage signal has

deviated from # volts. A simple lo pass RC circuit can also ork as an Integrator hen

time constant is very large. This reuires very large values of R and C.

The components R and C cannot be made infinitely large because of practical

limitations. 2oever in the op,amp integrator by >illerHs theorem% the effective input

capacitance becomes Cf '1,Av(% here Av is the gain of the 5p,amp.

A88ARAT9! RA-&: ;9A-TIT2? 1 CR5 #>2? 14 6ual 8oer

supply@ 1/* 1

Resistor 1.Bk%47# k /%1B Capacitor #.#1Nf 17 read oard , 1" Dires , As Reuired


15/84

The &ain 'Av( is the infinite for an ideal 5p,amp% so the effective time constant

of the 5p,amp Integrator becomes very large hich results perfect integration.

POCE#!E:

1. Construct the circuit as per Circuit diagram shon in figure./. !elect the !uare aveform in =unction &enerator and set fi0ed amplitude and

fi0ed freuency say 1* 'p,p( and 1 23 respectively.

. The resistance Rcomp is also connected to the -on,inverting input terminal to

minimi3e the effect of the input bias current.

4. -ote the corresponding input and output signals.

. -ote the gain of the integrator decreases ith increasing freuency.

B. Tabulate the noted readings and dra the input and output aveforms in &raph

sheet.

#ESI&N:

The Integrator output voltage can be e0pressed as%*5 ) ,1+Rf O*i dt

=or Integration% T)/PR1cf% f)11 k23% cf )#.1Nf

T ) 1+f ) 1m!


16/84

:

MO#EL EA#IN&:

Inp+t:

Amplit+/e : 0 '

Time perio/ : m2

O+tp+t:

Amplit+/e : 0 '

Time perio/ : m2

MO#EL &AP$:

Inp+t Signal (1 $ Fre6.)

('olt2)

F&, 1$

O+tp+t

INTE&ATO CIC!IT

1

#.1N=

1' (p-p)

1

S6+are I*P

1#

+

-E>741

F1/*

,1/*

/

B

7

4

CO


17/84

Time (m2)

Time (m2)

O+tp+t Signal (1 $ Fre6.)

Amplit+/e

('olt2)

Time (m2)

TA3!LATION: INTE&ATO


I-89T *5ETA&: 4mv 1./ms

59T89T *5ETA&: "mv 1#ms


18/84


19/84

T$EO%:

The name implies% is used to perform the mathematical operation ofdifferentiation. The output aveform is the derivative of input aveform..Thedifferentiator 'not to be confused ith differential( produces a voltage output proportionalto the input voltageQs rate of change.

At high freuencies differentiator may become unstable and break into oscillation. Theinput impedance decreases ith increase in freuency thereby making the circuit

sensitive to high freuency noise. The feedback netork of the differentiator% R1C1% is anRC lo pass filter hich contributes #S phase shift to the loop and may cause stabilityproblem ith an amplifier hich is compensated for unity gain.

POCE#!E:

1. Construct the circuit as per Circuit diagram shon in figure.

/. !elect the !uare aveform in =unction &enerator and set fi0ed amplitude and

fi0ed freuency say 1* 'p,p( and 1 23 respectively.

. The resistance Rcomp is also connected to the -on,inverting input terminal to

minimi3e the effect of the input bias current.

4. -ote the corresponding input and output signals.

. Tabulate the noted readings and dra the input and output aveforms in &raph

sheet.

#ESI&N:

The 6ifferentiator output voltage can be e0pressed as%*o ) RfJc 'd*in+dt(

=or 6ifferentiation T )/PRfc1% =)1 k23% c1 ) #.1Nf

T ) 1+f ) 1m! Rf ) T+/Pc1


20/84

CIC!IT #IA&AM:

# . 1 N =

1 #

# I F F E E N T I A T O C I C ! I T

O + t p + t

F & , 1 $ .

C O1 ' ( p - p )

1

+

-E > 7 4 1

F 1 / *

, 1 / *

/

B

7

4

S 6 + a r e I * P

MO#EL EA#IN&:

Inp+t 1:Amplit+/e : 8 '

Time perio/ : m2

Inp+t 0:

Amplit+/e : 9 '

Time perio/ : m2

O+tp+t:

Amplit+/e : 0 '

Time perio/ : m2

MO#EL &AP$:

Inp+t Signal (1 $ Fre6.)

('olt2)


21/84

Time (m2)

Time (m2)

O+tp+t Signal (1 $ Fre6.)

Amp

('olt2)

Time(m2)

TA3!LATION: #IFFEENTIATO


I-89T *5ETA&: 4mv 1./ms


22/84

59T89T *5ETA&: "mv 1ms

ES!LT:

Thus designed the 6ifferentiator using IC 741 and tested its operation.

Appliation2:

1.The 6C voltage produced by the differentiator circuit could be used to drive acomparator hich ould signal as alarm or active a control if the rate of change e0ceededa pre,set level.

/.Daveform &enerators

'iva 6+e2tion2 an/ an27er

1.Dhat are the limitations of the basic differentiator circuitG

At high freuency% a differentiator may become unstable and break intooscillations. The input impedance decreases ith increase in freuency % thereby makingthe circuit sensitive to high freuency noise.

/.Drite don the condition for good differentiation G,

=or good differentiation% the time period of the input signal must begreater than or eual to Rf C1 %T R f C1 Dhere% Rf is the feedback resistance

.Dhat is an ICGThe term IC refers to comple0 :lectronic circuits consisting of a large number of

components on a single substrate.

4.Dhat are the advantage of ICGCost reduction%Increased operating speed%Reduced poer consumption and

Improved functional performance.

.Dhat are the different IC technologiesG>onolithic technology and 2ybrid technology


23/84

:0.noG INST!MENTATION AMPLIFIE

AIM:

To designInstrumentation Amplifier using IC741 and to test the operation.

APPAAT!S E"!IE#:

!.-5 A88ARAT9! RA-&: ;9A-TIT2? / CR5 #>2? 1


8otentiometer 1# k 1

B Resistor 1k B7 read oard , 1" Dires , As Reuired


24/84

T$EO%:

The special amplifier% hich is used for lo level amplification ith high C>RR% highinput impedance to avoid loading % lo poer conception. Instrumentation amplifiercircuit provides high input resistance for accurate measurement of signals fromtransducers. In this circuit a non,inverting amplifier is added to each of the basicdifference amplifier inputs.

The 5p,amp A1 and A/ are the non,inverting amplifiers forming the input or first stageof the instrumentation amplifier and 5p,amp A is normal difference forming an outputstage of the amplifier.

=eatures of an Instrumentation AmplifierG 2igh gain and accuracy 2igh C>RR 2igh gain stability ith lo temperature co,efficient Eo 6C offset Eo output impedance

POCE#!E:

1. Construct the circuit as per Circuit diagram shon in figure.

/. !itch 5- the 8oer !upplies and apply the Input *oltages .

. 5bserve the 5utput *oltage for different input voltages.

4. -ote the readings and verify its values ith theoretical calculation.

#ESI&N:

=or instrumentation amplifier%

Eet R1) R/ ) R ) Rgain ) 1# then

*out ) '1F/( '*/,*1(

*out ) '*/,*1(


25/84

CIC!IT #IA&AM:

MO#EL EA#IN&:

Inp+t '1:Amplit+/e : '

Time perio/ : m2

Inp+t '0:

Amplit+/e : 1 '

Time perio/ : m2

1#

+

-LM;1

F1/*

,1/*

/

B

7

4

/

////*1

1#

1#1#

+

-LM;1

F1/*

,1/*

/

B

7

4

O+tp+t

#MM

1#

INST!MENTATION AMPLIFIE !SIN& ;1 IC.

1#

+

-LM;1

F1/*

,1/*

/

B

7

4

1#


26/84

O+tp+t '

?e @no7 tat,

'< 4 A/'/5A '

So A/ 4 '< *'/4 0 * 1.>

4 1.08

A 4 '< *'4 0 * 9.0408

CM 4 0< log (A/* A )

4 0< log ( 1.08 * 08 )

4

MO#EL &AP$:

Inp+t 1:


27/84

Inp+t 0:

O+tp+t:


28/84

TA3!LATION:


29/84

S.NO

INP!T

'OLTA&E

IN

'OLTS('1)

INP!T

'OLTA&E

IN

'OLTS('0)

COMMON

MO#E

&AIN(AC)

#IFFEENTIAL

MO#E

&AIN(A/)

CM

IN /B4023( 14 >ultimeter 1 Resistors 1## U

B U

/

1B Capacitors #.1 Vf% #.#1 Vf :ach one7 Regulated poer supply '# ,#*(%1A 1

T$EO%:

The circuit shos an inverting comparator ith positive feed back. This circuit

converts orbitrary ave forms to a suare ave or pulse. The circuit is knon as the

!chmitt trigger 'or( suaring circuit. The input voltage *inchanges the state of the output

*oevery time it e0ceeds certain voltage levels called the upper threshold voltage * utand

loer threshold voltage *lt.

Dhen *o) , *sat% the voltage across R1is referred to as loer threshold voltage%

*lt. Dhen *o)F*sat% the voltage across R1 is referred to as upper threshold voltage

*ut.The comparator ith positive feed back is said to e0hibit hysterisis% a dead band

condition.

CIC!IT #IA&AM:


48/84

Fig 1: Smitt trigger ir+it +2ing IC ;1

Fig 0: Smitt trigger ir+it +2ing IC 888

#ESI&N:

*utp ) [R1+'R1FR/(\'F*sat(

*ltp ) [R1+'R1FR/(\',*sat(

*hy ) *utpL *ltp

)[R1+'R1FR/(\ [F*satL ',*sat(\#ESI&N CALC!LATIONS IF AN%:


49/84

*9T) R1 + 'R1FR/( J 'F*sat(

*ET) R1 + 'R1FR/( J ',*sat(

F*sat ) F*cc ) F1* and ,*sat ) ,*cc ) ,1*

Eet R1 ) /./ and R/)//# then

*9T) /./ + '/./F//#( J 'F1(

*ET) /./ + '/./F//#( J ',1(

?A'E FOMS:

Fig1 : (a) Smitt trigger inp+t 7ave form

(B) Smitt trigger o+tp+t 7ave form


50/84

POCE#!E:

1. Connect the circuit as per the circuit diagram./. Apply an orbitrary aveform 'sine+triangular( of peak voltage greater than 9T8 to the

input of a !chmitt trigger.. 5bserve the output at pinB of the IC 741 and at pin of IC !chmitt trigger circuit by

varying the input and note don the readings as shon in Table4. =ind the upper and loer threshold voltages '*utp% *Etp( from the output ave form.

TA3!LATION: SC$MITT TI&&E


I-89T #v ms

59T89T 1./v5- TimeG./Vs

5== TimeG ./Vs

ES!LT:

Thus designed the !chmitt trigger circuit using IC 741 Timer and tested its operation.

'iva "+e2tion2 An27er2:

1. Dhat is the other name for !chmitt trigger circuitM


51/84

Regenerative comparator

/. In !chmitt trigger hich type of feedback is usedM

8ositive feedback.

. Dhat is meant by hysteresisM

The comparator ith positive feedback is said to be e0hibit hysteresis% a deadband

condition. Dhen the input of the comparator is e0ceeds *utp% its output sitches from

F *satto , *satand reverts back to its original state%F *sat %hen the input goes

belo *ltp

4. Dhat are effects of input signal amplitude and freuency on outputM

The input voltage triggers the output every time it e0ceeds certain voltage levels

'9T8 and ET8(. 5utput signal freuency is same as input signal freuency.

Exp. No : > C P$ASE S$IFT OSCILLATO !SIN& OP-AMP ;1 IC.

AIM:

To 6esign and construct RC 8hase !hift 5scillator Circuit using IC 741 and

observe its output aveform.


52/84


53/84

#ESI&N:

fo ) 1 + B '/ R C (

Rf / R1

C ) #.#1=% fo ) ## 23.

R ) 1 + B '/ f C ( ) 1 k

Therefore% Choose R ) 1k

To prevent loading%

R1 1# R

R1 )1# R ) 1# k.

Rf ) 4. >

MO#EL &AP$:

CR5

R1)1#k

Rf )47#k

R ) 1. k

C )#.#1=

t

T


54/84


55/84

'iva 6+e2tion2 an/ an27er2:

1. Dhat happens hen the common terminal of *F and *, sources is not groundedMIf the common point of the to supplies is not grounded% tice the supply voltage

ill get applied and it may damage the op,amp.

/. 6efine C>RR of an op,amp.The relative sensitivity of an op,amp to a difference signal as compared to a

Common Lmode signal is called the common Lmode reection ratio. It is e0pressed indecibels.

C>RR) Ad+Ac

. Dhat are the reuirements for producing sustained oscillations in feedback circuitsM=or sustained oscillations%. The total phase shift around the loop must be 3ero at

the desired freuency of oscillation% . At fo% the magnitude of the loop gain should beeual to unity

4. >ention any to audio freuency oscillatorsG RC phase shift oscillator Dein bridge oscillator

. 6efine analog signalDhen the amplitude of a signal varies continuously ith respect to time%the signal

is called analog.

B. 6efine discrete signal.Dhen a signal is defined only at discrete instants of time%the signal is called

discrete signal..

Exp. No: >(B) ?IEN 3I#&E OSCILLATO !SIN& OP-AMP ;1 IC.

AIM:

To 6esign and construct Dien ridge 5scillator Circuit using IC 741 and observeits output aveform.APPAAT!S E"!IE#:


56/84

S.NO #ESCIPTION AN&E "!ANTIT%

1 58,A>8 IC,741 1

/ Resistor 1B% /%1.% 1/

Capacitor #.1f

/

4 CR5 , 1 R8! 69AE'#,#( * 1

T$EO%:

A Dien bridge oscillator is a type ofelectronic oscillatorthat generates sine aves

ithout having any input source. It can output a large range of freuencies. The bridgecomprises four resistorsand to capacitors. The circuit is based on a netork originally

developed by >a0 Dienin 1"1.

In Dien bridge oscillator% ein bridge circuit is connected beteen the amplifier

input terminals and output terminals. The bridge has a series RC netork in one arm and

parallel netork in the adoining arm. In the remaining / arms of the bridge resistors

R1and Rf are connected. To maintain oscillations total phase shift around the circuit must

be 3ero and loop gain unity. =irst condition occurs only hen the bridge is balanced.

Assuming that the resistors and capacitors are eual in value% the resonant freuency of

balanced bridge is given by + the freuency of oscillation is given byG

#ESI&N:

At the freuency the gain reuired for sustained oscillations is given by

1FRf +R1 ) or Rf ) /R1 =o ) #.B+RC and Rf ) /R1

CALC!LATION:

Theoretical
http://en.wikipedia.org/wiki/Electronic_oscillatorhttp://en.wikipedia.org/wiki/Electronic_oscillatorhttp://en.wikipedia.org/wiki/Sine_wavehttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Max_Wienhttp://en.wikipedia.org/wiki/Electronic_oscillatorhttp://en.wikipedia.org/wiki/Sine_wavehttp://en.wikipedia.org/wiki/Resistorhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Max_Wien


57/84

=r ) 1+'/J.14JRJC(8racticalG

= ) 1+TCIC!IT

#IA&AM

POCE#!E:

1. Connections are made as per the diagram./. R%C%R 1%Rfare calculated for the given value of fo using the design .. 5utput aveform is traced in the CR5.



58/84


59/84


1 IC 1/ Capacitors #.1Vf%#.#1Vf :ach one Resistor 1#kU 1

4 Regulated 8oer supply '# L #*(%1A 1 =unction &enerator '12? L 1>23( 1B Cathode ray oscilloscope '# L /#>23( 1

T$EO%G

A >onostable >ultivibrator% often called a one,shot >ultivibrator% is a pulse,

generating circuit in hich the duration of the pulse is determined by the RC netork

connected e0ternally to the timer. In a stable or stand by mode the output of the

circuit is appro0imately ?ero or at logic,lo level. Dhen an e0ternal trigger pulse is

obtained% the output is forced to go high ' *CC(. The time for hich the output remains

high is determined by the e0ternal RC netork connected to the timer. At the end of the

timing interval% the output automatically reverts back to its logic,lo stable state. The

output stays lo until the trigger pulse is again applied. Then the cycle repeats. The

>onostable circuit has only one stable state 'output lo(% hence the name monostable.

-ormally the output of the >onostable >ultivibrator is lo.


60/84

CIC!IT #IA&AM:

Fig 1: Mono2taBle Cir+it +2ing IC888

#ESI&N:

Consider *CC) *% for given tp

5utput pulse idth tp) 1.1 RAC

Assume C in the order of microfarads Y =ind RA


61/84

Tpial val+e2:

If C)#.1 N= % RA ) 1#k then

tp) 1.1 m!ec

Trigger *oltage )4 *

?A'EFOMS:

Fig (a): Trigger 2ignal

(B): O+tp+t 'oltage

(): Capaitor 'oltage

TA3!LATION: MONOSTA3LE M!LTI'I3ATO



62/84


63/84

4. Dhat is the effect of *cc on outputM

The amplitude of the output signal is directly proportional to *cc

. Dhat are the ideal charging and discharging time constants 'in terms of R and C( of

capacitor voltageM

Charging time constant T)1.1RC !ec

6ischarging time constant)# !ec

B. Dhat is the other name of monostable >ultivibratorM DhyM

i( &ating circuit .It generates rectangular aveform at a definite time and thus

could be used in gate parts of the system.

ii( 5ne shot circuit. The circuit ill remain in the stable state until a trigger pulse

is received. The circuit then changes states for a specified period% but then it returns to

the original state.7. Dhat are the applications of monostable >ultivibratorM

>issing 8ulse 6etector% =reuency 6ivider% 8D>% Einear Ramp &enerator


64/84

ED.NO: ;(B) IC 888 TIME - ASTA3LE OPEATION CIC!IT

AIM:

To generate unsymmetrical suare and symmetrical suare aveforms using

IC.

APPAAT!S E"!IE#:


1 IC 1/ Resistors .BkU%7./] :ach one Capacitors #.1Vf%#.#1Vf :ach one4 6iode 5A7 1 Regulated 8oer supply '# L #*(%1A 1B Cathode Ray 5scilloscope '# L /#>23( 1

T$EO%:

Dhen the poer supply *CCis connected% the e0ternal timing capacitor ^C_

charges toards *CCith a time constant 'RAFR( C. 6uring this time% pin is high

'`*CC( as Reset R)#% !et !)1 and this combination makes Q )# hich has unclamped

the timing capacitor ^CH.

Dhen the capacitor voltage euals /+ *CC% the upper comparator triggers the

control flip flop on that Q )1. It makes ;1 5- and capacitor ^CH starts discharging

toards ground through Rand transistor ;1 ith a time constant RC. Current alsoflos into ;1 through RA. Resistors RAand Rmust be large enough to limit this current

and prevent damage to the discharge transistor ;1. The minimum value of RA is

appro0imately eual to *CC+#./ here #./A is the ma0imum current through the 5-

transistor ;1.


65/84

6uring the discharge of the timing capacitor C% as it reaches *CC+% the loer

comparator is triggered and at this stage !)1% R)# hich turns Q )#. -o Q )#

unclamps the e0ternal timing capacitor C. The capacitor C is thus periodically charged

and discharged beteen /+ *CCand 1+ *CC respectively. The length of time that the

output remains 2I&2 is the time for the capacitor to charge from 1+ *CCto /+ *CC.

The capacitor voltage for a lo pass RC circuit subected to a step input of *CC

volts is given by *C) *CC[1, e0p ',t+RC(\

Total time period T ) #.B 'RAF / R( C

f) 1+T ) 1.44+ 'RAF /R( C

CIC!IT #IA&AM:

Fig. 888 A2taBle Cir+it

#ESI&N:

=ormulaeG f) 1+T ) 1.44+ 'RAF/R( C

6uty cycle '6( ) tc+T ) RAF R+'RAF/R(

MO#EL CALC!LATIONS:

&iven f)1 23. Assuming c)#.1V= and 6)#./

1 23 ) 1.44+ 'RAF/R( 0 #.101#,Band #./ )' RAFR(+ 'RAF/R(

!olving both the above euations% e obtain RAY Ras

RA) 7./ U


66/84

R) .B U

?A'EFOMS:

Fig (a): !n2mmetrial 26+are 7ave o+tp+t

(B): Capaitor voltage of !n2mmetrial 26+are 7ave o+tp+t

(): Smmetrial 26+are 7ave o+tp+t

POCE#!E:

I) !n2mmetrial S6+are 7ave


67/84

1. Connect the circuit as per the circuit diagram shon ithout connecting the

diode 5A 7.

/. 5bserve and note don the aveform at pin B and across timing capacitor.

. >easure the freuency of oscillations and duty cycle and then compare ith the

given values.

4. !ketch both the aveforms to the same time scale.

II) Smmetrial 26+are 7aveform generator:

1. Connect the diode 5A7 as shon in =igure to get 6)#. or #./. Choose Ra)Rb) 1#U and C)#.1f. 5bserve the output aveform% measure freuency of oscillations and the duty

cycle and then sketch the o+p aveform.

TA3!LATION: ASTA3LE M!LTI'I3ATO


I-89T #mv Bms

59T89T /.4v 4."

ES!LT:

Thus designed the Astable multivibrator using IC Timer and tested its operation.


68/84

'iva "+e2tion2 An27er2:

1. Dhat is the effect of C on the outputM

Time period of the output depends on C

/. 2o do you vary the duty cycleM

y varying RAor R.

. Dhat are the applications of in astable modeM

=! &enerator% 8ulse 8osition >odulator% !uare ave generator

4. Dhat is the function of diode in the circuitM

To get symmetrical suare ave.

. 5n hat parameters Tcand Td designedM

RA%R and C

B. Dhat are charging and discharging timesMs

The time during hich the capacitor charges from '1+( *cc to '/+( *cc

is eual to the time the output is high is knon as charging time and is given by

Tc)#.B'RAFR( C

The time during hich the capacitor discharges from '/+( *cc to '1+(

*cc is eual to the time the output is lo is knon as discharging time and is given

by Td)#.B'R( C.


69/84

Exp. No: (a) C$AACTEISTICS OF PLL.

AIM:

To construct and study the operation of 8EE IC B and determine its Characteristics.

Apparat+2 e6+ire/:

!.-o ComponentsRange ;uantity

1 IC B , 1/ Resistors B." 1 Capacitors #.##1 =

#.1 =% 1 =

1 each

4 =unction &enerator '123 L 1>23.( 1 C.R.5 , 1B 6ual 8oer !upply #, # * 1

Cir+it #iagram:

5 > '

1 >. C 4 1 F

C1 4


70/84

Pin #iagram (IC 8>8 - PLL)

- 'CC 1 1 NC

Inp+t 0 19 NC

O+tp+t 9 10 NC

IC 8>8

'CO I*P 11 NC

'CO O*P 8 1< 5 'CC

O+tp+t > G 'CO CT

#emo/+late/ ; 'CO T

O+tp+t

Proe/+re:

The connections are given as per the circuit diagram. >easure the free running freuency of *C5 at pin 4% ith the input signal *i

set eual to 3ero. Compare it ith the calculated value ) #./ + 'RT CT(. -o apply the input signal of 1 *88 suare ave at a 1 23 to pin /.

Connect one channel of the scope to pin / and display this signal on the scope.

&radually increase the input freuency till the 8EE is locked to the inputfreuency. This freuency f1 gives the loer end of the capture range. &o onincreasing the input freuency% till 8EE tracks the input signal% say% to afreuency f/.This freuency f/ gives the upper end of the lock range. If inputfreuency is increased further% the loop ill get unlocked.

-o gradually decrease the input freuency till the 8EE is again locked. Thisis the freuency f% the upper end of the capture range. eep on decreasing theinput freuency until the loop is unlocked. This freuency f4 gives the loerend of the lock range.

The lock range fE ) 'f/ L f4(.Compare it ith the calculated value

of 7." fo + 1/ .Also the capture range is fc ) 'f L f1(.Compare it ith thecalculated value of capture range.

o fc ) 'fE + '/('.B('1#( C(1+/


71/84

TA3!LATION: PLL


I-89T #mv #ms

59T89T 1Bmv .Bms

e2+lt :

Thus the 8EE circuit is constructed and its Characteristics are determined.


72/84

Exp. No : (B) FE"!ENC% M!LTIPLIE !SIN& PLL.

AIM:

To construct and study the operation of freuency multiplier using IC B.

Apparat+2 e6+ire/:

S.No Component2ange "+antit

1 IC 8>8,IC ;Geasure the output freuency. It should be times the input freuency.

B. Repeat steps 4% for input freuency of 1 k23 and 1. k23.


73/84

Cir+it #iagram:

1

2

3

1 9

5

4

7

81 0

2

3

2 k o h m

2 0 k o h m

+ 6 v

1 0 M f

+ 6 v

1 1

2 3 6 7 1 0

1

1

2 N 2 2 2 21 0 k o h m

4 . 7 k o h m

- 6 v

0 . 0 1 M f

v i n

V C O O u t p u t

F o 5 f i n

5 6 5

7 4 9 0! " 5 #

$ %

$ %

$ %

C 1

0 . 0 0 1 M f

C

TA3!LATION:FE"!ENC% M!LTIPLIE


74/84


I-89T #mv #ms

59T89T 1Bmv .Bms

e2+lt :

Thus the freuency multiplier circuit using 8EE is constructed and studied.

'iva 6+e2tion2 an/ an27er2

1. >ention the applications of 8EE=reuency multiplier=reuency synthesi3er=reuency translationClock and data recovery

/. Dhat is a voltage controlled oscillatorM

*oltage controlled oscillator is a free running multivibrator operating at a setfreuency called the free running freuency. This freuency can be shifted to either sideby applying a dc control voltage and the freuency deviation is proportional to the dccontrol voltage.. Dhat are the applications of *C5M

*C5 is used in =>% =!% and tone generators% here the freuency needs to be

controlled by means of an input voltage called control voltage.4. Dhat is 8EEM

8EE is a control system that generates an output signal hose phase is related to

the phase of input Reference signal.

Ex.No: G #C PO?E S!PL% !SIN& LM91; AN# LM;09

AIM:

To design and test the dc poer supply using E>17and E>7/


75/84

.APPAAT!S E"!IE#:

T$EO%:

This is a positive variable poer supply that is compact and easy to build. It isideal for poering any application reuiring a 6C supply at current levels up to 1.A.This poer supply proect should be among the first proect that all electronic hobbyistshould embark on. Dith this poer supply% one can use it to poer up many electronickits and proects instead of usingbatteries.The features of E>17 circuit areG

5utput reverse polarity and back,voltage protectionE:6 poer on indication*ariable output voltageACor 6C input voltageEo noise

The features of E>7/ circuit areG 1# mA output current ithout e0ternal pass transistor 5utput currents in e0cess of 1#A possible by adding e0ternal transistors Input voltage 4#* ma0 5utput voltage adustable from /* to 7* Can be used as either a linear or a sitching regulator

!.-5 A88ARAT9! RA-&: ;9A-TIT17 , 1 8oer supply @1/* 14 CR5 #>2? 1 Transformer 1B Capacitor #.#1Vf 7 Resistor #U%1kU%47kU%

1#kU%1kU:ach 1%%1

" 8otentiometer 1#kU E:6 1" =unction

&enerator, 1

Resistor 1# /1# Dires !ingle stand As Reuired
http://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.htmlhttp://www.electronics-project-design.com/VariableDCPowerSupply.html


76/84

#ESI&N:

The output voltage is calculated byG*'out( ) 1./'1 F *R1+R1(

The design formula areG*59T ) 1./ '1 F R/+R1( volts% or alternativelyR/+R1 ) '*59T+1./( , 1

PIN CONFI&!ATIONG

6C 85D:R !988E< 9!I-& E>17


77/84

6C 85D:R !988E< 9!I-& E>7/G

POCE#!E:

1. !et up the circuit.


78/84

/. !itch on the input supply and input voltage source.

. *ary the input from B* to 1* and observe the output voltage.

4 *ary the rheostat and note the change in the output.

. 6ra the regulation characteristics ith input along ,a0is and

output along 17% E> 7/M4# *

4. Dhat is the output voltage of E>17% E> 7/M1./* to 4*% /* to 7*

ES!LT:

Thus the dc poer supply using E>17and E>7/ is constructed and studied.

Ex.No:1< ST!#% OF SMPS


79/84

AIM:

To !tudy the !>8! Control circuits using !&/4+!&/.

SMPS ontrol ir+it S&980

#ESCIPTIONThis monolithic integrated circuit contains all the control circuitry fora regulating poersupply inverter or sitching regulator. Included Ina 1B,pin dual,in,line package is thevoltage reference% error amplifier% oscillator% pulse,idth modulator% pulse steering flip,flop% dual alternating output sitches and current,limiting and shut don circuitry. Thisdevice can be used for sitching regulators of either polarity% transformer,coupled 6C,to,6C converters% transformer less voltage doublers and polarity converters% as ell as otherpoer control applications.

PIN CONFI&!ATION

6% =% -8ackages T58 *I:D

1 I-*:RT I-89T

/-5-,I-* I-89T

5!C 59T89T

4 'F(CE !:-!:

'L(CE !:-!:

B&R59-6

7 RT

"CT

*R:=

1#*I-

11:>ITT:R

1/ C5EE:CT5R 1 C5EE:CT5R A

14 :>ITT:R A1B !29T65D-

!29T65D-1 C5>8:-!ATI5-

T$EO% OF OPEATION

'oltage eferene


80/84

An internal series regulator provides a nominal * output hich is used both togenerate a reference voltage and is the regulated source for all the internal timing andcontrolling circuitry. This regulator may be bypassed for operation from a fi0ed *supply by connecting 8ins 1 and 1B together to the input voltage. In this configuration%the ma0imum input voltage is B.#*.

O2illatorThe oscillator in the !&/4 uses an e0ternal resistor 'RT( to establish a constantcharging current into an e0ternal capacitor 'CT(. Dhile this uses more current than aseries,connected RC% it provides a linear ramp voltage on the capacitor hich is also usedas a reference for the comparator. The charging current is eual to .B * and should bekept ithin the appro0imate range of #NA to /mAK i.e.% 1."kWRTW1##k. The range ofvalues for CT also has limits as the discharge time of CT determines the pulse,idth ofthe oscillator output pulse. This pulse is used 'among other things( as a blanking pulse toboth outputs to insure that there is no possibility of having both outputs on!imultaneously during transitions. This output dead time relationship is shon in =igure. A pulse idth belo appro0imately #.Ns may allo false triggering of one output by

removing the blanking pulse prior to the flip,flopHs reaching a stable state. If small valuesof CT must be used% the pulse,idth may still be e0panded by adding a shunt capacitanceto ground at the oscillator output. ['-oteG Although the oscillator output is a convenientoscilloscope sync input% the cable and input capacitance may increase the blanking pulse,idth slightly.(\ 5bviously% the upper limit to the pulse idth is determined by thema0imum duty cycle acceptable. 8ractical values of CT fall beteen #.##1 and #.1N=.The oscillator period is appro0imately t)RTCT here t is in microseconds. The use of=igure B ill allo selection of RT and CT for a ide range of operating freuencies.-ote that for series regulator applications% the to outputs can be Connected in parallelfor an effective #,# duty cycle and the freuency of the oscillator is the freuency ofthe output. =or push,pull applications% the outputs are separated and the flip,flopdivides the freuency such that each outputHs duty cycle is #,4 and the overallfreuency is one,half that of the oscillator.External Snroniation

If it is desired to synchroni3e the !&/4 to an e0ternal clock% a pulse of F*may be applied to the oscillator output terminal ith RTCT set slightly greater than theclock period. The same considerations of pulse,idth apply. The impedance to ground atthis point is appro0imately /kU. If to or more !&/4s must be synchroni3ed together%one must be designated as master ith its RTCT set for the correct period. The slavesshould each have an RTCT set for appro0imately 1# longer period than the master iththe added reuirement that CT'slave()one,half CT 'master(. Then connecting 8in on allunits together ill insure that the master output pulseZhich occurs first and has a iderpulse idthZill reset the slave units.

Error Amplifier

This circuit is a simple differential input transconductance amplifier. The output isthe compensation terminal% 8in % hich is a high,impedance node .The gain is A* g>RE " IC RE /kT #.##/RE and can easily be reduced from a nominal of 1#%### byan e0ternal shunt resistance from 8in to ground. In addition to 6C gain control% thecompensation terminal is also the place for AC phase compensation. Therefore% the best


81/84

stabili3ing netork is a series RC combination beteen 8in and ground hichintroduces a 3ero to cancel one of the output filter poles. A good starting point is #kU

plus #.##1N=.

Pilip2 Semion/+tor2 Pro/+t 2peifiation

SMPS ontrol ir+it S&980

5ne final point on the compensation terminal is that this is also a convenient placeto insert any programming signal hich is to override the error amplifier. Internalshutdon and current limit circuits are connected here% but any other circuit hich cansink /## A can pull this point to ground% thus shutting off both outputs. Dhile feedbackis normally applied around the entire regulator% the error amplifier can be used ithconventional operational amplifier feedback and is stable in either the inverting or non,inverting mode. Regardless of the connections% hoever% input common,mode limitsmust be observed or output signal inversions may result. =orconventional regulator applications% the * reference voltage must be divided don as

shon in =igure ". The error amplifier may also be used in fi0ed duty cycle applicationsby using the unity gain configuration shon in the open,loop test circuit.C+rrent Limiting

The current limiting circuitry of the !&/4 is shon in =igure . y matchingthe base,emitter voltages of ;1 and ;/% and assuming a negligible voltage drop acrossR1G Threshold)*:';1(FI1R/,*:';/( )I1R/ /##m* Although this circuitprovides a relatively small threshold ith a negligible temperature coefficient% there aresome limitations to its use% the most important of hich is the 1* common,mode rangehich reuires sensing in the ground line. Another factor to consider is that the freuencycompensation provided by R1C1 and ;1 provides a roll,off pole at appro0imately##23. !ince the gain of this circuit is relatively lo% there is a transition region as thecurrent limit amplifier takes over pulse idth control from the error amplifier. =or testingpurposes% threshold is defined as the input voltage reuired to get / duty cycle iththe error amplifier signaling ma0imum duty cycle. In addition to constant currentlimiting% 8ins 4 and may also be used in transformer,coupled circuits to sense primarycurrent and to shorten an output pulse% should transformer saturation occur. Anotherapplication is to ground 8in and use 8in 4 as an additional shutdon terminalG i.e.% theoutput ill be off ith 8in 4 open and on hen it is grounded.

=:AT9R:!Complete 8D> poer control circuitry!ingle ended or push,pull outputsEine and load regulation of #./1 ma0imum temperature variationTotal supply current is less than 1#mA5peration beyond 1##k23

!>8! using !&/G


82/84

There are three main blocks described belo ...A , !itching >5!=:Ts and transformer , Rectification and filteringC , Control circuitry

A - S7iting MOSFET2 an/ Tran2former

The selected sitching topology is called a push,pull converter% because thetransformer has a double primary 'or a centre,tapped one% if your prefer(. The centretap is permanently connected to the car battery 'via an EC filter to avoid creating peaks inthe battery lines% hich could affect other electronic euipment in the car(. The to ends

of the primary are connected to a pair of paralleled >5!=:Ts each that tie them toground in each conduction cycle '*gs of the corresponding >5!=:T high(.These >5!=:Ts should be fast% able to ithstand high currents 'in e0cess of #A each ifpossible( and have the loest possible Rds'on(. The proposed 5n,!emiconductorHs>T87-#B can ithstand 7Amp and has a Rds'on( belo 1# milliohm. This isimportant% because the loer this resistance is% the less poer they are going to dissipatehen sitching ith a suare aveform. Another alternatives are >T8B#-#B% or themore popular 9?11 and IR=4#.


83/84

Although the schematics sho a previous bipolar push,pull stage% you can also connectthe gate resistor directly to the output of the controlling IC% leaving out the transistors% asthe !&/ is capable to drive up to ## mA 'theoretically(% more than enough to sitchthe >5!=:Ts fast.3 - etifiation an/ Filtering

If one looks to the secondary side of the !>8!% it resembles e0actly the schemeof a typical mains 8!9% ith one fundamental difference , the sitching diodes have tobe =A!T or 9ETRA=A!T% if you use a standard diode bridge the system ill simply bloup 'and this can be very impressive% believe me( Although a diode bridge is represented%it can be made ith discrete diodes as ell. 9se high current '1# A minimum and asuitable voltage rating( diodes. I recommend using 4 0 T5//# double diodes that can beparalleled to form a single one in each package.5T: from the head unit%for e0ample(.In this proect% layout is critical% incorrect track idths or e0cessively long traces canhave high inductances and produce peaks that can make the >5!=:Ts blo up. :!8 illprobably offer a suitable 8C layout if there is enough interest in it.

ES!LT:

Thus the !>8! using !&/4 and !&/ ere studied.


84/84

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