lic manual m

LINEAR INTEGRATED CIRCUITS LABIndex

Exp.No

Date Experiment Name Page No

1 Amplifiers1.1 Inverting amplifier and Non inverting amplifier1.2 Differential amplifier2 Applications of Amplifiers2.1 Integrator2.2 Differentiator3 Instrumentation amplifier4 Active Filter4.1 Lowpass filter4.2 Highpass filter4.3 Bandpass filter5 Multivibrators using op-amp5.1 Astable multivibrators using op-amp5.2 Monostable multivibrators using op-amp5.3 Schmitt Trigger6 Oscillators using op-amp6.1 Wien bridge oscillator 6.2 Phase shift oscillator7 Multivibrators using NE555 Timer7.1 Astable multivibrators using NE555 Timer7.2 Monostable multivibrators using NE555 Timer

8PLL characteristics and its use as Frequency Multiplier

9 DC power supply9.1 DC power supply using LM3179.2 DC power supply using LM72310 Study of SMPS11 Simulation of Experiments using PSpice Netlists11.1 Instrumentation amplifier11.2 Active lowpass, Highpass and bandpass filters.

11.3Astable & Monostable multivibrators and Schmitt Trigger using op-amp

11.4 Phase shift and Wien bridge oscillators using op-amp

11.5Astable and monostable multivibrators using NE555 Timer

1

1. Title

2. Aim

3. Apparatus required (S.No , Apparatus Name , Range , Quantity)

4. Components required (S.No , Components Name , Range , Quantity)

5. Theory

6. Procedure

7. Pin diagram

8. Design

9. Circuit diagram

10.Model Graph

11.Tabulation

12.Calculation

13.Output graph

14.Result

2

Exp.No: INVERTING AMPLIFIER AND NON INVERTING AMPLIFIER Date:

Aim:To design and test the operation of Inverting, Non inverting amplifier and

Differential amplifier.

Apparatus Required:

Sl.No Apparatus Name Range Quantity1 Dual power supply (0-32)V 12 Function Generator (0-3)MHz 13 CRO (0-30)MHz 1

Components Required

Sl.No Components Range Quantity1 Resistors 1K,10K,100K,40KΩ Each one2 Op_amp IC741 13 Connecting wires ----- As required

Theory:

Op-amps have 5 basic terminals, two input terminals, one output terminal and two power supply terminals.

Characteristics of an Ideal Op-amp

1) Open loop voltage gain, Ao = 2) Input impedence Ri = 3) Output impedence Ro = 04) Bandwidth BW= 5) Zero offset, i.e. Vo = 0 when V1 = V2 = 0

1. Inverting Amplifier:

This is the most widely used of all op-amp circuits. Here, the output voltage Vo is

fed back to the inverting input terminal through the R f - R1 network where Ri is the

feedback resistor. Input signal Vi is applied to the inverting terminal through R1 and non

inverting input terminal of op-amp is grounded. The output voltage Vo is given by,

3

2. Non - Inverting Amplifier:

If the signal is applied to the inverting input terminal and feedback is given, the

circuit amplifies without inverting the input signal. Such a circuit is called

non - inverting amplifier circuit. It is also a negative feedback system as the output is fed

back to the inverting input terminal. The output voltage Vo is given by,

Procedure:

Inverting Amplifier:1. Connect the op-amp as an inverting amplifier circuit.2. Connect a dual channel on CRO to simultaneously view Vo and Vin.3. Adjust the signal generator to give 200mV peak to peak sine wave at 100 Hz.4. Measure and record the peak value of Vo.5. Note the phase of Vo with respect to Vin.6. Calculate the theoretical closed loop gain =-Rf/R1and compare it with the practical value of Vo / Vin.7. Plot the input and output waveforms.

Non Inverting Amplifier:1. Connect the op-amp as non inverting amplifier circuit.2. Connect a dual channel on CRO to simultaneously view Vo and Vin.3. Adjust the signal generator to give 200mV peak to peak sine wave at 100 Hz.4. Measure and record the peak value of Vo.5. Note the phase of Vo with respect to Vin.6. Calculate the theoretical closed loop gain =1+ (Rf/R1) and compare it with the practical value of Vo / Vin.7. Plot the input and output waveforms

IC 741 – Pin Diagram

4

Design:Inverting Amplifier:Design an amplifier with a gain of -10 and input resistance equal to 10 KΩLet gain Av = -Rf / R1 = -10Choose R1 =1 KΩ Rf = 10 KΩ

Non Inverting Amplifier:Design an amplifier with a gain of +5 using one opamp.Let gain Av = 1+( Rf / R1) = 11Choose R1 =1 KΩ Rf = 10 KΩ

Circuit Diagram



5

Model Graph:

Input Signal (Vin)



6

Tabulation:

Inverting AmplifierVoltage(V) Time(ms)

Vin

Vout

Non-Inverting AmplifierVoltage(V) Time(ms)

Vin

Vout

Result

Thus the Inverting amplifier and Non inverting amplifier was designed and tested .

7

Exp.No: DIFFERENTIAL AMPLIFIERDate:

Aim:To design and test the operation of Differential amplifier

Apparatus Required:

Sl.No Apparatus Name Range Quantity1 Dual power supply (0-32)V 12 Function Generator (0-3)MHz 13 CRO (0-30)MHz 1

Components Required

Sl.No Components Range Quantity1 Resistors 1K,10K 1,22 Op_amp IC741 13 Connecting wires ----- As required

Theory:

Differential Amplifier

A circuit that amplifies the difference between two signals is called difference or differential amplifier. This type of the amplifier is very useful in instrumentation circuits. Since the differential voltage at the input terminals of the op-amp is zero.

Vo = R2 / R1 (V1 – V2).

Such a circuit is very useful in detecting very small differences in signals, since the gain R2 / R1 can be chosen very large. for ex: R2 = 100 R1 , then a small difference (V1 – V2) is amplified 100 times.

Common mode and differential mode Gain:

VCM = [V1 + V2] / 2VCM common mode signalV1 , V2 i/p signals

V0 = A1V1 + A2V2

V0 o/p voltageA1 , A2 voltage amplification from i/p1 and i/p 2differential voltage Vd = (V1 – V2)V1 = VCM + ½ Vd

8

V2 = VCM - ½ Vd

Differential voltage Vd = V1 - V2

V0 = ADM Vd + ACM VCM

differential mode Gain ADM = ½ (A1 - A2)Common mode Gain ACM = (A1 - A2)

Common Mode Rejection Ratio(CMRR):

The relative sensitivity of an op_amp to difference signal as compared toa common mode signal is called common mode rejection ratio (CMRR) and gives the figure of merit for the differential amplifier. So CMRR is given by: =| ADM / ACM |And is usually expressed in decibels (dB)

Procedure:

Differential Amplifier

1. Connect the op-amp as non inverting amplifier circuit.2. Connect CRO to V0.3. Adjust the signal generator.4. Measure and record the peak value of Vo.5. Calculate the practical value of Vo 6. Plot the input and output waveforms

Circuit Diagram

Differential Amplifier:

Design:

9

Differential Amplifier:

Design a Differential Amplifier with an input resistance equal to 1 KΩ and R1 = R2 = 10 KΩ.Choose Ri =1 KΩ R1 = R2 = 10 KΩ

Vo = R2 / R1 (V1 – V2).Model Graph:

Tabulation:

10

Differential AmplifierVoltage(V) Time(ms)

V1

V2

Vout

Result

Thus the Differential Amplifier was designed and tested

Exp.No: INTEGRATOR

11

Date:

Aim:

To design and test the Integrator circuit with maximum frequency of 100Hz

Apparatus Required:

Sl.No Apparatus Range Quantity1 Dual power supply (0-32)V 12 Function Generator (0-3)MHz 13 CRO (0-30)MHz 1

Components Required:

Sl.No Components Range Quantity1 Resistors 100 kΩ, 10 kΩ Each one2 Capacitors 0.1µF,0.01 µF Each one3 Op_amp IC741 14 Connecting wires ----- As required

Theory:

Integrator:By interchanging the resistor and capacitor of the differentiator circuit we obtain

the integrator circuit.

V0(0) initial output voltage fb = 1 / [ 2πR1Cf] (ideal)

fa = 1 / [ 2πRfCf] (practical) f = fa 1. If f < fa, circuit acts like a simple inverting amplifier no integration2. If f = fa , 50% accuracy results3. If f = 10 fa , 99% accuracy results4. If f > fa circuit is an integrator

Procedure:

Integrator

1. Connect the integrator circuit2. Set the function generator to produce a square wave of 1V peak to peak amplitude

at 500Hz. View simultaneously the output Vo and input Vi . 3. Adjust the output frequency until getting the clear triangular waveform.4. Measure the amplitude and frequency of the input and output waveforms.

12

5. Verify f > fa = 1 / R1 Cf for good integration.6. Now set the function generator to a sine wave of 1V peak to peak and frequency

500 Hz. Adjust the frequency of the input until the output is a negative going cosine waveform. Measure the frequency and amplitude of the input and output waveform.

Design

Integrator:

Consider the lossy Integrator for that the component values R1 = 10 kΩ , Rf = 100 kΩ , Cf = 0.1 μF , determine the lower frequency limit of integration and study the response for the inputs sine and aquare wave.

Let Rf = 100 kΩ and Cf = 0.1 μF,

Choose Rf Cf = Period of the signal to be integrated

Rf Cf = 1/ fa and Rf = 10 R1

fa = 1 / [ 2πRfCf] = 159 Hz R1 = 10 kΩ

Circuit Diagram

13

Model Graph

Tabulation

IntegratorVoltage(V) Time(ms)

Vin

Vout

Result:

Thus the differentiator using op-amp is designed with maximum frequency of 100Hz and tested.

14

Exp.No: DIFFERENTIATOR Date:

Aim:

To design and test the differentiator circuit with maximum frequency of 100Hz

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1.59 KΩ, 15.9KΩ Each one2 Capacitors 0.1µF,0.01 µF Each one3 Op_amp IC741 14 Connecting wires ----- As required

Theory:

Differentiator:

Differentiator circuit performs the mathematical operation of differentiation .The output waveform is the derivative of the input waveform. Ordinary differentiator circuit sensitive to high frequency noise.

A Practical differentiator circuit eliminates the problem of stability and high frequency noise. For good differentiator the time period T of the input signal is larger than or equal to RfC1.

Steps for designing of good differentiator:

1. Choose fa equal to the highest frequency of the input signal 2. Assume a practical value of C1 (<1µF) and then calculate Rf

3. Choose fb=10fa

fa = 1 / [ 2πRfC1] (ideal) fb = 1 / [ 2πR1C1] (practical)

16

Procedure

Differentiator

1. Connect the differentiator circuit with the values obtained from the design.2. Adjust the signal generator to produce 1V peak sine wave at 100Hz3. Observe input Vi and output Vo simultaneously on the CRO.4. Measure and record the peak value of Vo and the phase angle of Vo with respect to Vi.

Design:

Differentiator:

Design an opamp differentiator that will differentiate an input signal with fmax = 100Hz. Draw the output waveform for a sine wave of 1V peak at 100Hz applied to the differentiator and square wave.

Choose fa = fmax = 1/(2п Rf C1) = 100HzLet C1 = 0.1 µFRf = 1 / [ 2π fa C1] = 1 / [(2п) (100) (0.1*10-6) ] = 15.9KΩ Choose fb=10fa =1KHz fb = 1/(2п R1 C1)

R1 =1.59 KΩSince RfCf = R1 C1

Cf = 0.01 µFRcomp = R1 || Rf = R1 (Rf>>R1)

IC 741 – Pin Diagram

17

Circuit Diagram

Model graph

18

Tabulation

DifferentiatorVoltage(V) Time(ms)

Vin

Vout

Result:

Thus the differentiator using op-amp is designed with maximum frequency of 100Hz and tested.

19

Exp.No: INSTRUMENTATION AMPLIFIER

Date:

Aim:

. To design an instrumentation amplifier and to display the output analog voltage

in seven segment display

Apparatus : Required

S.No Apparatus Range Quantity

1DRB(Decade

Resistance Box)1MΩ 1

2 Multimeter - 1

3 Dual power supply (0-32)V 14 Function Generator (0-3)MHz 15 CRO (0-30)MHz 1

Components Required

S.No Components Range Quantity

1 Op-amp IC741 10

2 Resistor 10k, 1k 4, 2

3 Connecting wires - As required

Theory:

The op-amps A1 and A2 have differential input voltage as zero. For V1=V2, that is,

under common mode condition, the voltage across R will be zero .As no current flows

through R and R' the non-inverting amplifier A1 acts as voltage follower, so its output

V2'=V2.Similarly op-amp A2 acts as voltage follower having output V1'=V1.

However, if V1≠V2, current flows in R and R', and (V2'-V1') > (V2-V1). Therefore,

this circuit has differential gain and CMRR more. The output voltage V0 can be

calculated as follows:

20

The voltage at the (+) input terminal of op-amp A3 is (R2V1'/ (R1+R2)).Using

superposition theorem, we have,

V0 = - (R2/R1) V2' + (1 + (R2/R1) (R2V1'/ (R1+R2))

= R2/R1 (V1'-V2') …………………………. (1)

Since, no current flows into op-amp, the current I flowing (upwards) in R is

I = (V1-V2)/R and passes through the resistor R'.

V1'= R'I+V1 =(R'/R) (V1-V2) + V1

and V2'= -R'I+V2 = -(R'/R) (V1-V2) + V2

Putting the values of V1' and V2' in Eq. (1), we obtain,

V0 = R2/R1 [2R'/R (V1-V2) + (V1-V2)]

The difference gain of this instrumentation amplifier can be varied by using a

variable resistance R.

The output of Instrumentation amplifier is given to a series of comparators. The

reference voltages for the comparators are set by using a ladder of resistors to provide

0.5, 1.5,….. 6.5 V. The comparator outputs are given to the 8-to-3 priority encoder which

provides the BCD output which is applied to the BCD to 7 segment driver IC. The output

of which will drive the display.

Procedure:

Connections are given as per the circuit diagram.

For different values of R, V1 & V2 tabulate the output voltage Vop.

Calculate the Theoretical output Vot & gain for different values of R, V1 & V2.

Construct the comparators as shown in the circuit diagram.

The output of the comparators is given to 8/3 priority encoder.

The output of the priority encoder is given to BCD to 7 segment display driver

present in the trainer kit.

The output of display driver IC is connected to the 7 segment LED display unit

present in the trainer kit internally.

Observe the output analog voltage from the Instrumentation Amplifier displayed

in the 7 segment display in digital format.

21

Circuit Diagram

V 2'

-12VV 1'

R '

1 k

R 2

1 0 k

INS TRUM ENTATION AM P LIFIER

R 1

1 0 k

0

+12V

+12V

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2

R 2 1 0 k

-12V

+12V-12V

V 1

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2

V outR1 0 k

LM741

R '

1 k

LM741

3

2

74

6

1

5+

-

V+

V-

O U T

O S 1

O S 2

LM741

V 2

R 1

1 0 k

22

Design

Design an instrumentation amplifier for R’ = 1kΩ and R = R1 = R2 =

10KΩ and find the gain of an instrumentation amplifier

Output voltage Vo =

R’ = 1kΩ and R = R1 = R2 = 10KΩ

Gain = (R2/R1) [1+ (2R’/R)]

Tabulation:

S.No R (Ω)

Input Voltage Vi

(volts)Output Voltage V0

(volts)Gain

V1 (V) V2 (V)

Result:

Thus the instrumentation amplifier was designed and the analog output voltage in

seven segment was displayed and tested

Exp.No: ASTABLE MULTIVIBRATOR USING OP-AMPDate:

23

Aim:

To design and test an astable multivibrator using op-amp for the frequency of oscillation of 1KHZ.

Apparatus Required:



Sl.No Components Range Quantity1 Capacitors 0.1µF 12 Resistors 10KΩ, 4.7KΩ 2,13 Op-amp IC741 1


Theory:

Astable Multivibrator:

The output of the op-amp is forced to swing repetitively between positive saturation +Vsat and negative -Vsat resulting in square wave output.This circuit is also called as free running multivibrator or square wave generator.The output of the op-amp will be in positive saturation if differential input voltage is negative and viceversa.The differential voltage Vd=Vc- β Vsat where β is the feedback factor.Vo is the potential at non-inverting terminal of op-amp.

Consider the instant at which Vo=+Vsat .Now the capacitor charges exponentially towards +Vsat through R. Automatically vd increases and crosses zero. This happens when Vc= + βVsat .The moment vd becomes +ve due to further charging of capacitor, output changes to -Vsat .Now capacitor starts to discharge to zero and recharges towards -Vsat. Now vd decreases and crosses zero.This happens when Vc=- βVsat.

The moment vd becomes -ve again, output changes to +Vsat .THis completes one cycle. The time period T of the square wave is

T=2 RC ln(1+ β )/(1- β ) , If β is made 1/2 ,T = 2.2 RC.

24

The astable multivibrator is practically useful for the generation of frequency in the audio frequency range.Higher frequencies are limited by the delay time and slew rate of the op-amp.

Procedure:


1. Verify whether the Op-Amp is in good condition wiring it as ZCD or voltage follower.2. Setup the astable multivibrator with the values of components as obtained in the design.3. Observe the waveforms at pin nos.6 and 2 of Op-Amp on CRO and note down their amplitudes and frequencies.4. Plot the waveforms obtained in pin no6 and 2.

Design:


Time period T = 2 RC ln

where, the feedback factor β = R2 / (R1+R2) = 0.5 Let β = 0.5 and R1 = R2 = 10KΩ. C = 0.1µF. Then R = 4.7KΩ T = 1 ms

Circuit Diagram

Model Graph

25

Tabulation

Astable Multivibrator

Pin NoAmplitude

(V)Time Period

(ms)

2

3

6

Result:

Thus the astable multivibrator using op-amp for the frequency of oscillation of 1KHZ was designed and tested.

26

Exp.No: MONOSTABLE MULTIVIBRATOR USING OP-AMPDate:

Aim:

To design and test monostable multivibrator using op-amp for the frequency of oscillation of 1KHZ.

Apparatus Required:



Sl.No Components Range Quantity1 Capacitors 0.1µF,0.001F Each one2 Resistors 10KΩ, 14.45KΩ,

800Ω2,1,1

3 Op-amp IC741 1


Theory:

Monostable Multivibrator :

Monostable multivibrator is also called as one-shot. It has one stable state and one quasi-stable state.The circuit remains in stable state until triggering signal causes a transition to quasi-stable state. After a time interval, it returns to the stable state. So a single pulse of predetermined duration can be generated using this circuit.

Assume the output Vo=+Vsat. Now the diode D1 clamps the capacitor voltage Vc at 0.7V. Feed back voltage available at non inverting terminal is + Vsat.When the negative going trigger is applied such that the potential at non inverting terminal becomes less than 0.7V,the output switches to -Vsat.Now the capacitor charges through R towards -Vsat,because the diode becomes reverse biased.When the capacitor voltage becomes more negative than -Vsat,the comparater switches back to Vsat,and capacitor C starts charging to +Vsat through R until Vc reaches 0.7V and C becomes clamped to 0.7V. The pulse width is given by T=RCln(1/(1- β ) approximately.If β =0.5,T=0.69RC

Procedure

27


1. Verify whether the op-amp is in good condition wiring it as ZCD or voltage follower.2. Setup monostable multivibrator and feed 6 Vpp,300Hz square wave at the trigger input.If pulse generator is available,use narrow pulses instead of square pulse.3. Observe the wave form at pin nos.6 and 2 of op-amp on CRO and note down its amplitude and frequency.

Design:


We have,T = RC ln [1/(1- β )].Let β = R2/(R1+R2) = 0.5.Then T = 0.69RC Let T = 1ms and C = 0.1µF .Then R = 14.45KΩ.Use15KΩ std. R1 = R2 = 10KΩ Design of diferentiating circuit:R4C4 < 0.0016 Tp. Take trigger time period Tp = 5ms. Let C4 = 0.001 F. Then R4 = 800Ω .Use 720

Circuit Diagram

28

Model Graph

Tabulation

Monostable Multivibrator

Pin NoAmplitude

(V)Time Period

(ms)

2

3

6

Result:

Thus the Monostable multivibrator using op-amp for the frequency of oscillation of 1KHZ was designed and tested.Exp.No: SCHMITT TRIGGER USING OP-AMPDate:

29

Aim:

To design and test an schmitt trigger using op-amp for the frequency of oscillation of 1KHZ.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1KΩ, 47KΩ 1,12 Op-amp IC741 1


4

Theory:

Schmitt Trigger:

The Schmitt trigger or Regenerative Comparator is a comparator with positive feedback. It converts slowly varying waveforms into square wave. The input voltage is applied to the inverting terminal and the feedback circuit is connected to the non inverting terminal. The input voltage triggers the output every time it exceeds certain voltage levels. These voltage levels are called as upper threshold voltage VUT and Lower Threshold Voltage VLT . As long as the input voltage is less than VUT the output remains at +Vsat. When Vin is just greater than VUT the output regenerative switches to –Vsat and remains at this level. When the input voltage becomes lesser than VLT , the output switches from –Vsat to +Vsat.

Procedure

Schmitt Trigger:

1 Connect the circuit as per the circuit diagram.1 Set the input voltage as 1Vpp1 Measure the amplitude of the output signal.

30

1 Note down the upper threshold voltage VUT and Lower Threshold Voltage VLT by superimposing the square wave on the input sine wave.

1 Plot the input and output waveforms.

Design

Schmitt Trigger:

Upper Threshold Voltage VUT = [ R2 / (R1+R2) ] Vsat

Lower Threshold Voltage VLT = [ R2 / (R1+R2) ] (- Vsat )

Vsat = 0.9 Vcc = (0.9) (12V) = 10.8VLet R2 = 1KΩ R1 / R2 = (Vsat / VUT) – 1R1 = 47KΩ , VUT = 0.225V

Circuit Diagram

Model Graph

31

Tabulation

Schmitt TriggerVUT =

VLT =Ampliude(V) Time(ms)

Vin

Vo

Result:

Thus the Schmitt Trigger using op-amp was designed and tested.

32

Exp.No: WIEN BRIDGE OSCILLATOR USING OP-AMPDate:

Aim:To design and test Wien Bridge Oscillator with the frequency of 1KHz.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1KΩ, 10KΩ 2,12 Op-amp IC741 1


4 Capacitors 0.1µF 2

Theory:

Wien Bridge Oscillator

This is an audio frequency oscillator of high stability and simplicity. The feedback signal in this circuit is connected to the non inverting input terminal so that the op-amp is working as the non-inverting amplifier. Therefore the feedback network need not provide any phase shift.The circuit can be viewed as the Wienbridge with a series RC network in the adjoining arm.Resistors Ri and Rf are connected in the remaining arms.The condition of zero phase shift around the circuit is achieved by balancing the bridge.The frequency of oscillation is the resonant frequency of the balanced bridge and is given by the expression

fo=1/2 π RC. From the analysis of the circuit , it can be seen that the feedback factor β

=1/3 at the frequency of oscillation.Therefore for the sustained oscillation ,the amplifier must have the gain of 3.

33

Procedure:


1.Verify whether the op-amp is in good condition 2.Setup the circuit with the values obtained in the design.3.Observe the output waveform on an oscilloscope.4.Adjust Rf to obtain a sine wave output.5.Note down the amplitude and frequency of the output wave form.

Design:


Let fo = 1KHz. Given fo = 1/ 2 πRC. Let C = 0.1 µF. Then R = 1.6KΩ. Use 1.5KΩ std. Gain Av = 1+ Rf / Ri = 3 Let Ri = 1KΩ Then Rf = 2.2KΩ. Use 4.7KΩ potentiometer

Circuit Diagram

Model Graph

34

Tabulation

Wien Bridge OscillatorNo. Ampliude(V) Time(ms)

Result:

Thus the Wien Bridge Oscillator using op-amp was designed and tested.

35

Exp.No: RC PHASE SHIFT OSCILLATOR USING OP-AMPDate

Aim:To design and test RC phase shift oscillator with the frequency of 500Hz.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1KΩ, 10KΩ,

290KΩ,3,1,1

2 Op-amp IC741 1


4 Capacitors 0.1µF 3

Theory:

RC phase shift oscillator

RC Phase shift oscillator consists an op-amp as the amplifying stage and three RC cascaded networks as the feedback netwok.The feedback network provides a fraction of the output voltage back to the input of the amplifier.The op-amp is in the inverting mode.Therefore any signal which appears at the inverting terminal is shifted by 180 degree at the output.An additional 180 degree phase shift required for oscillations as per Barkhausen criteria is provided by cascaded RC network.Thus the total phase shift around the loop becomes 0 degree.

The gain of the inverting op-amp should be at least 29 at this frequency.The gain fo = 1 / 6 (2 R C ).Also the gain of the inverting op-amp ahould be atleast 29,or Rf 29 R1

37

Procedure:

RCPhase shift oscillator:

1.Verify whether the op-amp is in good condition 2.Setup the circuit with the values obtained in the design.3.Observe the output waveform on an oscilloscope. 4.Note down the amplitude and frequency of the output wave form

Design

RC Phase shift oscillator:

and Rf 29 R1

Choose C = 0.1 µ FThen R = 1KΩTo prevent loading, R1>=10RTake R1 = 10KΩRf = 29 R1 = 290KΩ (use 500KΩ Potentiometer)

Circuit diagram

38

Model Graph

Tabulation

RC phase shift oscillatorNo. Ampliude(V) Time(ms)

Result:

Thus the RC phase shift oscillator using op-amp was designed and tested.

39

Exp.No: ASTABLE MULTIVIBRATOR USING 555 TIMERDate:

Aim:

To design and test the Astable multivibrator using NE555 with 1 KHz frequency

and 25 % duty cycle.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 10KΩ 22 Op-amp IC555 1


4 Capacitors 0.1 µF,0.01 µF Each one

Theory:

Astable Multivibrator using NE555

It is a square wave generator. It is also called free running oscillator. Output of astable multivibrator toggles spontaneously between one state and other, without any external command. The principle of operation of square wave output is to force an op-amp to operate in saturation region.

Initially capacitor C starts charging through Ra and Rb towards Vcc with a time constants Vcc with a time constant (Ra+Rb)C.During this time,R=0,S=1,Q=0 and output(pin 3) is high(equal to Vcc).When capacitor voltage equals (2/3)Vcc the upper comparator triggers the control flip flop so that Q=1 .This makes transistor Q1 ON and capacitor C starts discharging towards ground through Rb and Q1 with a time constant RbC.During the discharge of the timing capacitor C,as it reaches Vcc/3 the lower comparator is triggered and at this stage S=1,R=0, which turns Q=0.This makes transistor Q1 OFF and again capacitor C starts to charge.Thus the capacitor periodically charges and discharges between (2/3)Vcc and (1/3)Vcc. The charging period of capacitor C=0.69(Ra+Rb)C. The discharging period of capacitor C=0.69RbC.

41

Procedure

Astable Multivibrator Using 555 Timer:

1. Connect the circuit as per the circuit diagram.2. Measure the amplitude of the output signal.3. Observe the wave forms at pin nos.3 and 6 of the chip.4. Plot the input and output waveforms.

Design

Astable Multivibrator using NE555

Let Vcc=10V and T=1msT = 0.69 (Ra + 2Rb) C = 2.1msf = 1 / T = 1.45 / (Ra + 2Rb) CLet RA = RB = R = 10KΩLet C = 0.1µ F.Thigh = 0.69 (Ra + Rb) C = 1.4msTlow = 0.69 Rb C = 0.7ms

Pin Diagram NE555

42

Circuit Diagram NE555

Model Graph

Tabulation

Astable Multivibrator using NE555Voltage Ampliude(V) Time(ms)Output

Voltage(V0)Capacitor

Voltage(Vc)

Result:Thus the Astable Multivibrator using NE555 was designed and tested.

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Exp.No: MONOSTABLE MULTIVIBRATOR USING 555 TIMERDate:

Aim:

To design and test the Monostable Multivibrator using NE555 with 1 KHz

frequency and 25 % duty cycle.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 10KΩ 12 Op-amp IC555 1


4 Capacitors 0.1 µF,0.01 µF Each one

Theory:

Monostable Multivibrator using NE555

It is also called as one shot multivibrator. It is stable in only one state of its two states. We have to force it into the unstable state by using an external signal called trigger signal.

A monostable multivibrator is used to generate pulses of desired duration and is called gating circuit. The circuit has one stable state and other quasi state. The width of output pulse depends only on external components connected in op-amp. It is also referred to as time delay circuit, as it generates a fast transition at a predetermined time after the application of input trigger.

In the stable state Q is high and inturn,Q1 is turned ON and output is very low.When the negative going trigger passes through Vcc/3, the FF is set i.e.Q=0.This makes transistor Q1 off. The capacitor starts charging towards Vcc,which was earlier clamped to zero.After the time period , the capacitor voltage is greater than (2/3)Vcc and upper comparator resets the FF i.e. R=1,S=0.This makes Q =1.In turn,transistor Q1 turns ON and thereby discharging the capacitor C rapidly to ground potential. The output returns to the stable state.

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The time duration of quasi-stable state is given by the equation,T=1.1RC seconds. Though it is possible to apply the trigger pulse directly to pin 2 ,trigger shown in figure is better because it makes narrow trigger pulses applied to trigger terminal.Also it prevents the possibility of mistriggering the monostable multivibrator on positive pulse edges.

Procedure

Monostable Multivibrator Using 555 Timer:

1 Connect the circuit as per the circuit diagram.1 Measure the amplitude of the output signal.1 Observe the wave forms at pin nos.3 and 6 of the chip.1 Plot the input and output waveforms.

Design:

Monostable multivibrator:

Let Vcc = 10V and T = 1ms We have,T = 1.1RC.Let C = 0.1µ F Then R = 10 KΩ

Design of triggering circuit:,RiCi < 0.0016 Tp where Tp is the time period of the trigger.

Let Tp = 3ms and Ci = 0.01µF. Then Ri = 480Ω Choose Ci = 0.01µF.

Circuit Diagram

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Model Graph

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Tabulation

Monostable Multivibrator Using 555 TimerVoltage Ampliude(V) Time(ms)Output

Voltage(V0)Capacitor

Voltage(Vc)

Result:

Thus the Monostable Multivibrator Using 555 Timer was designed and tested.

48

Ex.No LOW PASS ACTIVE FILTERDate:

Aim:

To design and test the Low Pass Active Filter,

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1.6 KΩ ,10KΩ,

5.86KΩ 2 ,1,1

2 Op-amp IC555 1


4 Capacitors 0.1 µF 2

Theory:

Low Pass Active Filter:

A filter is a selective circuit that passes frequencies only within the specified band and attenuate all other frequencies. The active filters use op-amp as active element and reactance and capacitance as passive elements. The op-amp is used in non inverting configuration and offers high input impedance and low output impedence.Thus load is isolated from the frequency determining network. A first order filter consist of single RC network connected to the positive input terminal of op-amp. An improved filter response can be obtained by using a second order active filter. A second order filter consists of two RC pairs and has a roll-off rate of -40 dB/decade. A general second order filter (Sallen Kay filter) is used to analyze different LP, HP, BP and BSF.

Low-pass filter is a circuit offering easy passage to low-frequency signals and difficult passage to high-frequency signals.A high pass filter's task is just the opposite of a low pass filter: to offer easy passage of a high frequency signal and difficult passage to a low frequency signal.

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A0 = 1+ [Rf / Ri] , fh = 1 / 2пRC

1. f << fh , |H(jw)| = A0 (pass band)2. f >> fh , |H(jw)| << A0 = 0 (stop band)3. f = fh , |H(jw)| = 0.707 A0 (at cut off frequency)For minimum dc offset Rf || Ri = 2R (at dc condition, capacitors are open)

Procedure1. Get the required components and check the condition of them2. Connect the components as per the circuit diagram.3. Measure the input and output voltage and enter in to tabular column.4. Plot the response.

Design :

Design a second order butterworth low pass filter having upper cut off frequency 1KHZ. Then determine the frequency response.

Given fh = 1KHZ = 1 / 2пRC Let C = 0.1 µF , R = 1.6 KΩ.Let Rf = 5.86 KΩ , Ri = 10 KΩA0 = 1+ [Rf / Ri] = 1.586

Circuit Diagram:

50

Model Graph

Tabulation:

Vin =Low Pass Active Filter

Frequencyfin in HZ

Vo (Volts)

Gain in db =20log(Vo/Vin)

Result;

Thus the active low pass filter was designed and tested.

51

Ex.No HIGH PASS ACTIVE FILTERDate:

Aim:

To design and test the High Pass Active Filter,

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 1.6 KΩ ,10KΩ,

5.86KΩ 2 ,1,1

2 Op-amp IC555 1



Theory:

High pass filter is the complement of the low pass filter and can be simply by interchanging R and C in the low pass configuration. The Voltage gain magnitude equation of the second order butterworth HPF can be obtained as,

Where , fL = 1 / 2пRC

Procedure

1. Get the required components and check the condition of them2. Connect the components as per the circuit diagram.3. Measure the input and output voltage and enter in to tabular column.4. Plot the response.

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Design :

Design a second order butterworth high pass filter having lower cut off frequency 1KHZ. Then determine the frequency response.

Given fL = 1KHZ = 1 / 2пRC Let C = 0.1 µF , R = 1.6 KΩ.Let Rf = 5.86 KΩ , Ri = 10 KΩA0 = 1+ [Rf / Ri] = 1.586

Ciircuit Diagram

Model Graph

54

Tabulation:

Vin =High Pass Active Filter

Frequencyfin in HZ

Vo (Volts)


Result;

Thus the active High pass filter was designed and tested.

55

Ex.No BAND PASS ACTIVE FILTERDate:

Aim:

To design and test the Band Pass Active Filter,

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 7.9KΩ ,10KΩ,

39.8KΩ 2,4,2

2 Op-amp IC555 1



Theory:

A band pass filter passes a particular band of frequencies with zero attenuation and attenuates all other frequencies. There are two types of band pass filters which are classified as per the figure of merit or quality factor Q.

(i) Narrow band pass filter (Q > 10)(ii)Wide band pass filter (Q < 10)

Q = fo / B.W = fo / (fh - fl)

Wherefl = upper cut off frequencyfh = lower cut off frequencyfo = centre frequency fo =√ fh fl

A wide band pass filter can be formed by cascading a HPF and LPF section. If the HPF and LPF are of the second order, then he band pass filter will have a roll off rate of -40 dB/decade.

57

Procedure

1. Get the required components and check the condition of them2. Connect the components as per the circuit diagram.3. Measure the input and output voltage and enter in to tabular column.4. Plot the response.

Design:

Band pass filter:

Design a wide band pass filter having fL = 400HZ fH = 2KHZ and pass band gain 4. Find the value of Q of the filter.

Pass band gain = 4fl = 400Hzfh = 2 KHzThe LPF and HPF section may be designed to give gain = 2(ie) Ao = 1+(Rf / Ri) = 2 Let Rf = Ri = 10KΩ (for each LPF and HPF section)

For LPF, fh = 1 / (2пR1C1) = 2KHzLet C1 = 0.01 µF , R1 = 7.9KΩ

For HPF , fl =1 / (2пR2C2) = 400HzLet C2 = 0.01 µF , R2 = 39.8 KΩ

Center frequency fo =√ fh fl = 894.4Q = fo / B.W = fo / (fh - fl) = 0.56 , (Q < 10)

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Circuit Diagram

Model Graph

59

Tabulation:

Vin =Band Pass Active Filter

Frequencyfin in HZ

Vo (Volts)


Result;

Thus the active Band pass filter was designed and tested.

60

Exp.No: DC POWER SUPPLY USING LM723Date:

Aim:

To design and test the DC Power Supply Using LM723,

Apparatus Required:

Sl.No Apparatus Range Quantity1 Dual power supply (0-32)V 12 Function Generator (0-3)MHz 13 CRO (0-30)MHz 14 R. P. S (0- 30) V, 1 mA 15 Rheostat (0-350) , 1.5 A 1


Sl.No Components Range Quantity1 Resistors2 Op-amp IC 723 1


4 Capacitors 100 F / 25 V 2

Theory:

DC Power Supply Using LM723

The function of a voltage regulator is to provide a stable dc voltage for powering other electronic circuits. A voltage regulator should be capable of providing substantial output current. Voltage regulators are classified as, series regulator and switching regulator.

Line / Input Regulation : It is defined as the percentage change in the output voltage for a change in the input voltage. It is usually expressed in millivolts or as a percentage of the output voltage.

Load Regulation : It is defined as the percentage change in the output voltage for a change in the load current. It is usually expressed in millivolts or as a percentage of the output voltage V0.

The three terminal regulators have the limitations.. 1. No short circuit protection 2. Output voltage (positive or negative) is fixed.

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These limitations have been overcome in the 723 general purpose regulator, which can be adjusted over a wide range of both +ve or –ve regulated voltage. This IC is inherently low current device, but can be boosted to provide 5amps or mpre current by connecting external components. The limitation of 723 is that it has no in-built thermal protection. It also no short circuit current limits.

A low Voltage regulator using IC723: A simple +ve low voltage (2V to 7V) regulator can be made using 723. The voltage at the NI terminal of the error amplifier due to R1 R2

divider is, VNI = Vref [ R2 / ( R1 + R2 )]

The difference between VNI and the output voltage V0 which is directly fed back to the INV terminal is amplified by the error amplifier. The output of the error amplifier drives the pass transistor Q1 so as to minimize the difference between the NI and INV inputs of error amplifier. Since Q1 is operating as an emitter follwer

V0 = Vref [ R2 / ( R1 + R2 )]

If the output voltage becomes low, the voltage at the INV terminal of error amplifier also goes down. This makes the output of the error amp to become more +ve , thereby driving transistor Q1 more into conduction. This reduces the voltage across Q1 and drives more current into the load causing voltage across load to increase. So the initial drop in the load voltage has been compensated. Similarly, any increase in load voltage, or changes in the input voltage get regulated.

The typical reference voltage is 7.15V. So the output voltage

V0 = 7.15V [ R2 / ( R1 + R2 )]

Which will always be less than 7.15V. So in the circuit used as low voltage (<7V) 723 regulator.

Procedure:

1. Connect the 723 regulator as shown in fig.2. Set the dc power supply voltage Vinto +10V.Measure and record Vref with

respect to ground.With load RL(10KΩ pot) removed from the circuit measure the minimum and maximum output voltages by rotating the 1KΩ pot through its full range.

3. Now adjust the 1KΩ pot so that Vo is +5V dc.Measure the voltage between the wiper arm of the 1KΩ pot and ground.

4. Adjust the load RL(10KΩ pot ) untill the load current IL=1mA.Record VL.Repeat for different values of load currents(ie)5mA,10mA,15mA and 18mA.Calculate load regulation and compare with the maufacturers speifications

62

Circuit Diagram

Pin Diagram

63

Tabulation::

Load RegulationInput Voltage = Volts

S.No. Load Resistance () Output Voltage (V)

:

Line Regulation Load Resistor = KOhms

S.No. Input Voltage (V) Output Voltage (V)

Result:

Thus the low voltage IC regulator LM723 is constructed and the regulation characteristics are tabulated and drawn its characteristics.

64

Exp.No: DC POWER SUPPLY USING LM317Date:

Aim:

To design and test the DC Power Supply Using LM317,

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 240 Ω, 2KΩ,

2.01 k Ω, 0.52 k ΩEach one

2 Op-amp IC 317 1


4 Capacitors 2

Theory:

DC Power Supply Using LM317:The fixed voltage regulators are designed and preset for a particular voltage of

positive/negative polarities. There are applications which require 1. Regulated voltage sources which are precisely variable and 2. some supply voltages which are not available from standard fixed voltage regulators.

The LM317 series regulators are adjustable three terminal positive voltage regulators and they are capable of supplying output current of 0.1A to 1.5A over a range of 12V to 37V output voltage range.

Procedure:

DC Power Supply Using LM317:

1. Connect the 317 regulator as shown in fig.2. Set the dc power supply voltage Vin to +10V.Measure and record Vref with

respect to ground.With load RL(10KΩ pot) removed from the circuit measure the

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minimum and maximum output voltages by rotating the 1KΩ pot through its full range.

3. Now adjust the 1KΩ pot so that Vo is +5V dc.Measure the voltage between the wiper arm of the 1KΩ pot and ground.

4. Adjust the load RL(10KΩ pot ) untill the load current IL=1mA.Record VL.Repeat for different values of load currents(ie)5mA,10mA,15mA and 18mA.Calculate load regulation and compare with the maufacturers speifications

Design

1. An LM317 regulator with capacitors and protective diodes has R1 = 240 Ω and R2

2KΩ. If IADJ = 50µA and Vref = 1.25 find the value of V0.

V0 = Vref [1+ (R1 /R2)] + IADJ R2 = 11.77V.

2. Design an LM317 adjustable positive regulator voltage for an output voltage V0

varying from 4 to 12V and an output current I0 of 1A.

Maximum IADJ = 100µA for LM317.Assume R1 = 240 Ω and Vref = 1.25V0 = 4V, R2 = 0.52 k ΩV0 = 12V, R2 = 2.01 k Ω

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Circuit Diagram:

67

Tabulation

DC Power Supply Using LM317

Load Resistor = KOhmsS.No. Input Voltage (Vi) Output Voltage (V0)

Result:

Thus the low voltage IC regulator LM317 is constructed and the regulation characteristics are tabulated and drawn its characteristics.

68

Exp.No: PLL characteristics and its use as Frequency Multiplier Date:

Aim:

To design and test the Frequency Multiplier Using PLL 565.

Apparatus Required:



Sl.No Components Range Quantity1 Resistors 240 Ω, 2KΩ,

2.01 k Ω, 0.52 k ΩEach one

2 Op-amp IC 317 1


4 Capacitors 2

Theory:

Frequency Multiplier Using PLL 565:In the block diagram the frequency divider is inserted between the VCO and the

phase comparator. Since the output of the divider is locked to the input frequency fIN , the VCO is actually running at a multiple of the input frequency. The desired amount of multiplication can be obtained by selecting a proper divide-by-N network. Where N is an integer.

For EX: to obtain the output frequency fOUT = 5 fIN , a divide-by-N = 5 network is needed. This function is performed by a 7490 (4-bit binary counter) configured as a divide-by-5 circuit.. In that the transistor Q1 is used as a driver stage to increase the driving capability of the NE565.

To verify the operation of the circuit, one must determine the input frequency range and then adjust the free running frequency fOUT of the VCO by means of R1 and C1

s0 that the output frequency of the 3490 divider is midway within the predetermined

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input frequency range. The output of the VCO now should be 5fIN . The fOUT can be adjusted from 1.5KHz to 15 KHz by varying potentiometer R1 . This means fIN has to be within 300Hz to 3 KHz. In addition input waveform can be either sine or square wave and may be applied to input pins 2 or 3.

Even though supply voltages ±10V are used in the NE565 can be operated on ±5-V supply voltages instead. A small capacitor typically 1000pF, is connected between pins 7 and 8 to eliminate possible oscillations. Also, C2 should be large enough to stabilize the VCO frequency.

Procedure:

Frequency Multiplier Using PLL 565:

1. Make the connections as per the circuit diagram.2. Connect the CRO in output.3. Give the input using function generator.4. Vary the frequency.5. Note the output and plot.

Block Diagram

70

Circuit Diagram

Model Graph

71

Tabulation:

Frequency Multiplier Using PLL 565

S.No. fIN (Hz) fOUT (Hz)

Result:

Thus the Frequency Multiplier Using PLL 565 was designed and tested.

72

Exp.No: STUDY OF SWITCHED MODE POWER SUPPLY SMPSDate:

Aim:

To Study the performance and operation of the Switched Mode Power Supply (SMPS).

Theory

Limitations of the Linear Voltage Regulator:1. The input step down transformer is bulky and the most expensive componenet of

the linear regulated power supply mainly because of low line frequency (50Hz) and large values of the filter capacitors are required to decrease the ripple. The efficiency of a series regulator is usually very low (50%).

2. The input voltage must be greater than the output voltage (V in > V0). The greater the difference in input-output voltage, more will be the power dissipated in the series pass transistor which is always in the active region. A TTL system regulator (Vin = 5V) when operated at 10V dc input gives 50% efficiency and only 25% for 20V dc input.

3. In a system with one dc supply voltage (such as +5V for TTL) if there is need for ±15V for op_amp operation, it may not be economically and practically feasible to achieve this.

Switched Mode Power Supply (SMPS):SMPS overcome these difficulties. The Switching regulator, also called switched

mode regulator operate in a significantly different way from that of a conventional series regulator circuit.

In series regulator, the pass transistor is operated in its linear region to provide a controlled voltage drop across it with a steady dc current flow.

In switched mode regulator, the pass transistor is used as a “controlled switch” and is operated at either cutoff or saturated state. Hence, the power transmitted across the pass device is in discrete pulses rather than as a steady current flow. Greater efficiency is achieved since the pass device is operated as low impedance switch. When the pass device is at cutoff, there is no current and dissipates no power. Again when the pass device is in saturation, a negligible voltage drop appears across it and thus dissipates only a small amount of average power, providing maximum current to the load. In either case, the power wasted in the pass device is very little and almost all the power is transmitted to the load. Thus efficiency in switched mode power supply is remarkably high in the range of 70-90%.

Switched mode regulators rely on pulse width modulation to control the average value of the output voltage. The average value of a repetitive pulse waveform depends on the area under the waveform.Construction and operation of the circuit: The bridge rectifier and capacitor filters are connected directly to the ac line to give unregulated dc input. The thermistor (Rt) limits the high initial capacitive charge current.

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The reference voltage regulator is a series pass regulator. Its output is a regulated reference voltage Vref which serves as a power supply voltage for all other circuits. The current drawn from Vref is usually very small (-10mA). So the power loss in the series pass regulator does not affect the overall efficiency of the SMPS.The transistor Q1 and Q2 are alternately switched OFF and ON at 20KHz. These transistors are either fully ON (VCE sat ~ 0.2V) or cut-off, so they dissipate very little power. These transistors drive the primary of the main transformer. The secondary is centre-tapped and full wave rectifications achieved by diodes D1 and D2. This unidirectional square wave is next filtered through a two stage LC filter to produce output voltage V0.The regulation of V0 is achieved by the feedback circuit consisting of a pulse width modulator and steering logic circuit.The output voltage V0 is sampled by a R1R2 divider and a fraction R1 / [R1 + R2 ) is compared with a fixed reference voltage Vref in comparator1. The output of this voltage comparison amplifier is called Vcontrol (fig.a). Vcontrol is applied to the (-) input terminal of comparator2 and a triangular waveform of frequency 40KHz.is applied at the (+) input tyerminal.. It may be noted that a high frequency triangular waveform is being used to reduce the ripple. The comparator2 functions as a pulse as a pulse width modulator and its output is a square wave VA (fig.b) of period T (f = 40KHz). The duty cycle of the square wave is T1 / (T1 + T2) and varies with Vcontrol which in turn varies with the variation of V0. The output Va drives a steering logic circuit in the dashed block. It consists of 40KHz oscillator cascaded with a flip-flop to produce two complementary outputs VQ and VQ’

fig.d & e). The VA1 and VA2 are the outputs of AND gates A1 A2. These waveforms are applied at the base of transistor Q1 and Q2. Depending upon whether transistor Q1 or Q2 is ON, the waveform at the input of the transformer will be a square wave in(fig.h). The rectified output Vo (fig.i).

The output current passes through the power switch consisting of transistors Q1

and Q2. Inductor having low resistance and the load. Hence using a switch with low losses (transistor with small VCE sat and high switching speed) and a filter with high quality factor, the conversion effiency can easily exceed 90%.

If there is a rise in dc output voltage V0 the voltage control Vcontrol with the triangular waveform and in this case decreases the time period T1 in the waveform. This in decreases the pulse width of the waveform driving the main power transformer. Reduction in pulse width lowers the average value of the dc output V0. Thus the initial rise in the dc output voltage V0 has been nullified.Why SMPS has better efficiency than linear regulated power supply?

The very high frequency signals (>=40KHz) are being applied. The transistor Q1

and Q2 are acting as the switches and become alternately ON and OFF at a frequency of 20KHz. Again the transistor Q1 or Q2 is ON for very small duration and consumes negligibly small power since (VCE sat ~ 0.2V) is small. It may also be noted that the high operating frequency used for the switching transistors allows the use of smaller transformers, capacitors and inductors. This allows a decrease in size and cost.Limitations and Precautions in SMPS:Since the rectifier is tied directly to the ac line voltage, the rectifiers, capacitors and

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switching transistors must be able to withstand the peak line voltage (310V for 220V ac rms line). The resistor Rt must be provided to prevent the uncharged capacitors from shorting out the line when initially turned ON. A SMPS is more complex and requires external components like inductors transformers. It is slow in responding to transient load changes compared to the conventional series regulator. One should be careful about the electromagnetic and RF interference while using SMPS.Available IC’s: Motorola MC 3420/3520 Pulse width modulator IC, SG 1524.

Circuit Diagram

75

Model Graph

Result;

Thus the study of switched mode power supply was done and verified.

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lic manual m

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