leveraging software to enhance timing analysis for actel rtax-s devices

Leveraging Software to Enhance Timing Analysis for Actel RTAX-S DevicesJohnny ChungCorporate Applications EngineeringActel CorporationMAPLD 2005

2 MAPLD 2005/1034Chung

SmartTimeAchieve timing closure easier with Actel’s gate-level

static timing analysis tool fully integrated within Actel’s software solution

Enables complete timing analysis and timing constraints editing for RTAX-S designs to achieve desired performance Ensure all timing constraints are met Ensure design operates at the desired speed with the right amount of

margin across all operating condition variations Provides a selection of analysis types that enables the

following: Find the minimum cycle time that does not result in a timing violation Identify paths with timing violations Analyze delays of paths that have no timing constraints Perform inter-clock domain timing verification Perform maximum and minimum delay analysis for setup and hold checks checks the timing requirements for violations while taking into account timing

exceptions such as multicycle or false paths


SmartTimeTiming Constraints Editor

You can add or modify timing constraints on a specific pin (for example, clock constraint) or on a specific set-of-paths (for example, maximum delay constraint) for your timing requirements and timing exceptions

User-friendly visual dialog boxes

Timing Analyzer You can browse through the design’s various clock domains to

examine the timing paths and identify those violating the timing requirements

You can also add or modify constraints for your timing requirements and timing exceptions


SmartTime New FeaturesProvides a larger number of work-saving features

compared to previous timing tool External Setup/Hold

includes an external setup/hold domain browser to show the delay more clearly than previous timing tool

Input Delay Constraint can be set according to External Setup/Hold constraint or as Input

delay constraint Visual constraint dialogs

Clock to Output Delay SmartTime shows the entire path delay from the clock source

through the clock pin of the register to the output port, an improvement over the previous timing tool


SmartTime New FeaturesProvides a larger number of work-saving features

compared to previous timing tool Maximum Delay Constraint Priority

Maximum delay is seen as an exception to the clock constraint Maximum delay constraint always has a higher priority than the

clock constraint Inter-Clock Domain

SmartTime allows the inter-clock domain analysis, an improvement over the previous timing tool

Flexibility in clock domain selection


Setup Check in SmartTime to Aid RTAX-S Timing Analysis

Setup Check Arrival time = Launch edge (0) + max Clock to FF1 + max Data path Required time = Capture edge (T) + min Clock to FF2 – Setup of FF2 Slack = Required – Arrival = Violation if < 0


Setup Check w/ Multicycle Paths for RTAX-S Timing Analysis

Add MulticycleConstraint Fields are pre-filled with the

path information


Setup Check w/ Multicycle Paths for RTAX-S Timing Analysis

Setup Check Arrival time = Launch edge (0) + max Clock to FF1 + max Data path Required time = Capture edge (2T) + min Clock to FF2 – Setup of FF2 Slack = Required – Arrival = Violation if < 0


Hold Check in SmartTime for RTAX-S Timing Analysis

Hold Check Arrival time = Launch edge (0) + min Clock to FF1 + min Data path Required time = Capture edge (0) + max Clock to FF2 + Hold of FF2 Slack = Arrival – Required = Violation if < 0


Setup Check w/ Input DelayEnter Constraint as Input Delay


Setup Check w/ Input DelayEnter Constraint as External Setup/Hold


Setup Check w/ Input Delay in SmartTime for RTAX-S Timing Analysis

Setup Check Arrival time = Launch edge (0) + max input delay + max Data path Required time = Capture edge (T) + min Clock to FF1 – Setup of FF1 Slack = Required – Arrival = Violation if < 0


Setup Check w/ Output DelayEnter Constraint as Output Delay


Setup Check w/ Output DelayEnter Constraint as Clock-to-Out


Setup Check w/ Output Delay in SmartTime for RTAX-S Timing Analysis

Setup Check Arrival time = Launch edge (0) + max Data path Required time = Capture edge (T) – Output Delay Slack = Required – Arrival = Violation if < 0


Inter-Clock Domains Timing AnalysisLarger designs may require interfacing between

different clock domainsDesigns with inter-clock domains requires timing

verification between the related clocks When functional paths exist across two clock domains, accurate

specification of both clocks is required to allow a valid inter-clock domain timing check

This is important especially when the clocks are specified with different waveforms and frequencies

First step is to consider whether the inter-clock domain paths are false or functional

If functional, setup and hold check must be performed


Inter-Clock Domains Timing Analysis

SmartTime timing analyzer for Actel RTAX-S FPGA timing analysis SmartTime looks at the relationship between the active clock edges over a full repeating

cycle, equal to the least common multiple of the two clock periods The new common period represents a full repeating cycle (or pattern) of the two clock

waveforms For setup check, the tightest relation launch-capture is considered to ensure that the data

arrives before the capture edge The hold check verifies that a setup relationship is not overwritten by a following data

launch

CLK2

FF2FF1

CLK1

CLK1FF1

CLK1FF2

Repeating cycle

setup1 setup2


Inter-Clock Domains in SmartTime


Timing Report Options Timing Report can be generated with different options,

providing flexibility and customization for users General setup

Filter report by slack threshold Report using Maximum or Minimum delay analysis

Paths and Sets Limit the number of paths to be reported in the timing report

Clock Domains Limit reporting of clock domains to specific domains

More clear reporting format Improvement over previous timing tool


Key enhancements from old timing report vs. new timing report Old report format

New report format shows more detail for the specified path

Timing Report Summary

$Registers(Clock):$ClockPins() to $Registers(Clock):$InputPins

Delay(ns) Slack(ns) Pins9.17 N/A From: DFN1C1_Q_9_inst:CLK

To: DFN1C1_Q_31_inst:D

Set Register to Register From: DFN1C1_Q_9_inst:CLK To: DFN1C1_Q_31_inst:D Delay (ns): 9.17 Slack (ns): 40.301 Arrival (ns): 13.133 Required (ns): 53.434 Setup (ns): 0.539 Minimum Period (ns): 9.709


Timing Report Summary (cont’d) Additional details are available (expanded path) in the new timing report

Clock Domain: ClockExpanded Path 1 From: DFN1C1_Q_9_inst:CLK To: DFN1C1_Q_31_inst:D data required time 53.434 data arrival time - 13.133 slack 40.301 ________________________________________________________ Data arrival time calculation 0.000 Clock + 3.973 clock network 3.973 DFN1C1_Q_9_inst:CLK (r) + 0.568 cell: ADLIB:DFN1C1 4.541 DFN1C1_Q_9_inst:Q (r) + 1.478 net: q_9_net_c ... ... ... 12.821 XOR2_Sum_31_inst:Y (f) + 0.312 net: sum_31_net 13.133 DFN1C1_Q_31_inst:D (f) 13.133 data arrival time ________________________________________________________ Data required time calculation 50.000 Clock + 3.973 clock network 53.973 DFN1C1_Q_31_inst:CLK (r) - 0.539 Library setup: ADLIB:DFN1C1 53.434 DFN1C1_Q_31_inst:D 53.434 data required time

leveraging software to enhance timing analysis for actel rtax-s devices

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