lecture note on verilog, course #90132300, ee, ntu, c.h tsai basic logic design with verilog ta:...

Lecture Note on Verilog, Course #90132300, EE, NTU, C.H Tsai

Basic Logic Designwith Verilog

TA: Chen-han Tsai

Lecture Note on Vrilog, Course #90132300, EE, NTU C.H Tsai, 10/29/2004

Outline

Introduction to HDL/ Verilog Gate Level ModelingBehavioral Level ModelingTest benchSummary and NotesSimulation using Silos


Introduction to HDL/ Verilog


What is HDL/VerilogWhy use HDL (Hardware Description Language)?

HDL ←→ layout by humanReduce cost and time

Verilog is one of the most popular HDLsVHDL (another popular HDL)

Key features of VerilogSupports Various levels

Behavior level (Register Transfer Level, RTL)Gate levelSwitch level

Simulate design functions


Hardware Design Flow

RTLEditor

LogicSynthesizer

RTLSimulation

Gate LevelSimulation

Place & RoutePost Gate

LevelSimulation

Chip

RTL Code

Gate Level Code

Physical Layout

Tape Out

Designer

Level

High

Low

Cost

Low

High

Verilog


An Example1-bit Multiplexer

in1

in2

out0

1

sel

if (sel==0) out = in1;else out = in2;

out = (sel’‧in1) + (sel‧in2)

sel in1 in2 out

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

to “select” output


Gate Level Description

a1

a2

in1

in2

sel

outo1

iv_sel a1_o

a2_on1

iv_sel

Gate Level: you see only gates and wires in the code


Behavioral Level Description

RTL: you may see high level behavior in the code

always block assign


Verilog HDL Syntax


A Simple Verilog Code

declaration syntax

module name in/out port

port/wiredeclaration

kernel hardwaregate-connection/behavior


Module Basic building block in Verilog.Module1. Created by “declaration” (can’t be neste

d)2. Used by “instantiation“Interface is defined by portsMay contain instances of other modulesAll modules run concurrently


Module Instantiation

Adder

Adder Adder

Adder_tree

instance example


Port Connection

Connect module port by order listFA1 fa1(c_o, sum, a, b, c_i);

Not fully connectedFA1 fa3(c_o,, a, b, c_i);

Connect module port by nameFA1 fa2(.A(a), .B(b), .CO(c_o),.CI(c_i), .S(sum));Recommended


Verilog Language Rule

Case sensitive Identifiers:

Digits 1…9Underscore _Upper and lower case letters from the alphabet

Terminate line with semicolon “;”Comments:

Single line: // it’s a single line comment exampleMultiline: /* when the comment exceeds single line,

multiline comment is necessary*/


Register and NetRegisters

Keyword : reg, integer, time, realStorage elementAssignment in “always” block

NetsKeyword : wire, wand, wor, tri

triand, trior, supply0, supply1Doesn’t store value, just a connectioninput, output, inout are default “wire”Can’t appear in “always” block assignment


Value and Number expressions

Verilog value set consists of four basic values:

0 represent a logic zero or false condition

1 represent a logic one or true condition

x represent an unknown logic value

z represent a high-impedance stage


Value and Number Expressions : Examples

659 // unsized decimal‘h 837ff // unsized hexadecimal‘o7460 // unsized octal4af // illegal syntax4’b1001 // 4-bit binary5’D 3 // 5-bit decimal3’b01x // 3-bit number with

unknown LSB12’hx // 12-bit unknown8’d -6 // illegal syntax-8’d 6 // phrase as - (8’d6)

// underline usage27_195_00016’b0001_0101_0001_111132’h12ab_f001

// X and Z is sign-extended

reg [11:0] a;initialbegin

a = ‘hx; // yields xxxa = ‘h3x; // yields 03xa = ‘h0x; // yields 00x

end


Net Concatenations : An Easy Way to Group Nets

Representations Meanings

{b[3:0],c[2:0]} {b[3] ,b[2] ,b[1] ,b[0], c[2] ,c[1] ,c[0]}{a,b[3:0],w,3’b101} {a,b[3] ,b[2] ,b[1] ,b[0],w,1’b1,1’b0,1’b1}{4{w}} {w,w,w,w}{b,{3{a,b}}} {b,a,b,a,b,a,b}

3‘o7

Module A

Module B

Module C


(excerpts from CIC training course ： Verilog_9807.pdf)


Compiler Directives `define

`define RAM_SIZE 16Defining a name and gives a constant value to it.

`include`include adder.vIncluding the entire contents of other verilog source file.

`timescale`timescale 100ns/1nsSetting the reference time unit and time precision of your simulation.Only 1, 10, and 100 are legal values.


System Tasks$monitor

$monitor ($time,"%d %d %d",address,sinout,cosout);Displays the values of the argument list whenever any

of the arguments change except $time.$display

$display ("%d %d %d",address,sinout,cosout);Prints out the current values of the signals in the

argument list$finish

$finishTerminate the simulation


Gate Level Modeling

•Gate Level Modeling•Primitives•Case Study


Gate Level ModelingSteps

Design the smallest sub-modulesConstruct modules with built sub-modulesConnections

Use “assign a = b;” to connect a and b (a is driven by b)

HDL: Hardware Description LanguageArchitecture figure first, then start to write code!!


Primitives

Primitives are modules ready to be instancedVerilog build-in primitive gate

not, bufand, or, not, buf, xor, nand, nor, xnor

Design wareVender-provided primitive gates

User-built primitive gateYour building block modules (sub-modules)


Case Study1-bit Full Adder

Ci A B SCo

0 0 0 00

0 0 1 10

0 1 0 10

0 1 1 01

1 0 0 10

1 0 1 01

1 1 0 01

1 1 1 11

A B

CiCo

S

FullAdder



Co = (A‧B‧Ci’)+(A‧B’‧Ci)+(A’‧B‧Ci)+(A‧B‧Ci)= (A‧B‧Ci’)+(A‧B’‧Ci)+ (B‧Ci)= { A‧[ (B‧Ci’)+(B’‧Ci) ] } + (B‧Ci)

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co



S = (A’‧B’‧Ci)+(A’‧B‧Ci’)+(A‧B’‧Ci’)+(A‧B‧Ci)= { A’‧[ (B’‧Ci)+(B‧Ci’) ] } + { A‧[ (B’‧Ci’)+(B‧Ci) ] }

A9

O2

A

A4B’Ci

A5BCi’ A6

A’O4

O3

A8B

A7B’Ci’

Ci

S



Design hierarchy

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co

A9

O2

A

A4B’Ci

A5BCi’ A6

A’O4

O3

A8B

A7B’Ci’

Ci

S

Co connect

S connect

Full Adder

AND

OR



Basic gate: 1-bit AND



Basic gate: 1-bit OR



Connect coInstance AND, OR gates

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co



Connect sInstance AND, OR gates

A9

O2

A

A4B’Ci

A5BCi’ A6

A’O4

O3

A8B

A7B’Ci’

Ci

S



Full Adder ConnectionInstance co, s

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co

A9

O2

A

A4B’Ci

A5BCi’ A6

A’O4

O3

A8B

A7B’Ci’

Ci

S

Co connect

S connect

Full Adder



Code


However… Further Reduction is

Possible

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co

A9

O2

A

A4B’Ci

A5BCi’ A6

A’O4

O3

A8B

A7B’Ci’

Ci

S

A3

O0

B

Ci

A0B’

Ci

A1BCi’ A2

AO1 Co

A9A

A6A’

O4 S

-1


Behavioral Level Modeling

•Behavioral Level Modeling•Case Study


Behavioral Level ModelingHigh level description

User friendlyConcise code

Widely used for some common operations

+,-,*&,|,~

Two main formatsalways blockassign



A B

CiCo

S

FullAdder

{Co,S} = A + B + Ci



LHS signals in always block should be declared as “reg”


Test bench


Test bench Usage

DesignTop Module

input ports

output ports

Test bench

data_oEqual?

answer_o

data_i


SummaryDesign module

Gate level or behavior levelReal hardware

Modules exists all the timeEach module has architecture figure

Plot architecture figures before you write verilog codesTest bench

Feed input data and compare output values versus timeUsually behavior levelNot real hardware, just like C/C++


NoteVerilog is a platform

Support hardware design (design module)Also support C/C++ like coding (test bench)

How to write verilog wellKnow basic concepts and syntaxGet a good reference (a person or some code files)Form a good coding habit

Naming rule, comments, format partition (assign or always block)

HardwareCombinational circuits (today’s topic)

畫圖 (architecture), then 連連看 (coding)Sequential circuits (next topic)

register: element to store data


Simulation using Silos


Create new projectWrite your verilog design codeCreate a new project:

Project -> New -> (enter your project name)Include your verilog file(s)

(choose your .v file) -> (click Add bottom) -> (click OK)Note that testbench should be included

Then run and debug


Run and Debug Run

Press F5 or click the “GO” icon on tool barAn output window is generated to show whether there exists errors.

DebugPress “open analyzer” on the toolbarPress “open explorer” on the toolbar

Choose signals you want to watchClick right button and select “Add signal to analyzer”

Then you can debug with waveform

lecture note on verilog, course #90132300, ee, ntu, c.h tsai basic logic design with verilog ta:...

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