lecture 8 –design rules - iran university of science and...

Adib AbrishamifarEE Department

IUST

Lecture 8 – Design Rules

Digital Integrated Circuit Design

IUST: Digital IC Design LECTURE 8 : Design RulesLECTURE 8 : Design Rules Adib Abrishamifar 20082/50

} Design Rules} CMOS Process Layers} Intra-Layer Design Rules} Via’s and Contacts} Select Layer} Example

} Cell Design} Standard Cells} Datapath Cells

} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation

} Summary

Contents


} Interface between designer and process engineer} Guidelines for constructing process masks} Unit dimension: Minimum line width} scalable design rules: lambda parameter} absolute dimensions (micron rules)

Design Rules


Layer

PolysiliconMetal1Metal2Contact To PolyContact To DiffusionVia

Well (p,n)Active Area (n+,p+)

Color Representation

YellowGreen

RedBlueMagentaBlackBlackBlack

Select (p+,n+) Green

Design Rules

} CMOS Process Layers


Metal2 4

3

10

90

Well

Active3

3

Polysilicon2

2

Different PotentialSame Potential

Metal1 3

32

Contactor Via

Select2

or6

2Hole

} Intra-Layer Design Rules

Design Rules


} Transistor Layout

Design Rules

1

2

5

3

Tran

sisto

r


1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

Design Rules

} Via’s and Contacts


1

3 3

2

2

2

WellSubstrate

Select3

5

Design Rules

} Select Layer


A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’

Design Rules

} CMOS Inverter Layout





} Summary

Contents


} Standard Cells} General purpose logic} Can be synthesized} Same height, varying width

} Datapath Cells} For regular, structured designs (arithmetic)} Includes some wiring in the cell} Fixed height and width

Cell Design


} Layout can be very time consuming} Design gates to fit together nicely} Build a library of standard cells

} Standard cell design methodology} Vdd and GND should abut (standard height)} Adjacent gates should satisfy design rules} NMOS at bottom and PMOS at top} All gates include well and substrate contacts

Cell Design


signals

Routingchannel

VDD

GND

Cell Design

} Standard Cell Layout Methodology-1980s


M1

No Routingchannels VDD

GNDM2

VDD

GND

Mirrored Cell

Mirrored Cell

Cell Design

} Standard Cell Layout Methodology-1990s


Cell boundary

N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects

Cell height is “12 pitch”

2λ

Rails ~10λ

In Out

VDD

GND

Cell Design

} Standard Cells


In Out

VDD

GND

In Out

VDD

GND

With silicideddiffusion

With minimaldiffusionrouting

OutIn

VDD

M 2

M 1

Cell Design

} Standard Cells


A

Out

VDD

GND

B

2-input NAND gate

B

VDD

A

Cell Design

} Standard Cells


OutIn

VDD

PMOS

NMOS

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

Contacts

N Well

Cell Design

} Standard Cells} CMOS Inverter


Connect in Metal

Share power and ground

Cell Design

} Standard Cells} Two Inverters

VDD


One finger Two fingers (folded)

Less diffusion capacitance

} Multi-Fingered Transistors

Cell Design


Cell Design

} Inverter


} NAND3} Horizontal N-diffusion and P-diffusion strips} Vertical polysilicon gates} Metal1 Vdd rail at top} Metal1 GND rail at bottom

Cell Design





} Summary

Contents


} To help plan layout quickly• Need not be to scale• Draw with color pencils or dry-erase markers

Sticks Diagrams


In

Out

VDD

GND

Inverter

A

Out

VDD

GNDB

NAND2

Sticks Diagrams

} Contains No Dimensions} Represents Relative Positions of Transistors


} Stick Diagram for a 4-input NOR Gate

AVDD

GND

B C

Y

D

Sticks Diagrams

A

B

C

D

A B C D

Vdd+

Y


j

VDDX

X

i

GND

AB

C

(PUN)

(PDN)

Logic Graph

} Logic Graph

Sticks Diagrams

Pull Up Network

Pull Down Network


C

A B

X = (A+B)•(C+D)

B

A

D

VDDX

X

GND

AB

C

PUN

PDN

C

D

D

ABCD

} OAI22 Logic Graph

Sticks Diagrams


C

A B

X = C • (A + B)

B

AC

i

j

j

VDDX

X

i

GND

AB

C

PUN

PDNABC

Logic Graph

} Logic Graph

Sticks Diagrams


X

CA B A B C

X

VDD

GND

VDD

GND

} Two Versions of C(A + B)

Sticks Diagrams


j

VDDX

X

i

GND

AB

C

A B C

} Consistent Euler Path

Sticks Diagrams


} Euler Path and Circuit } As legend has it, a resident of Konigsberg wrote to

Leonard Euler saying that a popular pastime for couples was to try to cross each of the seven bridges in the city exactly once, without crossing any bridge more than once

} It was well-known that the feat could not be accomplished, yet no one knew why. Could Euler, great mathematician as he was, answer that question

Sticks Diagrams


} Euler Path and Circuit } In Konigsberg, Germany, a river ran through the city

such that in its center was an island, and after passing the island, the river broke into two parts. Seven bridges were built so that the people of the city could get from one part to another as below

Sticks Diagrams


} Euler Path and Circuit } Euler realized that all problems of this form could be

represented by replacing areas of land by points (he called them vertices), and the bridges to and from them by arcs

Sticks Diagrams


} Euler Path and Circuit } Once the problem is simplified the graph of the

bridges and land look like this

Sticks Diagrams


} Euler Path and Circuit } The problem now becomes one of drawing this

picture without retracing any line and without picking your pencil up off the paper

Sticks Diagrams


} Euler Path and Circuit } Euler looked at the vertices that had an odd number

of lines connected to it} He stated they would either be the beginning or end

of his pencil-path

Sticks Diagrams


} Euler Path and Circuit } Euler path: a continuous path that passes through

every edge once and only once} Euler circuit: when a Euler path begins and ends at

the same vertex

Sticks Diagrams


} Euler Path and Circuit } Euler’s 1st Theorem

• If a graph has any vertices of odd degree, then it can't have any Euler circuit

• If a graph is connected and every vertex has an even degree, then it has at least one Euler circuit (usually more)

Sticks Diagrams


} Euler Path and Circuit } Euler’s 2nd Theorem

• If a graph has more than two vertices of odd degree, then it cannot have an Euler path

• If a graph is connected and has exactly two vertices of odd degree, then is has at least one Euler path. Any such path must start at one of the odd degree vertices and must end at the other odd degree vertex

Sticks Diagrams


} Euler Path and Circuit } Path, circuit, or neither…?

Sticks Diagrams


GND

x

a

b c

d

VDDx

GND

x

a

b c

d

VDDx

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

a c d

x

VDD

GND

(c) stick diagram for ordering {a b c d}b

} Example: x = ab + cd

Sticks Diagrams


} Area Estimation} Wiring Tracks

• A wiring track is the space required for a wire– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch

• Transistors also consume one wiring track

Sticks Diagrams


} Area Estimation} Well Spacing

• Wells must surround transistors by 6 λ– Implies 12 λ between opposite transistor flavors– Leaves room for one wire track

Sticks Diagrams


} Area Estimation} Estimate area by counting wiring tracks

• Multiply by 8 to express in λ

Sticks Diagrams


} Area Estimation} Stick diagram for O3AI and

estimate area

• Y = ( A + B + C) D

Sticks Diagrams

A

B

C

D

B C

D

Vdd+

Y

A


} Area Estimation} Stick diagram for O3AI and estimate area

• Y = ( A + B + C) D

Sticks Diagrams


} Area Estimation} Sketch a stick diagram for O3AI and estimate area

• Y = ( A + B + C) D

Sticks Diagrams





} Summary

Contents


Summary

} This lecture describes the basic design rules for the layout of both MOS and CMOS transistors, cells design methodologies and also sticks diagrams. Specifically described in detail are:} Design Rules} Cells Design Methodologies} Sticks Diagrams} Logic Graph} Euler Path} Area Estimation

lecture 8 –design rules - iran university of science and...

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