lecture 3 operational amplifiersnon-ideal behavior 1
TRANSCRIPT
Lecture 3Operational Amplifiers—Non-ideal
behavior
1
Goals
• Study non-ideal op amp behavior.
• Demonstrate circuit analysis techniques for non-ideal op amps.
• Understand frequency response limitations of op amp circuits.
2
vi2 = 0
v+ = 0 = v-, vo(1) = -R2.vi1 (inverting amplifier) R1
Vi1 = 0
V+ = R4. vi2, vo(2) = (1+ R2/R1) . R4.vi2 R3 + R4 R3+R4
non-inverting amplifier
vo = vo(1) + vo(2)
= (1+ R2). R4 vi2 - R2.Vi1
R1 R3 + R4 R1
Difference Amplifier
Assume an ideal op-ampUse the superposition theory
Difference Amplifiers
In order to provide equal gain for both inputs vo = -R2/R1 (v1 – v2)
(1 + R2 ) . R4 = R2
R1 R3 + R4 R1
R4/R3 = R2/R1 Balance Condition
Difference Amplifier
• Also called a differential subtractor, amplifies difference between input signals.
• Rin2 is series combination of R1 and R2 because i+ is zero.
• For v2=0, Rin1= R1, as the circuit reduces to an inverting amplifier.
• For general case, i1 is a function of both v1 and v2.
)2
v1
(v
1
2v R
Ro
For R2= R1)
2v
1(vv o
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Difference Amplifier
vicm, and vid are another representation for the inputs
vo = Ad vid + Acmvicm
Differential gain
Common-modegain
For the ideal case, vo = -R2/R1(v1 – v2) = (-R2/R1).vid + 0
Ad = -R2/R1, and Acm = 0
If balance condition is not satisfied, (R4/R3≠ R2/R1) Then Acm ≠ 0
vid = v1 – v2 differential input voltagevicm = (v1 + v2)/2 Common-mode input voltage
Define
Figure of meritThe Common-mode rejection ratioCMRR = 20.LOG |Ad| in dB , For Acm = 0, CMRR = 8
|Acm|
V id
1 2
4
3
v1
v2
+
-
Ad = vo / vid
1 2
4
3
Acm = vo / vicm
Vicm
+
Figure of meritThe Common-mode rejection ratioCMRR = 20.LOG |Ad| in dB , For Acm = 0, CMRR = 8
|Acm|
V id
1 2
4
3
v1
v2
+
-
Ad = vo / vid
1 2
4
3
Acm = vo / vicm
Vicm
+
Difference Amplifier FOM
Integrator
• Feedback resistor R2 in the inverting amplifier is replaced by capacitor C.
• The circuit uses frequency-dependent feedback.
Rsv
si dt
odvCci
Since ic= is
)0()0(
)0(0
)(1)(
1
cVov
ovdt
svRC
tov
dsvRCodv
Voltage at the circuit’s output at time t is given by the initial capacitor voltage integral of the input signal from start of
integration interval, here, t=0.Integration of an input step signal results in a ramp at the output.
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Differentiator
• Input resistor R1 in the inverting amplifier is replaced by capacitor C.
• Derivative operation emphasizes high-frequency components of input signal, hence is less often used than the integrator.
Rov
Ri dt
sdvCsi
Since iR= is
dtsdv
RCov
Output is scaled version of derivative of input voltage.
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Operational Amplifier Complete Model
Represented by:
A= open-circuit voltage gain
vid = (v+-v-) = differential input signal voltage
Rid = amplifier input resistance
Ro = amplifier output resistance
3
Non-ideal Operational Amplifier
• Various error terms arise in practical operational amplifiers due to non-ideal behavior.
• Some of the non-ideal characteristics include:
– √ Finite open-loop gain that causes gain error
– Nonzero output resistance
– Finite input resistance
– Finite CMRR
– Common-mode input resistance
– √ DC error sources
– √ Output voltage and current limits
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Vo
+VS
-VS
-+
+
-
A VinV+
V-
Vin = V+ - V-
vo = A (v+ - v-) = A.vin
|v+ - v- | > 0
Finite Open-loop Gain
Example 1, Inverting Amplifier
S
SV-
V+
i
i
12
in
f
in
out
in
in
f
in
out
in
in
inffout
in
in
in
out
f
out
f
out
outout
in
in
in
-
f
-
f
out
f
out-
in
in
-
R
R
v
vA
ARA
R
R
v
v p gain Closed loo
R
v
ARARRv
R
v
AR
v
AR
v
R
v
Avv)-vA(v,vv
R
v
R
v
R
v
R
v
R
- vv
R
vv i
, V
inite pedance ise input imtill assum, We can s i i
,
111
111
,0
0
inf0
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DC Error Sources: Input-Offset Voltage
AoV
OSV
vo=A(v+-v-), if v+ = v-
Then vo = 0 (Ideal case)
For real op-amp an input dc offset exists that can saturates the output.
We can bring the output back to zero by applying an external voltage equal in magnitude but opposite in direction to the offset voltage
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Finding the error in the output voltage produced by the offset (vos)
osoe
os
vR
Rv
vvv
)1
21(
Consider only the offset voltage. i.e set any input signal to zeroVoe = output error due to vos
If an input signal is connected to R1Total output =
osi vR
Rv
R
Rvo )1(
1
2
1
2
Desired output error
FOR LF351, vos = 5mV (typical)
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DC Error Sources: Input-Offset Voltage (Example)
Problem: Find quiescent dc voltage at output.
Given data: R1 =1.2 k, R2 = 99 k
Assumptions: Ideal op amp except for nonzero offset voltage.
mV3OS
V
Output voltage is given by
Actual sign of VOS is unknown as only upper bound is given.Note: Offset voltage of most IC op amps can be manually adjusted by adding a potentiometer as shown.
V25.0)003.0(1.2k99k1
OSV
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Bias currents IB1 and IB2 ( base currents in BJTs or gate currents in MOSFETs or JFETs) are similar in value with directions depending on internal amplifier circuit type
21
12
2
BBos
BBB
III
III
+-IB
IB
Ios/2
IB2
IB1
Ideal -opamp
Equivalent circuit model
Sign of offset current is unknown as only upper bound is given.
DC Error Sources: Input-Bias and Offset Currents
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DC Error Sources: Input-Bias and Offset Currents
In inverting amplifier shown, IB1
shorted out by ground connection. Since,inverting input is at virtual ground, amplifier output is forced to supply IB2 through R2 .
22R
BIoV
18
Set vin=0, v- = v+ = 0 (virtual gnd)i1=0, i2=IB2
i1
i2
This poses a limitation on the value of R2
Numerical Example
nAInAI
OR
nAInAI
nAII
nAIII
nAInAIgiven
BB
BB
BB
BBB
osB
95 ,105
105 ,95
10
2002
10 ,100
12
12
21
21
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DC Error Sources: Input-Bias and Offset Currents - Bias Current Compensation
Bias current compensation resistor RB is used in series with non-inverting input. Output due to IB1 alone is
1
211 R
R
BRB
IoV
By superposition,
if .
Since, offset current is typically 5.10 times smaller than individual bias currents, dc output voltage error can be reduced by using bias compensation.
22)
12(
1
21122
ROS
IRB
IB
I
R
R
BRB
IRB
IToV
2//
121
21 RRRR
RR
BR
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DC Error Sources: Input-Bias and Offset Currents - Errors in Integrator
At t<0, reset switch is closed, circuit becomes a voltage-follower,
OSVoV
At t=0, reset switch is opened, circuit starts integrating its own offset voltage and bias current. Using superposition analysis,
Output becomes ramp with slope determined by VOS and IB2 and saturates at one of the power supplies.
tCB
It
RCOS
V
OSVtov 2)(
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