lecture 3 – common elements
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Lecture 3 – Common Elements. 9/26/2008. ECE 561 - Lecture . 1. Common Logic Elements. Review Lecture 2 sequential elements Examine the data sheet for some of these elements When using element in a design you start with the documentation for the element. 9/26/2008. ECE 561 - Lecture . 2. - PowerPoint PPT PresentationTRANSCRIPT
9/28/089/26/2008 ECE 561 - Lecture 1
Lecture 3 – Common Elements
9/26/2008 1ECE 561 - Lecture
9/28/089/26/2008 ECE 561 - Lecture 2
Common Logic Elements
• Review Lecture 2 sequential elements• Examine the data sheet for some of these
elements• When using element in a design you start with
the documentation for the element
9/26/2008 2ECE 561 - Lecture
9/28/089/26/2008 ECE 561 - Lecture 3
Common Sequential Elements
• Basic Element– The Latch – A latch is a level sensitive component
that stores and holds a value– What does level sensitive mean?
• Flip Flops are edge triggered elements– F/F can be constructed of a Master Slave arrangement of 2
latches– Master is level sensitive to new input– On edge master is locked and its value is transmitted to the
slave
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Another Basic Elements
• Register– Registers are composed of latches or F/Fs– Several uses• Register sets – driven from/drive busses• Input register for functional units• Output hold register for a functional unit• Configuration register
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Edge Triggered F/F
• Edge triggered flip-flops can be– Master Slave – formed from 2 latches
– Discrete design
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Sequential ComponentsMultiple ICs
• Cascaded Elements (Registers, Counters)• State Machines (FSM)• Controllers• Cooperating State Machines
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Data Books
• Data Books List Components and their parameters
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More Data Book Components
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D F/F Data Sheet
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The inputs and outputs specs
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The circuit Implementation
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Various type of implmentation
• Note this is• A Master-Slave• Implementation
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Timing
• And has its own• Implementation• And timing
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Voltage and Current Specs
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Higher level components
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Use of data
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Use of data
• You use the data to analyze circuit and then can answer questions on it as illustrated in the following
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Some Specifications
Clock Period
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Solution
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What are the states
• Develop the state table• Pick a state to start with
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Self Starting Circuits
• Circuits that end up in a valid state regardless of the state the FSM starts in.
• Is this circuit self starting?
• Go to www.wikipedia.com and look at material there on Finite State Machine