lecture 240 – cascode op amps - phillip...
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Lecture 240 Cascode Op Amps (3/28/10) Page 240-1
CMOS Analog Circuit Design © P.E. Allen - 2010
LECTURE 240 – CASCODE OP AMPSLECTURE ORGANIZATION
Outline• Lecture Organization• Single Stage Cascode Op Amps• Two Stage Cascode Op Amps• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 293-310
Lecture 240 Cascode Op Amps (3/28/10) Page 240-2
CMOS Analog Circuit Design © P.E. Allen - 2010
Cascode Op AmpsWhy cascode op amps?
• Control of the frequency behavior• Can get more gain by increasing the output resistance of a stage• In the past section, PSRR of the two-stage op amp was insufficient for many
applications• A two-stage op amp can become unstable for large load capacitors (if nulling resistor
is not used)• The cascode op amp leads to wider ICMR and/or smaller power supply requirements
Where Should the Cascode Technique be Used?
• First stage -
Good noise performanceRequires level translation to second stageDegrades the Miller compensation
• Second stage -
Self compensatingIncreases the efficiency of the Miller compensation Increases PSRR
Lecture 240 Cascode Op Amps (3/28/10) Page 240-3
CMOS Analog Circuit Design © P.E. Allen - 2010
SINGLE STAGE CASCODE OP AMPSSimple Single Stage Cascode Op Amp
060627-01
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VNBias1+
-
VBias
2vin2
-
+
MC2MC1
MC4MC3
-
+ vin
M1 M2
M3 M4
M5
VDD
VSS
+
-
2vin2
-+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
-
+
VBias
Implementation of the floating voltage VBiaswhich must equal2VON + VT.
VPBias2
VNBias1
VPBias2
Rout of the first stage is RI (gmC2rdsC2rds2)||(gmC4rdsC4rds4)
Voltage gain = vo1
vin = gm1RI [The gain is increased by approximately 0.5(gMCrdsC)]
As a single stage op amp, the compensation capacitor becomes the load capacitor.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-1 Single-Stage, Cascode Op Amp PerformanceAssume that all W/L ratios are 10 μm/1 μm, and that IDS1 = IDS2 = 50 μA of single
stage op amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz.Use KN’ = 120μA/V2, KP’ = 25μA/V2, VTN = 0.5V, VTP = -0.5V, N = 0.06V-1 and P =
0.08V-1.Solution
The device transconductances aregm1 = gm2 = gmI = 346.4 μS
gmC1 = gmC2 = 346.4μS
gmC3 = gmC4 = 158.1 μS.
The output resistance of the NMOS and PMOS devices is 0.333 M and 0.25 M ,respectively.
RI = 7.86 M
Av(0) = 2,722 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.51 pF.
What happens if a 100pF capacitor is attached to this op amp?GB goes from 10MHz to 0.551MHz.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-5
CMOS Analog Circuit Design © P.E. Allen - 2010
060627-02
+
−vIN
vOUT
M1 M2
M3 M4
M5 M6
M7 M8
M9
VDD
VNB1
-A
-A-A
+
−vIN
vOUT
M1 M2
M3 M4
M5 M6
M7 M8
M9
VDD
VNB1 M10
VNB1
VDD VDDVPB1
M11 M12
M13 M14
M15
M16
Enhanced Gain, Single Stage, Cascode Op Amp
From inspection, we can write the voltage gain as,
Av = vOUTvIN
= gm1Rout where Rout = (Ards6gm6rds8)|| (Ards2gm4rds4)
Since A gmrds/2 the voltage gain would be equal to 100,000 to 500,000.
Output is not optimized for maximum signal swing.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-6
CMOS Analog Circuit Design © P.E. Allen - 2010
TWO-STAGE, CASCODE OP AMPSTwo-Stage Op Amp with a Cascoded First-Stage
070427-01
Cc
-
+vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias+
-
R
2vin2-
+
MC2MC1
MC4MC3
MB1 MB2
MB3 MB4
MB5
-
+
VBias
MT1
MT2
M6
M7
vout
ID6
W6/L6
VSG6
= VSD4
VSG6 =
VSD4+VSDC4
W6’/L6’<< W6/L6
VT6
Current
Volts
• MT1 and MT2 are required for level shiftingfrom the first-stage to the second.
• The PSRR+ is improved by the presence of MT1• Internal loop pole at the gate of M6 may cause
the Miller compensation to fail.• The voltage gain of this op amp could easily be 100,000V/V
σ
jω
z1p1p2p3Fig. 6.5-2A
Lecture 240 Cascode Op Amps (3/28/10) Page 240-7
CMOS Analog Circuit Design © P.E. Allen - 2010
Two-Stage Op Amp with a Cascode Second-Stage
Av = gmIgmIIRIRIIwhere gmI = gm1 = gm2, gmII = gm6,
RI = 1
gds2 + gds4 =
2( 2 + 4)ID5
and
RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
Comments:• The second-stage gain has greatly
increased improving the Miller compensation
• The overall gain is approximately (gmrds)3 or very large
• Output pole, p2, is approximately the same if Cc is constant
• The zero RHP is the same if Cc is constant
• PSRR is poor unless the Miller compensation is removed (then the op amp becomesself compensated)
-
+
vinM1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias+
-
Cc
CL
VBP
VBN
MC6
MC7
Fig. 6.5-3
Rz
Lecture 240 Cascode Op Amps (3/28/10) Page 240-8
CMOS Analog Circuit Design © P.E. Allen - 2010
A Balanced, Two-Stage Op Amp using a Cascode Output Stage
vout = gm1gm8
gm3
vin2 +
gm2gm6
gm4
vin2 RII
= gm1
2 +gm2
2 kvin RII = gm1·k·RII vinwhereRII = (gm7rds7rds6)||(gm12rds12rds11)and
k = gm8gm3 =
gm6gm4
This op amp is balanced because thedrain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
Slew rate = Iout
CLGB =
gm1gm8
gm3CLAv =
12
gm1gm8
gm3+
gm2gm6
gm4 RII
Vin(max) = VDD I5
3
1/2 |VTO3|(max) +VT1(min) Vin(min) = VS S + VDS5 +
I5
1
1/2 + VT1(min)
060627-03
-
+
vinM1 M2
M3
M4
M5
M6
M11
vout
VDD
VSS
+
-
CLM9
M10
M8
M12
M7VPB2
VNB2
VNB1
Lecture 240 Cascode Op Amps (3/28/10) Page 240-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 Design of Balanced, Cascoded Output Stage Op AmpDesign a balanced, cascoded output stage op amp using the procedure outlined
above. The specifications of the design are as follows:VDD = 2.5 V (VSS = 0) Slew rate = 5 V/μs with a 50 pF load
GB = 10 MHz with a 25 pF load Av 5000
Input CMR = 1V to +2 V 0.5V < Output swing < 2 V
Use KN’=120μA/V2, KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P =
0.08V-1and let all device lengths be 0.5 μm.Solution
While numerous approaches can be taken, we shall follow one based on the abovespecifications. The steps will be numbered to help illustrate the procedure.1.) The first step will be to find the maximum source/sink current. This is found from theslew rate.
Isource/Isink = CL slew rate = 50 pF(5 V/μs) = 250 μA
2.) Next some W/L constraints based on the maximum output source/sink current aredeveloped. Under dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current ifS3 = S4, S6 = S8, and S10 = S11
Lecture 240 Cascode Op Amps (3/28/10) Page 240-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued3.) Choose I5 as 100 μA. This current (which can be changed later) gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for +0.5V output capability. We shall assume that the output mustsource or sink the 250μA at the peak values of output. First consider the negative outputpeak. Since there is 0.5V difference between VSS(0V) and the minimum output, letVDS11(sat) = VDS12(sat) = 0.25 V (we continue to ignore the bulk effects). Under themaximum negative peak assume that I11 = I12 = 250 μA. Therefore
0.25 = 2I11
K'NS11 =
2I12K'NS12
= 500 μA
(120 μA/V2)S11
which gives S11 = S12 = 67 and S9 = S10 = 67. For a maximum output voltage of 2V, weget
0.25 = 2I6
K'PS6 =
2I7K'PS7
= 500 μA
(25 μA/V2)S6
which gives S6 = S7 = S8 = 320 and S3 = S4 = (320/2.5) = 128.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-11
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued5.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 67. Using ICMRrelationship, we find that S3 should be at least 8. A larger value of S3 will give a highervalue of Vin(max) so that we continue to use S3 = 67 which gives Vin(max) = 2.32V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth.Assuming a Cox of 6fF/μm2 gives the first-stage pole of
p3 = -gm3
Cgs3+Cgs8 =
- 2K’PS3I3(0.667)(W3L3+W8L8)Cox
= 3.125x109 rads/sec or 497 MHz
which is much greater than 10GB.6.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain is
Av = (gm1/2gm4)(gm6 + gm8) RII
Note, a current gain of k can be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
gm6
gm4 =
gm11
gm3 =
2KP’·S6·I62KP’·S4·I4 = k
Calculating the various transconductances we get gm4 = 566 μS, gm6 = gm7 = gm8 = 1414μS, gm11 = gm12 = 1414 μS, rds6 = rd7 = 100 k , and rds11 = rds12 = 133 k . Assumingthat the gain Av must be greater than 5000 and k = 2.5 gives gm1 > 221 μS.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-12
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-2 - Continued (b.) The second method of finding gm1 is from the GB specifications. Multiplying thegain by the dominant pole (1/CIIRII) gives
GB = gm1(gm6 + gm8)
2gm4CL
Assuming that CL= 25 pF and using the specified GB gives gm1 = 628 μS.
Since this is greater than 221μS, we choose gm1 = gm2 = 628μS. Knowing I5 gives S1 =S2 = 32.9 33.
8.) The next step is to check that S1 and S2 are large enough to meet the +1V input CMRspecification. Use the saturation formula we find that VDS5 is 0.341 V. This gives S5 = 15.The gain becomes Av = 14,182V/V and GB = 10 MHz for a 25 pF load. We shall assumethat exceeding the specifications in this area is not detrimental to the performance of theop amp.9.) Knowing the currents and W/L values, the bias voltages VNB1, VNB2 and VPB2 can bedesigned.The W/L values resulting from this design procedure are shown below. The powerdissipation for this design is seen to be 350μA·2.5V = 0.875 mW.
S1 = S2 = 33 S3 = S4 = 128 S5 = 15S6 = S7 = S
8 = 320 S9 = S10 = S11 = S12 = 67
Lecture 240 Cascode Op Amps (3/28/10) Page 240-13
CMOS Analog Circuit Design © P.E. Allen - 2010
Technological Implications of the Cascode Configuration
Fig. 6.5-5
�� ��������Poly IIPoly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
If a double poly CMOS process is available, inter-node parasitics can be minimized.As an alternative, one should keep the drain/source between the transistors to a minimumarea.
Fig. 6.5-5A
�� �����Poly I
n+ n+n-channel
p substrate/well
A B C D
Thinoxide
A
B
C
D
Poly I
Minimum Polyseparation
����n-channeln+
Lecture 240 Cascode Op Amps (3/28/10) Page 240-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Input Common Mode Range for Two Types of Differential Amplifier Loads
vicm
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSG3
M1 M2
M3 M4
M5
VDD
VSS
VBias+
-
+
-
VSD3
VBP
+
-
VSD4
+
-
VSD4
VDD-VSG3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
vicm
VDD-VSD3+VTN
VSS+VDS5+VGS1
InputCommon
ModeRange
Differential amplifier witha current mirror load. Fig. 6.5-6
Differential amplifier withcurrent source loads.
In order to improve the ICMR, it is desirable to use current source (sink) loads withoutlosing half the gain.The resulting solution is the folded cascode op amp.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-15
CMOS Analog Circuit Design © P.E. Allen - 2010
The Folded Cascode Op Amp
Comments:• I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating• Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can beachieved if RA and RB are greater than gm1 or gm2.
060628-04
VPB1
M4 M5
RAI6
VPB2 RB
I4 I5
VDD
I7M6 M7
VNB2
M8 M9
M10 M11
+−vIN
vOUT
VNB1
I1 I2
M1 M2
M3I3
CL
Lecture 240 Cascode Op Amps (3/28/10) Page 240-16
CMOS Analog Circuit Design © P.E. Allen - 2010
Small-Signal Analysis of the Folded Cascode Op AmpModel:
Recalling what welearned about theresistance looking intothe source of thecascode transistor;
RA = rds6+(1/gm10)1 + gm6rds6
1
gm6 and RB =
rds7 + RII1 + gm7rds7
RII
gm7rds7 where RII gm9rds9rds11
The voltage transfer function can be found as follows. The current i10 is written as
i10 = -gm1(rds1||rds4)vin2[RA + (rds1||rds4)]
-gm1vin2
and the current i7 can be expressed as
i7 = gm2(rds2||rds5)vin
2RII
gm7rds7+ (rds2||rds5)
= gm2vin
2 1 +RII(gds2+gds5)
gm7rds7
= gm2vin2(1+k) where k =
RII(gds2+gds5)gm7rds7
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,voutvin
= gm12 +
gm22(1+k) Rout =
2+k2+2k gmIRout
060628-02
gm1vin2 rds1 rds4
rds6
gm6vgs6RA
gm2vin2 rds2 rds5
rds7
gm7vgs7
RII
RB
i10
i10+
-vgs7
+
-vgs6
+
-vout
i7
1gm10
Lecture 240 Cascode Op Amps (3/28/10) Page 240-17
CMOS Analog Circuit Design © P.E. Allen - 2010
Intuitive Analysis of the Folded Cascode Op AmpAssume that a voltage of V is applied. Weknow that
RA(M6) 1/gm6 and RB(M7) rds
The currents flowing to the output are,gm1 V
2 + gm2 V
4The output resistance is approximately,
Rout (gm9rds9rds11)||[ gm7rds7(rds2||rds5)]
gmrds2
3
Therefore, the approximate voltage gain is,
voutvin
= gm1
2 +gm24 Rout
3gm4 Rout =
gm2rds2
4
While the analysis is simpler than small signal analysis, the value of k defined in theprevious slide is 1.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-18
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Folded Cascode Op AmpThe frequency response of the folded cascode op amp is determined primarily by theoutput pole which is given as
pout = -1
Rout'Coutwhere Rout’ =
2+k2+2k Rout
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions foreach pole is1.) Pole at node A: pA - gm6/(Cgs+ 2Cdb)
2.) Pole at node B: pB - gm7/(Cgs+ 2Cdb)
3.) Pole at drain of M6: p6 -gm10/(2Cgs+ 2Cdb)
4.) Pole at source of M8: p8 -(gm8rds8gm10)/(Cgs+ Cdb)
5.) Pole at source of M9: p9 -gm9/(Cgs+ Cdb)
where the approximate expressions are found by the reciprocal product of the resistanceand parasitic capacitance seen to ground from a given node. One might feel that becauseRB is approximately rds that this pole also might be small. However, at frequencieswhere this pole has influence, Cout, causes Rout to be much smaller making pB also non-dominant.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-19
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-3 - Folded Cascode, CMOS Op AmpAssume that all gmN = gmP = 100μS, rdsN = 2M , rdsP = 1M , and CL = 10pF. Find allof the small-signal performance values for the folded-cascode op amp.
RII = 0.4G , RA = 10k , and RB = 4M k = 0.4x109(0.3x10-6)
100 = 1.2
voutvin
= 2+1.22+2.4 (100)(57.143) = 4,156V/V
Rout = RII ||[gm7rds7(rds5||rds2)] = 400M ||[(100)(0.667M )] = 57.143M
|pout| = 1
RoutCout =
157.143M ·10pF = 1,750 rads/sec. 278Hz GB = 1.21MHz
Lecture 240 Cascode Op Amps (3/28/10) Page 240-20
CMOS Analog Circuit Design © P.E. Allen - 2010
PSRR of the Folded Cascode Op Amp
Consider the following circuit used to model the PSRR-:
Vout
Vss
Cgd11
M11
M9
VDD
R
Fig. 6.5-9A
Vss Vout
Cgd9
Rout
+
-
Cgd9
VGS11
VGSG9
Vss
Vss
Vss
rds11
Cout
rds9
This model assumes that gate, source and drain of M11 and the gate and source of M9 allvary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
VoutVss
sCgd9Rout
sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-21
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the PSRR- of the Folded Cascode Op Amp
VoutVss
GB
Cgd9Rout
|PSRR-|
dB
0dB
Fig. 6.5-10A
log10(ω)
1
Cout
Cgd9
Other sources of Vss injection, i.e. rds9
Dominantpole frequency
|Avd(ω)|
We see that the PSRR of the cascode op amp is much better than the two-stage op ampwithout any modifications to improve the PSRR.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-22
CMOS Analog Circuit Design © P.E. Allen - 2010
Design Approach for the Folded-Cascode Op Amp
Step Relationship Design Equation/Constraint Comments1 Slew Rate I3 = SR·CL2 Bias currents in
output cascodesI4 = I5 = 1.2I3 to 1.5I3 Avoid zero current in
cascodes3 Maximum output
voltage,vout(max)
S5=2I5
KP’VSD52 , S7=2I7
KP’VSD72 , (S4=S5 and S6= S7)VSD5(sat)=VSD7(sat)= 0.5[VDD-Vout(max)]
4 Minimum outputvoltage, vout(min) S11=
2I11KN’VDS112 , S9=
2I9KN’VDS92 , (S10=S11and S8=S9)
VDS9(sat)=VDS11(sat)= 0.5[Vout(min)-VSS]
5GB =
gm1CL
S1=S2= gm12
KN’I3 =
GB2CL2
KN’I3
6 Minimum inputCM S3 =
2I3
KN’ Vin(min)-VSS- (I3/KN’S1) -VT12
7 Maximum inputCM S4 = S5 =
2I4KP’ VDD-Vin(max)+VT1
2 S4 and S5 must meet orexceed value in step 3
8 DifferentialVoltage Gain
voutvin
= gm1
2 +gm2
2(1+k) Rout = 2+k2+2k gmIRout k =
RII(gds2+gds4)gm7rds7
9 Power dissipation Pdiss = (VDD-VSS)(I3+I10+I11)
Lecture 240 Cascode Op Amps (3/28/10) Page 240-23
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 Design of a Folded-Cascode Op AmpDesign a folded-cascode op amp if the slew rate is 10V/μs, the load capacitor is 10pF, themaximum and minimum output voltages are 2V and 0.5V for a 2.5V power supply, theGB is 10MHz, the minimum input common mode voltage is +1V and the maximum inputcommon mode voltage is 2.5V. The differential voltage gain should be greater than3,000V/V and the power dissipation should be less than 5mW. Use KN’=120μA/V2,
KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P = 0.08V-1. Let L = 0.5 μm.
SolutionFollowing the approach outlined above we obtain the following results.
I3 = SR·CL = 10x106·10-11 = 100μA
Select I4 = I5 = 125μA.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
S4 = S5 = 2·125μA
25μA/V2·(0.25V)2 = 2·125·16
25 = 160
and assuming worst case currents in M6 and M7 gives,
S6 = S7 = 2·125μA
25μA/V2(0.25V)2 = 2·125·16
25 = 160 The value of 0.5(Vout(min)-|VSS|) is 0.25V which gives the value of S8, S9, S10 and S11 as
S8 = S9 = S10 = S11 = 2·I8
KN’VDS82 = 2·125
120·(0.25)2 = 20
Lecture 240 Cascode Op Amps (3/28/10) Page 240-24
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 - ContinuedIn step 5, the value of GB gives S1 and S2 as
S1 = S2 = GB2·CL2
KN’I3 =
(20 x106)2(10-11)2
120x10-6·100x10-6 = 32.9 33
The minimum input common mode voltage defines S3 as
S3 = 2I3
KN’ Vin(min)-VSS-I3
KN’S1- VT1
2 =
200x10-6
120x10-6 1.0+0-100
120·33 -0.5 2 = 14.3 15
We need to check that the values of S4 and S5 are large enough to satisfy the maximuminput common mode voltage. The maximum input common mode voltage of 2.5 requires
S4 = S5 2I4
KP’[VDD-Vin(max)+VT1]2 = 2·125μA
25x10-6μA/V2[0.5V]2 = 40
which is less than 160. In fact, with S4 = S5 = 160, the maximum input common modevoltage is 2.75V.The power dissipation is found to be
Pdiss = 2.5V(125μA+125μA) = 0.625mW
Lecture 240 Cascode Op Amps (3/28/10) Page 240-25
CMOS Analog Circuit Design © P.E. Allen - 2010
Example 240-4 - ContinuedThe small-signal voltage gain requires the following values to evaluate:
S4, S5: gm = 2·125·25·160 = 1000μS and gds = 125x10-6·0.08 = 10μS
S6, S7: gm = 2·75·25·1600 = 774.6μS and gds = 75x10-6·0.08 = 6μS
S8, S9, S10, S11: gm = 2·75·120·20 = 600μS and gds = 75x10-6·0.06 = 4.5μS
S1, S2: gmI = 2·50·120·33 = 629μS and gds = 50x10-6(0.06) = 3μS
Thus,
RII gm9rds9rds11 = (600μS)1
4.5μS1
4.5μS = 29.63M
Rout 29.63M ||(774.6μS)1
6μS1
10μS+3μS = 7.44M
k = RII(gds2+gds4)
gm7rds7 =
7.44M (3μS+10μS)(6μS)774.6μS = 0.75
The small-signal, differential-input, voltage gain is
Avd = 2+k
2+2k gmIRout = 2+0.752+1.5 0.629x10-3·7.44x106 = (0.786)(4680) = 3,678 V/V
The gain is slightly larger than the specified 3,000 V/V.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-26
CMOS Analog Circuit Design © P.E. Allen - 2010
Comments on Folded Cascode Op Amps• Good PSRR• Good ICMR• Self compensated• Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)• Need first stage gain for good noise performance• Widely used in telecommunication circuits where large dynamic range is required
Lecture 240 Cascode Op Amps (3/28/10) Page 240-27
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded Cascode Op AmpsIf more gain is needed, the folded cascode opamp can be enhanced to boost the outputimpedance even higher as follows.
Voltage gain = gm1Rout,
whereRout [Ards7gm7(rds1||rds5)]||
(Ards9gm9rds11)
Since A gmrds the voltage gain would be in the range of 100,000 to 500,000.
Note that to achieve maximum output swing, it will be necessary to make sure that M5and M11 are biased with VDS = VDS(sat).
060718-03
vOUT
M4M5
M3
M7
M8 M9
M10 M11
M6
VDD
VPB1
-A
-A-A
+
−vIN
M1 M2
VNB1
Lecture 240 Cascode Op Amps (3/28/10) Page 240-28
CMOS Analog Circuit Design © P.E. Allen - 2010
What are the Enhancement Amplifiers?Requirements:1.) Need a gain of gmrds.
2.) Must be able to set the dc voltage at its input to get wide-output voltage swing.Possible Enhancement Amplifiers:
060718-05
VDDVPB1
VPB2
VNB1VDD-VSD(Sat)
vin
vout
M1 M2
M3
M4
M5
M6
-A
vin
vout
VDDVPB1
VNB2
VNB1
vin
vout
VDS(Sat)M1 M2
M3
M4
M5
M6
vout
-A
vin
Lecture 240 Cascode Op Amps (3/28/10) Page 240-29
CMOS Analog Circuit Design © P.E. Allen - 2010
Enhanced-Gain, Folded Cascode Op AmpDetailed realization:
Lecture 240 Cascode Op Amps (3/28/10) Page 240-30
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Enhanced Gain Cascode Op AmpsNormally, the frequency response of the cascode op amps would have one dominant poleat the output. The frequency response would be,
Av(s) = gm1Rout(1/sCout)Rout +1/sCout
= gm1Rout
sRoutCout +1 = gm1Rout
1 -sp1
If the amplifier used to boost the output resistance had no frequency dependence then thefrequency response would be as follows.
060629-02
0dB
40dB
60dB
80dB
100dBEnhanced Gain Cascode Op Amp
Normal CascodeOp Amp
|p1(enh)| GBlog10ω
Gain (db)
|p1|
Lecture 240 Cascode Op Amps (3/28/10) Page 240-31
CMOS Analog Circuit Design © P.E. Allen - 2010
Frequency Response of the Enhanced Gain Cascode Op Amp – Continued• Does the pole in the feedback amplifier A have an influence?
Although the output resistance can be modeled as,
Rout’ RoutAo
1-s
p2Ao
1-s
p2
it has no influence on the frequency response because Cout has shorted out anyinfluence a change in Rout might have.
• Higher order poles come from a diversion of the current flow in the op amp to groundrather than the intended destination of the current to the output. These poles thatdivert the current are:
- Pole at the source of M6 (Agm6/C6) - Pole at the source of M7 (Agm7/C7)
- Pole at the drain of M8 (gm10/C8) - Pole at the source of M9 (Agm9/C6)
- Pole at the drain of M10 (gm8rds8gm10/C10)
Note that the enhancement amplifiers cause most of the higher-order poles to be movedout by |A|. However, each of the enhancement amplifiers introduce a pole at their outputwhich is approximately -1/[rds(Cgs+2Cdb+2Cgd)]. These poles become the dominantpoles that limit GB.
Lecture 240 Cascode Op Amps (3/28/10) Page 240-32
CMOS Analog Circuit Design © P.E. Allen - 2010
SUMMARY• Cascode op amps give additional flexibility to the two-stage op amp
- Increase the gain- Control the dominant and nondominant poles
• Enhanced gain, cascode amplifiers provide additional gain and are used when highgains are needed
• Folded cascode amplifier is an attractive alternate to the two-stage op amp- Wider ICMR- Self compensating- Good PSRR