Prof. YingLi TianMar. 29, 2018

Department of Electrical EngineeringThe City College of New York

The City University of New York (CUNY)

Lecture 13: Encoders, Multiplexers, Three-State Gates, and Gate Arrays

1

EE210: Switching Systems

Decoders

2

EN1: active highEN2’: active lowEN3’: active lowOutputs: active low

EN’: active lowOutputs: active high

Implement Logic Functions using Decoders

Example 5.3 (p263 - 264): Implement the following functions using decoders with OR or NAND gates.f (a, b, c) = ∑m(0, 2, 3, 7)g(a, b, c) = ∑m(1, 4, 6, 7)

3

Binary Encoders An encoder is the inverse of a binary

decoder. A binary encoder is a multi-input combinational logic circuit that converts the logic level "1" data at its inputs into an equivalent binary code at its output. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line configurations.

4

A 4-to-2 Binary Encoder

5Figure is from http://www.electronics tutorials.ws/combination/comb_4.html

Priority Encoders If more than one input can be 1 at the same

time, priority must be established: Descending: Highest priority given to the

largest input number. Ascending: Highest priority given to the

smallest input number.

6

Example of a Priority Encoder

Highest priority given to the largest input number (Descending). NR indicates that there are no requests.

Multiplexers (muxes) A multiplexer (mux) is a device that selects one of several

analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has nselect lines, which are used to select which input line to send to the output.

8

A 2-to-1 MultiplexerSelect line

S = 0, out = w;S = 1, out = x.

A 4-to-1 Multiplexer

9

Select lines

(S1, S0) = 00, out = w;(S1, S0) = 01, out = x;(S1, S0) = 10, out = y;(S1, S0) = 11, out = z.

Implement Logic Functions using Multiplexer

10

f (a, b, c) = ∑m(0, 1, 2, 5)

Implement f with:1. an 8-way mux.2. a 4-way mux.

Demultiplexers A demultiplexer is a device that selects one of several

analog or digital output signals from a single input line.

11http://en.wikipedia.org/wiki/Multiplexer

A 1-to-2 DeMultiplexer

A 4-way Demultiplexer

12

in: input signal a, b are the selectsab = 00, out0 = in. ab = 01, out1 = in. ab = 10, out2 = in. ab = 11, out3 = in.

Three-State Gates Input variables:

1 0 X (don’t care,

can be 0 or 1)

Outputs 1 0 Z (not

connected) 3rd

state.13

EN: Enable input. EN = 1 (active), gate as usual. EN = 0 (inactive), gate as an open-circuit (not connected – the 3rd

state).

Three-State Gates The 3rd state “Z” is the state of an output

terminal which is not currently driven by the circuit. It means that the signal is neither driven to a logical high nor low level - hence "tri-stated". Such a signal can be seen as an open circuit because connecting it to a low impedance circuit will not affect that circuit; it will instead itself be pulled to the same voltage as the actively driven output.

14

A 2-way Multiplxer using 3-state gates

15

EN: Enable input. EN = 0, f = a. EN = 1, f = b.

Gate Arrays-- Programmable Logic Device (PLD) Gate arrays are an approach to the design

and manufacture of application-specific integrated circuits by using standard NAND or NOR logic gates, and other active devices. ROMs – Read-Only Memories PLAs – Programmable Logic Arrays PALs –Programmable Array Logic

16

A Gate Array

17

A gate array with 3 inputs and 3 outputs.

Dash lines indicate possible connections.

One big company for Field-programmable gate array (FPGA) is “xilink”, http://www.xilinx.com/

More info about FPGA can be found at:http://en.wikipedia.org/wiki/Field-programmable_gate_array

18

Implementation of the following functions:

f = a’b’ + abcg = a’b’c’ + ab + bch = a’b’ + c

Solid lines indicate the actual connections.

Simple Representation

19

Use dots or Xs show the actual connections. Implementation of the following functions:

f = a’b’ + abcg = a’b’c’ + ab + bch = a’b’ + c

Three Common Types of Logic Arrays ROMs – Read-Only Memories: user can

specify the connections of only the OR gates.

PLAs (Programmable Logic Arrays): user can specify the connections of both AND and OR gates.

PALs –Programmable Array Logic: user can specify the connections of the AND gates.

20

Designing with ROMs

21

W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15)

X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15)

Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15)

For ROMs – user can specify the connections of only the OR gates.

Xs show the connections built into the ROM, dots show the implementation.

Designing with PLAs -- 1

22

W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15)

X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15)

Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15)

For PLAs – user can specify the connections of both the AND and OR gates.

Step1: Draw K-maps

Step2: Find SOPs (need to find the shared terms)

Step3: Implementation

Designing with PLAs -- 2

23

W(A, B, C, D) = ∑m(3, 7, 8, 9, 11, 15) = AB´C´ + CD

X(A, B, C, D) = ∑m(3, 4, 5, 7, 10, 14, 15) = A´BC´ + ACD´ + A´CD + {BCD or ABC)

Y(A, B, C, D) = ∑m(1, 5, 7, 11, 15) = A´C´D + ACD + {A´BD or BCD}

Designing with PLAs -- 3

24

Solution 2: W = AB´C´ + A´CD + ACD

X = A´BC´ + ACD´ + A´CD + BCD

Y = A´C´D + ACD + BCD

Designing with PLAs -- 4

25

Solution 2: W = AB´C´ + A´CD + ACD

X = A´BC´ + ACD´ + A´CD + BCD

Y = A´C´D + ACD + BCD

Solution 1: W = AB´C´ + CD

X = A´BC´ + ACD´ + A´CD + {BCD or ABC)

Y = A´C´D + ACD + {A´BD or BCD}

Solution 1 Solution 2

Designing with PALs

26

For PAL (Programmable Array Logic): user can specify the connections of the AND gates.

A PAL with 6 inputs and 4 outputs.

Designing with PALs

27

W = AB´C´ + CD

X = A´BC´ + ACD´ + A´CD + {BCD or ABC)

Y = A´C´D + ACD + {A´BD or BCD}

Announcement Read Chapter 5.3, 5.4, 5.5, 5.6 HW5 is out today, due 4/10/2018! Next class:

Sequential System Design State Tables, Diagrams

28