multiplexers decoders encoders code converters arithmetic comparison circuits

1. Multiplexers

2. Decoders

3. Encoders

4. Code converters

5. Arithmetic comparison circuits

6. VHDL for combinational circuits

Figure 6.1 A 2-to-1 multiplexer

(a) Graphical symbol

f

s

w0

w1

0

1

(b) Truth table

01

f

fs

w0

w1

(c) Sum-of-products circuit

s

w0

w1

(d) Circuit with transmission gates

w 0

w 1 f

s

1. Multiplexers


f

s 1

w 0 w 1

00

01

(b) Truth table

w 0 w 1

s 0

w 2 w 3

10

11

0 0 1 1

1 0 1

f s 1

0

s 0

w 2 w 3

f

(c) Circuit

s 1

w 0

w 1

s 0

w 2

w 3

(a) Graphic symbol

Figure 6.3 Using 2-to-1 multiplexers to build a 4-to-1 multiplexer

0

w 0

w 1

0

1

w 2

w 3

0

1

f 0

1

s 1

s


w 8

w 11

s 1

w 0

s 0

w 3

w 4

w 7

w 12

w 15

s 3

s 2

f

Figure 6.5 A practical application of multiplexers

x 1 0

1

x 2 0

1

s

y 1

y 2

x 1

x 2

y 1

y 2

(a) A 2x2 crossbar switch

(b) Implementation using multiplexers

s

Figure 6.6 Implementing programmable switchesin an FPGA

i 1

i 2

f

(a) Part of the FPGA in Figure 3.39

Storage cell

0/1

0/1

i 1

i 2

f

(b) Implementation using pass transistors

i 1

i 2

f

(c) Implementation using multiplexers

0/1 0/1 0/1

0/1 0/1 0/1

0/1 0/1

0/1 0/1

Figure 6.7 Synthesis of a logic function using multiplexers

(a) Implementation using a 4-to-1 multiplexer

f

w 1

0 1

0

1

w 2

1 0

0

0

1

1

1

0

1

f w 1

0

w 2

1

0

(b) Modified truth table

0

1

0

0

1

1

1

0

1

f w 1

0

w 2

1

0

f w 2

w 1

0

1

f w 1

w 2

w 2

(c) Circuit

Synthesis of a logic function using multiplexers

Figure 6.8 Three-input majority function

w3

w3

f

w1

0

w2

1

(a) Modified truth table

(b) Circuit

00011

101

fw1

0

w2

1

0 00 11 01 1

0001

0 00 11 01 1

0111

w1 w2 w3 f

00001111

w3

Figure 6.9 Three-input XOR function

(a) Truth table

0 00 11 01 1

0110

0 00 11 01 1

1001

w1 w2 w3 f

00001111

w2 w3

w2 w3

f

w3

w1

(b) Circuit

w2

Figure 6.10 Three-input XOR function

f

w 1

w 2

(a) Truth table (b) Circuit

0 0

0 1

1 0

1 1

0

1

1

0

0 0

0 1

1 0

1 1

1

0

0

1

w 1 w 2 w 3 f

0

0

0

0

1

1

1

1

w 3

w 3

w 3

w 3

w 3

Figure 6.11 Three-input majority function using a 2-to-1 MUX

0 0

0 1

1 0

1 1

0

0

0

1

0 0

0 1

1 0

1 1

0

1

1

1

w 1 w 2 w 3 f

0

0

0

0

1

1

1

1

(b) Circuit

0 1

f w 1

w 2 w 3

w 2 w 3 +

f

w 3

w 1 w 2

(b) Truth table

Boole’s (Shannon’s) Expansion

f(w1,w2,...,wn)

= w1 f(0,w2,...,wn) + w1 f(1,w2,...,wn)

= w1fw1 + w1fw1

= w1 w2 f(0,0,w3,...,wn) +

w1 w2 f(0,1,w3,...,wn) +

w1 w2 f(1,0,w3,...,wn) +

w1 w2 f(1,1,w3,...,wn)

f = w1w2 + w1w3 + w2w3

F=W1’(W2W3)+W1(W2+W3)

Shannon’s

F=w2’(w1w3)+w2(w1+w3)

f = w1’w3 + w2w3’

F=W1’(W3+W2W3’)+W1(W2W3’)

F=W1’(W3+W2)+W1(W2W3’)

Decomposition using w1 gives



Figure 6.12 Example circuits

(a) Using a 2-to-1 multiplexer

f

w 2

w 1

w 3

f

w 1

w 2

w 3

(b) Using a 4-to-1 multiplexer

1

f = w1’w3‘+ w1w2 +w1w3

F=w1’(w3’)+w1(w2+w3)

F=w1’w2’(w3’)+w1’w2(w3’) +w1w2’(w3)+w1w2(1)

Figure 6.13 Example circuit

w 2

0 w 3

1

f

w 1

f = w1w2 + w1w3 + w2w3

g=w2’(0)+w2(w3)h=w2’(w3)+w2(1)

f = w2’w3+w1’w2w3’+ w2w3’w4+w1w2’w4’

F=w1’fw1’+w1fw1 =w1’(w2’w3+w2w3’+w2w3’w4) +w1(w2’w3+w2w3’w4+w2’w4’)F=w2’fw2’+w2fw2 =w2’(w3+w1w4’)+w2(w1’w3’+w3’w4)

Figure 6.14 Example circuits

w 2 w 3

f

w 4

w 1

f w 1

(a) Using three 3-LUTs

(b) Using two 3-LUTs

f w 1

w 1 w 3

f

w 4

0 f w 2

w 2

0

Figure 6.15 An n-to-2n decoder

0

w n 1 –

n inputs

EnEnable

2 n

outputs

y 0

y 2 n 1 –

w

2. DECODERS

Figure 6.16 A 2-to-4 decoder

0 0 1 1

1 0 1

y 0 w 1

0

w 0

(c) Logic circuit

w 1

w 0

x x

1 1

0

1 1

En

0 0 0

1

0

y 1

1 0 0

0

0

y 2

0 1 0

0

0

y 3

0 0 1

0

0

y 0

y 1

y 2

y 3

En

w 0

En

y 0 w 1 y 1

y 2 y 3

(a) Truth table (b) Graphic symbol

Figure 6.17 A 3-to-8 decoder using two 2-to-4 decoder

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

En

Figure 6.18 A 4-to-16 decoder built using a decoder tree

w 0

En

y 0 w 1 y 1

y 2 y 3

y 8 y 9 y 10y 11

w 2

w 0 y 0 y 1 y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

w 0

En

y 0 w 1 y 1

y 2 y 3

y 12y 13y 14y 15

w 0

En

y 0 w 1 y 1

y 2 y 3

w 3

En

Figure 6.19 A 4-to-1 multiplexer built using a decoder

w 1

w 0

w 0

En

y 0 w 1 y 1

y 2 y 3

w 2

w 3

f

s 0 s 1

1

Figure 6.20 A 4-to-1 multiplexer built using a decoder and tri-state buffers

w1

w0

w0

En

y0

w1 y1

y2

y3

f

s0s1

1 w2

w3

Demultiplexers• A demultiplexer is a circuit which places

the value of a single data input onto multiple data outputs is a demultiplexer.

w 1

w 0

y 0

y 1

y 2

y 3

En

Figure 6.21 A 2m x n read-only memory (ROM) block

Sel 2

Sel 1

Sel 0

Sel 2 m 1 –

Address

Read

d 0 d n 1 – d n 2 –

m -to-2

m deco

der

0/1 0/1 0/1

0/1 0/1 0/1

0/1 0/1 0/1

0/1 0/1 0/1

Data

a 0

a 1

a m 1 –

Figure 6.22 A 2n-to-n binary encoder

2 n

inputs

w 0

w 2 n 1 –

y 0

y n 1 –

n outputs

3.ENCODERS

Figure 6.23 A 4-to-2 binary encoder

0 0 1 1

1 0 1

w 3 y 1

0

y 0

(b) Circuit

w 1

w 0

0 0 1

0

w 2

0 1 0

0

w 1

1 0 0

0

w 0

0 0 0

1

y 0

w 2

w 3 y 1

(a) Truth table

BINARY ENCODER

Figure 6.24. Truth table for a 4-to-2 priority encoder.

d001

010

w0 y1

d

y0

1 1

01

1

11

z

1xx

0

x

w1

01x

0

x

w2

001

0

x

w3

000

0

1

PRIORITY ENCODER

Figure 6.25. A BCD-to-7-segment display code converter.

c e

1 0 1 1

1 1 1

w 0 a

1

b

0 1

1 1

1

0 1

1 0 1

0

0

w 1

0 1 1

0

0

w 2

0 0 0

0

1

w 3

0 0 0

0

0

c

1 0 1 0

0 1 1 0

1 1 1 0

0 0 0 1

1 0 0 1

1 1 1 1

0 1 1

0

1 1

1 1

1

1 1

0 1 1

1

d

0

1 0

0

1 0

e

1 0 1

1

1

0 1

0

0 1

0 0 0

1

f

1

0 0

1

1 1

g

1 0 1

1

1

1 1

1

0 1

(c) Truth table

(a) Code converter

w 0

a

w 1

b c d w 2

w 3 e f g

a

g

b f

d

(b) 7-segment display

4 CODE CONVERTERS

Figure 6.26. A four-bit comparator circuit.

i 0

i 1

i 2

i 3

b 0

a 0

b 1

a 1

b 2

a 2

b 3

a 3

AeqB

AgtB

AltB

5 ARITHMETIC COMPARISIONS

):( 333

0123

bai

iiiiBAAeqB

예

001231123

22333

baiiibaii

baibaAgtB

AgtBAeqBAltB

Libraries

• Library ieee;

• Use ieee.std_logic_1164.all;

• Use ieee.std_logic_arith.all;

• Use ieee.std_logic_signed.all;

• Use ieee.std_logic_unsigned.all;

Data Types

• bit values: '0', '1' • boolean values: TRUE, FALSE • integer values: -(231) to +(231 - 1)

• std_logic values: 'U','X','1','0','Z','W','H','L','-' U' = uninitialized'X' = unknown'W' = weak 'X‘'Z' = floating'H'/'L' = weak '1'/'0‘'-' = don't care

• Std_logic_vector (n downto 0);• Std_logic_vector (0 upto n);

Entity• Define inputs and outputs• Example:

Entity test is

Port( A,B,C,D: in std_logic;

E: out std_logic);

End test;

Inputs and Outputs

Chip

A

B

C

D

E

Architecture• Define functionality of

the chip

• X <= A AND B;• Y <= C AND D;• E <= X OR Y;

ChipA

B

C

D

EX

Y

VHDL features

• Case insensitive– inputa, INPUTA and InputA are refer to same variable

• Comments– ‘--’ until end of line– If you want to comment multiple lines, ‘--’ need to be put at

the beginning of every single line• Statements are terminated by ‘;’• Signal assignment:

– ‘<=’• User defined names:

– letters, numbers, underscores (‘_’)– start with a letter

VHDL structure

• Library– Definitions, constants

• Entity– Interface

• Architecture– Implementation, function

VHDL - Library

• Include library

library IEEE;– Define the library package used

use IEEE.STD_LOGIC_1164.all;– Define the library file used– For example, STD_LOGIC_1164 defines ‘1’

as logic high and ‘0’ as logic low• output <= ‘1’; --Assign logic high to output

Reserved VHDL keywords

VARIABLE

WAITWHENWHILEWITH

XNORXOR

RETURN

SELECTSEVERITYSIGNALSHAREDSLASLLSRASRLSUBTYPE

THENTOTRANSPORTTYPE

UNAFFECTEDUNITSUNTILUSE

OFONOPENOROTHERSOUT

PACKAGEPORTPOSTPONEDPROCEDUREPROCESSPURE

RANGERECORDREGISTERREMREPORTROLROR

ININERTIALINOUTIS

LABELLIBRARYLINKAGELITERALLOOP

MAPMOD NANDNEWNEXTNORNOTNULL

DISCONNECTDOWNTO

ELSEELSIFENDENTITYEXIT

FILEFORFUNCTION

GENERATEGENERICGROUPGUARDED

IFIMPURE

ABSACCESSAFTERALIASALLANDARCHITECTUREARRAYASSERTATTRIBUTE

BEGINBLOCKBODYBUFFERBUS

CASECOMPONENTCONFIGURATION CONSTANT

Entity Declaration• Entity Declaration describes the interface of the component, i.e. input and output ports.

ENTITY nand_gate ISPORT( a : IN STD_LOGIC;

b : IN STD_LOGIC; z : OUT STD_LOGIC

);END nand_gate;

Reserved words

Entity name Port names Port typeSemicolon

No Semicolon

Port modes (data flow directions)

Entity declaration – simplified syntax

ENTITY entity_name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

………….

port_name : signal_mode signal_type);

END entity_name;

Architecture

• Describes an implementation of a design entity.

• Architecture example:

ARCHITECTURE model OF nand_gate ISBEGIN

z <= a NAND b;END model;

Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]

BEGIN

code

END architecture_name;

Entity Declaration & Architecture

LIBRARY ieee;USE ieee.std_logic_1164.all;


b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;



nand_gate.vhd

Port ModesThe Port Mode of the interface describes the direction in which data travels with respect to the component

– In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.

– Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.

– Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

– Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

Library declarations

Use all definitions from the package

std_logic_1164LIBRARY ieee;USE ieee.std_logic_1164.all;


b : IN STD_LOGIC; z : OUT STD_LOGIC);

END nand_gate;



Library declaration

Library declarations - syntax

LIBRARY library_name;

USE library_name.package_name.package_parts;

Fundamental parts of a libraryLIBRARY

PACKAGE 1 PACKAGE 2

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS

TYPES

CONSTANTS

FUNCTIONS

PROCEDURES

COMPONENTS

Libraries• ieee

• std

• work

Need to be explicitly

declared

Visible by default

Specifies multi-level logic system,

including STD_LOGIC, and

STD_LOGIC_VECTOR data types

Specifies pre-defined data types

(BIT, BOOLEAN, INTEGER, REAL,

SIGNED, UNSIGNED, etc.), arithmetic

operations, basic type conversion

functions, basic text i/o functions, etc.

Current designs after compilation

Operations on Unsigned Numbers

For operations on unsigned numbers

USE ieee.std_logic_unsigned.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTOR

OR

USE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeUNSIGNED

Operations on Signed Numbers

For operations on signed numbers

USE ieee.std_logic_signed.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTOR

OR

USE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeSIGNED

Signed and Unsigned Types

Behave exactly like

STD_LOGIC_VECTOR

plus, they determine whether a given vector

should be treated as a signed or unsigned number.

Require

USE ieee.std_logic_arith.all;

Integer Types

Operations on signals (variables)

of the integer types:

INTEGER, NATURAL,

and their sybtypes, such as

TYPE day_of_month IS RANGE 0 TO 31;

are synthesizable in the range

-(231-1) .. 231 -1 for INTEGERs and their subtypes

0 .. 231 -1 for NATURALs and their subtypes

Integer TypesOperations on signals (variables)

of the integer types:

INTEGER, NATURAL,

are less flexible and more difficult to control

than operations on signals (variables) of the type

STD_LOGIC_VECTOR

UNSIGNED

SIGNED, and thus

are recommened to be avoided by beginners.

6.1 Assignment statements

selected signal assignment

conditional signal assignment

generate statements

if-then-else statements

case statements

6.VHDL FOR COMBINATIONAL CIRCUITS

Figure 6.27 VHDL code for a 2-to-1 multiplexer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 ISBEGIN

WITH s SELECTf <= w0 WHEN '0',

w1 WHEN OTHERS ;END Behavior ;

SELECTED SIGNAL ASSIGNMENT


ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;


WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;

END Behavior ;

Figure 6.28 VHDL code for a 4-to-1 multiplexer

Figure 6.28 Component declaration for the 4-to-1 multiplexer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;PACKAGE mux4to1_package IS

COMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;


END COMPONENT ;END mux4to1_package ;

Figure 6.29 Hierarchical code for a 16-to-1 multiplexer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY work ;USE work.mux4to1_package.all ;

ENTITY mux16to1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;


END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 ISSIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGINMux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;Mux5: mux4to1 PORT MAP

( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;END Structure ;

Figure 6.30 VHDL code for a 2-to-4 binary decoder


ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS ;

END Behavior ;

Figure 6.31 A 2-to-1 multiplexer using a conditional signal assignment





f <= w0 WHEN s = '0' ELSE w1 ;END Behavior ;

CONDITIONAL SIGNAL ASSIGNMENT

Figure 6.32 VHDL code for a priority encoder


ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE Behavior OF priority ISBEGIN

y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;END Behavior ;

Figure 6.33 Less efficient code for a priority encoder




END priority ;


WITH w SELECTy <= "00" WHEN "0001",

"01" WHEN "0010","01" WHEN "0011","10" WHEN "0100","10" WHEN "0101","10" WHEN "0110","10" WHEN "0111","11" WHEN OTHERS ;

WITH w SELECTz <= '0' WHEN "0000",

'1' WHEN OTHERS ;END Behavior ;

Figure 6.34 VHDL code for a four-bit comparator

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY compare ISPORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE Behavior OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END Behavior ;

Figure 6.35 A four-bit comparator using signed numbers

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;

ENTITY compare ISPORT ( A, B : IN SIGNED(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE Behavior OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END Behavior ;

Figure 6.36 Code for a 16-to-1 multiplexer using a generate statement

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.mux4to1_package.all ;

ENTITY mux16to1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;


END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 ISSIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;

GENERATE STATEMENTS

Figure 6.37 Hierarchical code for a 4-to-16 binary decoder


ENTITY dec4to16 ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;

END dec4to16 ;

ARCHITECTURE Structure OF dec4to16 ISCOMPONENT dec2to4

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );G2: IF i=3 GENERATE

Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ;END GENERATE ;

END GENERATE ;END Structure ;

Concurrent vs. Sequential

• All previous statements are called concurrent assignment statements because order does not matter.

• When order matters, the statements are called sequential assignment statements.

• All sequential assignment statements are placed within a process statement.

Process Statement

• Begins with PROCESS keyword followed by a sensitivity list.

• For a combinational circuit, sensitivity list includes all input signals used in the process.

• Process executed whenever there is a change on a signal in the sensitivity list.

• Statements executed in sequential order.• No assignments are visible until all statements in the

process have been executed.• If multiple assignments, only last has an effect.

Figure 6.38 A 2-to-1 multiplexer specified using an if-then-else statement





PROCESS ( w0, w1, s )BEGIN

IF s = '0' THENf <= w0 ;

ELSEf <= w1 ;

END IF ;END PROCESS ;

END Behavior ;

Figure 6.39 Alternative code for a 2-to-1 multiplexer






f <= w0 ;IF s = '1' THEN

f <= w1 ;END IF ;

END PROCESS ;END Behavior ;

Figure 6.40 A priority encoder specified using if-then-else

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY priority IS

PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;


PROCESS ( w )BEGIN

IF w(3) = '1' THENy <= "11" ;

ELSIF w(2) = '1' THEN y <= "10" ;

ELSIF w(1) = '1' THENy <= "01" ;

ELSEy <= "00" ;

END IF ;END PROCESS ;z <= '0' WHEN w = "0000" ELSE '1' ;

END Behavior ;

Figure 6.41 Alternative code for the priority encoder




END priority ;


PROCESS ( w )BEGIN

y <= "00" ;IF w(1) = '1' THEN y <= "01" ; END IF ;IF w(2) = '1' THEN y <= "10" ; END IF ;IF w(3) = '1' THEN y <= "11" ; END IF ;

z <= '1' ;IF w = "0000" THEN z <= '0' ; END IF ;


Figure 6.42 Code for a one-bit equality comparator


ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END compare1 ;

ARCHITECTURE Behavior OF compare1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

AeqB <= '1' ;END IF ;


Figure 6.43 An example of code that results in implied memory


ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;


END Behavior ;

Figure 6.44 Circuit generated due to implied memory

A

B AeqB

…PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;


…

Figure 6.45 A CASE statement that represents a 2-to-1 multiplexer






CASE s ISWHEN '0' =>

f <= w0 ;WHEN OTHERS =>

f <= w1 ;END CASE ;


CASE STATEMENTS

Figure 6.46 A 2-to-4 binary decoder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISBEGIN

PROCESS ( w, En )BEGIN

IF En = '1' THENCASE w IS

WHEN "00" => y <= "1000" ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;

END CASE ;ELSE

y <= "0000" ;END IF ;


Figure 6.47 A BCD-to-7-segment decoder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 IS

PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGIN

PROCESS ( bcd )BEGIN

CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;

END CASE ;END PROCESS ;

END Behavior ;

Table 6.1 The functionality of the 74381 ALU

Figure 6.48 Code that represents the functionality of the 74381 ALU

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY alu IS

PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END alu ;

ARCHITECTURE Behavior OF alu ISBEGIN

PROCESS ( s, A, B )BEGIN

CASE s ISWHEN "000" => F <= "0000" ;WHEN "001" => F <= B - A ;WHEN "010" => F <= A - B ;WHEN "011" => F <= A + B ;WHEN "100" => F <= A XOR B ;WHEN "101" => F <= A OR B ;WHEN "110" => F <= A AND B ;WHEN OTHERS =>

F <= "1111" ;END CASE ;


Figure 6.49 Timing simulation for the 74381 ALU code

multiplexers decoders encoders code converters arithmetic comparison circuits

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