lecture 12 8086/8088 hardware specifications and memory interface presented by dr. shazzad hosain...

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Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

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Page 1: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

Lecture 128086/8088 Hardware Specifications

and Memory Interface

Presented ByDr. Shazzad Hosain

Asst. Prof. EECS, NSU

Page 2: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

8086 Microprocessor 8088 Microprocessor8.1: Barry B. Brey

Page 3: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

Chapter 9: Memory Interface

• 1K Memory has A0 – A9

• 4K Memory has A0 – A11

Address Pins

• O0 – O7 for 8 bit computer

• O0 – O15 for 16 bit computer

Output/Data Pins

Page 4: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

Address Decoding

• Why need address decoding?– 8086/8088 has 20 address pins– But EPROM, the memory device has less space– For example, 2716 EPROM is a 2K memory device

Page 5: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

NAND Gate Decoder• Decode memory address locations FF800H – FFFFFH

1111 1111 1000 0000 0000 = FF800H1111 1111 1111 1111 1111 = FFFFFH

Figure: 9-12

Page 6: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

• Develop a NAND gate decoder so that it decodes the memory range DF800H – DFFFFH

More Example

Page 7: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

The 3-to-8 Line Decoder (74LS138)

Page 8: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

• Develop a 64K memory bank using eight 2764 EPROMs, where each 2764 EPROM is a 8K memory device and it address the memory locations F0000H – FFFFFH

1111 0000 0000 0000 0000 = F0000H1111 0001 1111 1111 1111 = F1FFFH

1111 0010 0000 0000 0000 = F2000H1111 0011 1111 1111 1111 = F3FFFH1111 0100 0000 0000 0000 = F4000H1111 0101 1111 1111 1111 = F5FFFH

1111 0110 0000 0000 0000 = F6000H1111 0111 1111 1111 1111 = F7FFFH1111 1000 0000 0000 0000 = F8000H1111 1001 1111 1111 1111 = F9FFFH

1111 1110 0000 0000 0000 = FE000H1111 1111 1111 1111 1111 = FFFFFH

**

Page 9: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

1111 0000 0000 0000 0000 = F0000H1111 0001 1111 1111 1111 = F1FFFH

1111 0010 0000 0000 0000 = F2000H1111 0011 1111 1111 1111 = F3FFFH1111 0100 0000 0000 0000 = F4000H1111 0101 1111 1111 1111 = F5FFFH

1111 0110 0000 0000 0000 = F6000H1111 0111 1111 1111 1111 = F7FFFH1111 1000 0000 0000 0000 = F8000H1111 1001 1111 1111 1111 = F9FFFH

1111 1110 0000 0000 0000 = FE000H1111 1111 1111 1111 1111 = FFFFFH

**

Page 10: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

A13

A14

A15

A16

A17A18A19

Page 11: Lecture 12 8086/8088 Hardware Specifications and Memory Interface Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

References

• Chapter 8, 9 The Intel Microprocessors – by Barry B. Brey