lecture 10: sequential circuits - u of s engineering · pdf file ·...

I t d ti tIntroduction toCMOS VLSI

Design

Lecture 10: Sequential CircuitsSequential Circuits

David Harris

Harvey Mudd CollegeSpring 2004

OutlineOutlineSequencingSequencing Element DesignMax and Min-DelayClock SkewTime BorrowingTwo Phase ClockingTwo-Phase Clocking

CMOS VLSI Design10: Sequential Circuits Slide 2

SequencingSequencingCombinational logic– output depends on current inputs

Sequential logic– output depends on current and previous inputs– Requires separating previous, current, future

Called state or tokens– Called state or tokens– Ex: FSM, pipeline

clk clk clk clk

CLin out

CL CL


PipelineFinite State Machine

Sequencing Cont.Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cable

Li ht l (t k ) t d bl– Light pulses (tokens) are sent down cable– Next pulse sent before first reaches end of cable– No need for hardware to separate pulses– No need for hardware to separate pulses– But dispersion sets min time between pulses

This is called wave pipelining in circuitsp p gIn most circuits, dispersion is high– Delay fast tokens so they don’t catch slow ones.


Sequencing OverheadSequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensM k i it l th j t th l i d lMakes circuit slower than just the logic delay– Called sequencing overhead

Some people call this clocking overheadSome people call this clocking overhead– But it applies to asynchronous circuits too– Inevitable side effect of maintaining sequenceg q


Sequencing ElementsSequencing ElementsLatch: Level sensitive– a.k.a. transparent latch, D latch

Flip-flop: edge triggered– A.k.a. master-slave flip-flop, D flip-flop, D register

Timing DiagramsTransparent D

Flopatch Q

clk clk

D Q– Transparent– Opaque– Edge-trigger

FLa

clk

DEdge triggerQ (latch)

Q (flop)


Latch DesignLatch DesignPass Transistor LatchPros++ D Q

φ

+Cons–

D Q

–––––


Latch DesignLatch DesignPass Transistor LatchPros+ Tiny+ Low clock load D Q

φ

+ Low clock loadCons– Vt drop

D Q

Used in 1970’st

– nonrestoring– backdriving

output noise sensitivity– output noise sensitivity– dynamic– diffusion input


p

Latch DesignLatch DesignTransmission gate+- D Q

φ

φ


Latch DesignLatch DesignTransmission gate+ No Vt drop- Requires inverted clock D Q

φ

φ


Latch DesignLatch DesignInverting buffer φ

++

D

φ

φ

X Q

+ Fixes either••

φ

D Q

φ

•–

φ


Latch DesignLatch DesignInverting buffer φ

+ Restoring+ No backdriving

D

φ

φ

X Q

+ Fixes either• Output noise sensitivity• Or diffusion input

φ

D Q

φ

• Or diffusion input– Inverted output

φ


Latch DesignLatch DesignTristate feedback+–

φ

φ

QD X

φ φ

φφ


Latch DesignLatch DesignTristate feedback+ Static– Backdriving risk

φ

φ

QD X

Static latches are now essentialφ φ

φφ


Latch DesignLatch DesignBuffered input++

φ

QD X

φ

φ φ

φ

φ


Latch DesignLatch DesignBuffered input+ Fixes diffusion input+ Noninverting

φ

QD X

φ

φ φ

φ

φ


Latch DesignLatch DesignBuffered output Qφ

+φ

D X

φ

φ

φ

φ


Latch DesignLatch DesignBuffered output Qφ

+ No backdrivingφ

D X

φ

φ

Widely used in standard cells+ Very robust (most important)

φ

φ

+ Very robust (most important)- Rather large- Rather slow (1 5 – 2 FO4 delays)Rather slow (1.5 2 FO4 delays)- High clock loading


Latch DesignLatch DesignDatapath latch

φ Q+-

φ

φ φ

Q

D X

φ φ

φφ


Latch DesignLatch DesignDatapath latch

φ Q+ Smaller, faster- unbuffered input

φ

φ φ

Q

D X

φ φ

φφ


Flip-Flop DesignFlip Flop DesignFlip-flop is built as pair of back-to-back latches

D Q

φ φ

X

φ φ

Q

D

φ φ

X

Q

Qφ φ

φ φ

φ φ


EnableEnableEnable: ignore clock when en = 0– Mux: increase latch D-Q delay– Clock Gating: increase en setup time, skew

φ φ

φ en

Symbol Multiplexer Design Clock Gating Design

Latc

h

D Q

en

Latc

hDQ

0

1

en

Latc

h

D Q

φ en

D Q

φ DQ

φ

0

1

enD Q

φ en

Flop

Flop

Flop


en

ResetResetForce output low when reset assertedSynchronous vs. asynchronous

Sym

bol FlopD Q

Latc

h

D Q

φ φ

D

φ φ Q

Qφ φ

reset

φ

Qφ

Dreset

Synchronous Rl

reset reset

φ φφ

φ

φ

φ

φ

φ

φ

Q φ

Reset

Q

D

φ

φφ

φ

φ

Qφ

φ

Dreset

reset

φ

φ

reset

Asynchronous R

eset

φ

reset


φφ φ

Set / ResetSet / ResetSet forces output high when enabled

Flip-flop with asynchronous set and reset

D

φ φ

φ

Qset reset

φ φφφ

reset set

φφ

reset


Sequencing MethodsSequencing MethodsFlip-flops

F

Tc

2-Phase LatchesPulsed Latches

Flip-FlopsFl

op

Flop

clk

clk clk

Combinational Logic

φ1

φ2

2-Phase Transpar

Tc/2

tnonoverlap tnonoverlap

Latc

h

Latc

h

Latc

h

φ1 φ1φ2

ent LatchesP

ul

CombinationalLogic

CombinationalLogic

Half-Cycle 1 Half-Cycle 1

φp

φp φp

lsed Latches

Combinational Logic

Latc

h

Latc

h

tpw


Timing DiagramsTiming Diagrams

C t i ti dA tpd

CombinationalLogicA Y

t Logic Prop Delay

Contamination and Propagation Delays

p

Yog c

clk clk

tcd

tsetup thold

tpd Logic Prop. Delay

tcd Logic Cont. Delay

tpcq Latch/Flop Clk-Q Prop Delay

FlopD Q D

Q tccq

tpcqtccq Latch/Flop Clk-Q Cont. Delay

tpdq Latch D-Q Prop Delay

t Latch D Q Cont DelayLa

tch

D Q

clk clk

D

Q

tccq

tsetup tholdtpcq

tpdqtcdq

tpcq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time


Max-Delay: Flip-FlopsMax Delay: Flip Flopsclk clk( )t T≤

F1 F2Combinational Logic

Tc

Q1 D2( )sequencing overhead

pd ct T≤ −1442443

clk

Q1 tpd

tsetuptpcq

D2


Max-Delay: Flip-FlopsMax Delay: Flip Flopsclk clk( )t T t t≤ +

F1 F2Combinational Logic

Tc

Q1 D2( )setup

sequencing overhead

pd c pcqt T t t≤ − +14243

clk

Q1 tpd

tsetuptpcq

D2


Max Delay: 2-Phase LatchesMax Delay: 2 Phase Latchesφ1 φ1φ2

( )t t t T≤ Q1

L1

φ1

L2 L3

CombinationalLogic 1


Q2 Q3D1 D2 D3( )1 2

sequencing overhead

pd pd pd ct t t T= + ≤ −1442443

Tc

φ1

φ2

D1 t

Q1

D2

D1

tpd1

tpdq1

tpdq2

Q2

D3

tpd2

pdq2


Max Delay: 2-Phase LatchesMax Delay: 2 Phase Latchesφ1 φ1φ2

( )2t t t T t≤Q1

L1

φ1

L2 L3



Q2 Q3D1 D2 D3( )1 2

sequencing overhead

2pd pd pd c pdqt t t T t= + ≤ −123

Tc

φ1

φ2

D1 t

Q1

D2

D1

tpd1

tpdq1

tpdq2

Q2

D3

tpd2

pdq2


Max Delay: Pulsed LatchesMax Delay: Pulsed Latchesφp φp( )maxt T≤

Tc

Q1 Q2D1 D2

D1

p p

Combinational LogicL1 L2

t d

( )sequencing overhead

max pd ct T≤ −14444244443

Q1

D2

D1

(a) tpw > tsetup tpd

tpdq

φp

tpw

Q1

D2

(b) tpw < tsetup

Tctpcq

tpd tsetup

D2


Min-Delay: Flip-FlopsMin Delay: Flip Flopsclk

cdt ≥ CLF1

Q1

clk

clk

F2

D2

clk

Q1

D2

tcd

thold

tccq

hold


Min-Delay: Flip-FlopsMin Delay: Flip Flopsclk

holdcd ccqt t t≥ − CLF1

Q1

clk

clk

F2

D2

clk

Q1

D2

tcd

thold

tccq

hold


Min-Delay: 2-Phase LatchesMin Delay: 2 Phase Latches

φ1

1, 2 cd cdt t ≥CL

Q1

φ1

L1

φ2Hold time reduced byD2

L2

φ1

tnonoverlap

Hold time reduced by nonoverlap

Paradox: hold applies

Q1

D2

φ2

tcd

t

tccq

Paradox: hold applies twice each cycle, vs. only once for flops.

D2 thold

But a flop is made of two latches!


Min-Delay: 2-Phase LatchesMin Delay: 2 Phase Latches

φ1

1, 2 hold nonoverlapcd cd ccqt t t t t≥ − −CL

Q1

φ1

L1

φ2Hold time reduced byD2

L2

φ1

tnonoverlap

Hold time reduced by nonoverlap

Paradox: hold applies

Q1

D2

φ2

tcd

t

tccq

Paradox: hold applies twice each cycle, vs. only once for flops.

D2 thold

But a flop is made of two latches!


Time BorrowingTime BorrowingIn a flop-based system:– Data launches on one rising edge– Must setup before next rising edge– If it arrives late, system fails– If it arrives early, time is wasted

Flops have hard edges– Flops have hard edgesIn a latch-based system– Data can pass through latch while transparentData can pass through latch while transparent– Long cycle of logic can borrow time into next– As long as each loop completes in one cycle


g p p y

Time Borrowing ExampleTime Borrowing Exampleφ1φ1

φ2

φ1 φ1φ2

Latc

h

Latc

h

Latc

h

Combinational Logic CombinationalLogic(a)

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

h h

φ1 φ2

(b) Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle


Loops may borrow time internally but must complete within the cycle

How Much Borrowing?How Much Borrowing?φ1 φ22-Phase Latches

Q1

L1

φ1

L2Combinational Logic 1Q2D1 D2

( )borrow setup nonoverlap2cTt t t≤ − +

φ1

φ2Tc

Tc/2 tborrow

tnonoverlap

tsetup

D2

c Nominal Half-Cycle 1 Delay

borrow


Clock SkewClock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival time– Decreases maximum propagation delay– Increases minimum contamination delay– Decreases time borrowing


Skew: Flip-FlopsSkew: Flip Flops

F1 F2

clk clk

Combinational LogicQ1 D2

( )T≤ F F

clk

Combinational Logic

Tc

Q1

tskew

t

tpcq

t

( )setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

≤ − + +

≥ − +

144424443

Q1

D2

CL1

clk

Q1

tsetuptpdqhold skewcd ccq

CLF1

F2

clk

D2

Q1

D2

clk

tskew

t

thold

tccq


D2 tcd

Skew: LatchesSkew: Latchesφ1 φ1φ22-Phase Latches

Q1

L1

φ1

φ

L2 L3



Q2 Q3D1 D2 D3

( )sequencing overhead

2pd c pdqt T t≤ −123

φ2

( )

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

,

2

cd cd ccq

c

t t t t t t

Tt t t t

≥ − − +

≤ − + +2


Two-Phase ClockingTwo Phase ClockingIf setup times are violated, reduce clock speedIf hold times are violated, chip fails at any speedIn this class, working chips are most important– No tools to analyze clock skew

An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesphase latches with big nonoverlap timesCall these clocks φ1, φ2 (ph1, ph2)


Safe Flip-FlopSafe Flip FlopIn class, use flip-flop with nonoverlapping clocks– Very slow – nonoverlap adds to setup time– But no hold times

In industry, use a better timing analyzer– Add buffers to slow signals if hold time is at risk

Q

D

φ2

X

Q

Qφ2

φ1

φ1

φ1

2 1φ1

φ2

φ2


12

SummarySummaryFlip-Flops:– Very easy to use, supported by all tools

2-Phase Transparent Latches:– Lots of skew tolerance and time borrowing

Pulsed Latches:Fast some skew tol & borrow hold time risk– Fast, some skew tol & borrow, hold time risk


lecture 10: sequential circuits - u of s engineering · pdf file ·...

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