lecture 1 - intro,transistor

8/14/2019 Lecture 1 - Intro,Transistor

1/70

VLSI

VLSI - ' 1

Introduction, Design MetricsCMOS Transistor

based on course & book byJan M. RabaeyAnantha Chandrakasan

Borivoje Nikolicand foils from

Mary Jane Irwin


2/70

VLSI

:

:

:

:

:


3/70


4/70

VLSI

Transistor Revolution

q

q

q

q

q

q


5/70

VLSI

The Transistor Revolution

First transistorBell Labs,


6/70

VLSI

The First Integrated Circuits

Bipolarlo ic

ECL 3-input GateMotorola 1966


7/70VLSI

MOSFET Technology

q

q

q

q

q

q


8/70VLSI

Moores Law

qqq

qq

q


9/70VLSI

Moores Law in Microprocessors

40048008

80808085 8086

286386

486Pentium

P

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010

Year

Transistors

2X growth in 1.96

Transistors on lead microprocessors double every 2 years


10/70VLSI

Intel 4004 MicroprocessorIntel 4004 Microprocessor


11/70VLSI

Intel Pentium (IV) Microprocessor


12/70VLSI

State-of-the Art: Lead MicroprocessorsState-of-the Art: Lead Microprocessors


13/70VLSI

Evolution in DRAM Chip Capacity

humanmemory

2 hrs CD audio30 sec HDTV

b

p

4X growth every 3 years!


14/70VLSI

Die Size Growth

4004

8008

80808085

8086286

386486 Pentium

P6

1

10

100

1970 1980 1990 2000 2010

Year

Diesize

~7% growth per year

~2X growth in 10


15/70VLSI

Clock Frequency

Lead microprocessors frequency doubles every 2 years

P6

Pentium 486

3862868086

8085

8080

80084004

0.

1

10

100

1000

10000

1970 1980 1990 2000 2010

Year

Frequency

Power-limitedfrequency increase

2X every 2 years


16/70VLSI

Power will be a major problem

5KW18KW

1.5KW

500W

40048008

80808085

8086286386486

Pentium

0.

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er

Power delivery and dissipation will be


17/70VLSI

Power density

40048008

80808085

8086

286386

486Pentium

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

PowerDe

nsity

Hot Plate

Nuclea

Reactor

RocketNozzl

Power density too high to keep junctions at low


18/70


19/70

VLSI

Technology Directions: SIA Roadmap


20/70

VLSI

Why Design Methods?

q

q

qqq

qq


21/70

VLSI

Design Abstraction Levels

SYSTE

GATE

CIRCUITCIRCUIT

MODULE

DEVIC


22/70

VLSI

Major Design Challenges

qqqqq

q

qqqqq

q


23/70

VLSI

Design Metrics

qqq

qqq

qqq

q


24/70

VLSI

Cost of Integrated Circuits

q---

qq

qq

-

qq


25/70

VLSI

Silicon Wafer


26/70

VLSI

Variable Costs


27/70


28/70

VLSI

Examples of Cost Metrics (1994)


29/70


30/70

VLSI

Example of Capacitive Coupling

q Signal wire glitches as large as 80% of the supply voltage willbe common due to crosstalk between neighboring wires asfeature sizes continue to scale

Crosstalk vs. Technology


31/70

VLSI

Static Gate Behavior

q static behavior

q

q nominal voltage level

q signal swing


32/70

VLSI

DC OperationVoltage Transfer Characteristics (VTC)

Switching


33/70

VLSI

Mapping Logic Levels to the Voltage Domain

"1"

"0"

Undefined

q


34/70

VLSI

Noise Margins

Undefined

"1

"0

Gate Gate

Noise Margin

Noise Margin


35/70


36/70

VLSI

Directivity

q undirectional

q full

q output impedanceinput impedanceqq


37/70


38/70

VLSI

The Ideal Inverterqqqq


39/70

VLSI

The Ideal Inverterqqqq

g = -


40/70

VLSI

Design Metrics

qqq

qqq

qqq

q


41/70

VLSI

Delay Definitions

t

V

Vi

t

Vi V


42/70

VLSI

Delay Definitions

t

V

Vi

t = (t HL +

t

t t

t t

Vi V


43/70

VLSI

Modeling Propagation Delay


44/70

VLSI

Power and Energy Dissipation

q

q

q

q


45/70

VLSI

Power and Energy Dissipation

qq

q

S


46/70

VLSI

qq

qq

Summary


47/70

VLSI

CMOS Transistor


48/70

VLSI

Review: Design Abstraction LevelsReview: Design Abstraction Levels

SYSTE

GATE

CIRCUITCIRCUIT

MODULE

DEVIC

Th MOS T i


49/70

VLSI

The MOS Transistor

Polysilicon or MetalAluminum orCopper

Th NMOS T i t C S tiTh NMOS T i t C S ti


50/70

VLSI

The NMOS Transistor Cross SectionThe NMOS Transistor Cross Section

L

S it h M d l f NMOS T i t


51/70

VLSI

Switch Model of NMOS Transistor

Th PMOS T i t C S tiTh PMOS T i t C S ti


52/70

VLSI

The PMOS Transistor Cross SectionThe PMOS Transistor Cross Section

L

S it h M d l f PMOS T i t


53/70

VLSI

Switch Model of PMOS Transistor


54/70

Th Th h ld V lt


55/70

VLSI

The Threshold Voltageq

q

q

T i t i Li M dT i t i Li M d


56/70

VLSI

Transistor in Linear ModeTransistor in Linear Mode

Voltage Current Relation: Linear Mode


57/70

VLSI

Voltage-Current Relation: Linear Mode

q

The Body Effect


58/70

VLSI

The Body Effect

qq

Transistor in Saturation ModeTransistor in Saturation Mode


59/70

VLSI

Transistor in Saturation ModeTransistor in Saturation Mode

Voltage Current Relation: Saturation Mode


60/70

VLSI

Voltage-Current Relation: Saturation Mode

q

q

Current Determinates


61/70

VLSI

Current Determinates

qqq

q

qq

-

-

Long Channel I V Plot (NMOS)


62/70

VLSI

Long Channel I-V Plot (NMOS)

Short Channel I V Plot (NMOS)


63/70

VLSI

Short Channel I-V Plot (NMOS)


64/70

Unified Transistor model for manual analysisUnified Transistor model for manual analysis


65/70

VLSI

Unified Transistor model for manual analysisUnified Transistor model for manual analysis

Note:

Unified model vs separate modelsUnified model vs separate models


66/70

VLSI

Unified model vs separate modelsUnified model vs separate models

By definition VGT== VGS VT, remember this wile looking at equations below

Case 1: Vmin = VGT, Saturation

Case 2: Vmin = VDS , Linear

Case 3: Vmin = VDSAT , Velocity

saturation

remember kn =

Boundaries of operation for Unified ModelBoundaries of operation for Unified Model


67/70

VLSI

Boundaries of operation for Unified ModelBoundaries of operation for Unified Model


68/70

Other MOS Transistor Concerns


69/70

VLSI

Other MOS Transistor Concerns

q q

q

qq

q

qq

q

Present and Future PerspectivesPresent and Future Perspectives


70/70

Present and Future PerspectivesPresent and Future Perspectives

25 nm FINFET MOS

lecture 1 - intro,transistor

Documents