lec 5 spice model
TRANSCRIPT
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CMOS Digital Integrated Circuits1
CMOS Digital Integrated Circuits
Lec 5
SPICE Modeling of MOSFET
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CMOS Digital Integrated Circuits2
SPICE Modeling of MOSFETS
Goals
Understand the element description for MOSFETs
Understand the meaning and significance of the various parametersin SPICE model levels 1 through 3 for MOSFETs
Understand the basic capacitance models
Have a general notion of BSIM model parameters
Become award of some newer models
Understand the use and shortcomings of the models covered Note: In the following, HSPICE = Star-HSPICE
Rederences
Massobrio, G., and P. Antognetti, Semiconductor Device Modeling withSPICE, 2nd Edition, McGraw-Hill, 1993.
Foty, D.,MOSFET Modeling with SPICE
Principles and Practice,Prentice Hall PTR, 1997.
StarHspice Manual, Avant!http://cmbsd.cm.nctu.edu.tw/~yumin/tutorial/hspice_qrg.pdf
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CMOS Digital Integrated Circuits3
The MOSFET Description Lines
Model and Element
What does SPICE stand for? Simulation Program with Integrated Circuit Emphasis
The MOSFET Model and Element Description Lines
Process and circuit parameters which apply to a particular class of
MOSFETS with varying dimensions are described for that class of
MOSFETS in a single .model line in which + is used to denote linecontinuation.
The dimensions are given on the element description line. In both, it is
critical to watch the units; they are basically illogical!
The SPICE element description line for a MOSFET has the following
form: Mxxxxxxx nd ng ns mname
All parameter value pairs between < and > are optional.
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CMOS Digital Integrated Circuits4
The MOSFET Description Lines
Element Line (Continued)
Additional optional HSPICE parameters:
TEMP=val is not used on element line in HSPICE and not used for level
4 or 5 (BSIM) models.
Parameter Definitions
See http:\\cmbsd.cm.nctu.edu.tw\~yumin\tutorial\hspice_qrg.pdf
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CMOS Digital Integrated Circuits5
DC SPICE Models
Level 1 (Shichman-Hodges) DC Model
EquationsVTEquation as derived previously
IDEquations as derived previously with linear mode equation times(1+VDS) for continuity across linear-saturation boundary. Both useLeff in place ofL where:
Leff= L 2 LD
Key Parameters: What do they represent? See Kang and LeblebiciTable 4.1
NMOS, PMOS (obvious) MOSFET channel type
KP process transconductancek
VTO (note O, not 0!) zero substrate-bias threshold voltage VT0
GAMMAsubstrate-bias or body-effect coefficient PHItwice the Fermi potential 2FLAMBDA channel length modulation
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CMOS Digital Integrated Circuits6
DC SPICE Models
Level 1 (Continued) Additional Parameters: What do they represent?
LD Lateral diffusion (If not present, may need to find Leffmanually!)
TPGType of gate material: 0 A1, +1 opposite to substrate, -1 same as substrate. Default +1. For the typical CMOS process, TPG = 1for NMOS and 1 for PMOS
NSUBsubstrate impurity concentration NA (NMOS) ND (PMOS)
NSS Surface state density Used to define surface component ofVT0.
TOXOxide thickness toxU0 (note 0, not O) Surface mobility 0
RD, RS Drain resistance, Source resistance
RSHDrain and Source sheet resistance (/) Derived Parameters. Note that if some parameters missing, others, if
present, can be used to derive them. E. g. NSUB to derive PHI, and TOXand U0 to derive KP. Question: What parameters to derive GAMMA? Ifthe derivable parameters are present in the model, they will be used; ifnot, derived if possible from other parameters (and defaults), else,defined.
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CMOS Digital Integrated Circuits7
DC SPICE Models
Level 2 What about defaults and units? See Table 4.1. of Kang and Leblebici
Other parameters in Level 1 are related to capacitance (later) or irrelevantto digital applications.
Level 2
Analytical model that takes into account small geometry effects.
Equations that use most of the parameters are given in the text.
Parameters in addition to those for Level 1:
NFS - Fast surface state density Used in modeling subthresholdcondition.
NEFFTotal channel charge coefficient Empirical fitting factormultiplied times NSUB in the calculation of the short channel effect .Used only in Level 2.
XJJunction depth of source and drain.
VMAXMaximum drift velocity for carriers use for modeling velocitysaturation.
DELTAChannel width effect on VT.
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CMOS Digital Integrated Circuits8
DC SPICE Models
Level 2 (Continued)
XQCCoefficient of channel charge share. Used to specify the portionof the channel charge attributed to the drain. Also, more importantly
causes the Ward capacitive model to replace the Myer capacitance
model. Both have their disadvantages.
Next three parameters produce a multiplicative surface mobility
degradation factor to multiply times KP and appear in Level 2 only.
UCRITCritical electric field for mobility degradation.
UEXPExponent coefficient for mobility degradation.
UTRATransverse field coefficient for mobility degradation.
Coefficient ofVDS in denominator of the factor.
See Table 4.1. of Kang and Leblebici.
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CMOS Digital Integrated Circuits9
DC SPICE Models
Level 3
More empirical and less analytical than Level 2; this permits improvedconvergence and simpler computation while sacrificing little accuracy.
The parameters have beyond those in Level 2 (Note that the following
Level 2 parameters are deleted: NEFF, UCRIT, UEXP, and UTRA.)
KAPPA Saturation field factor. An empirical factor in the equation
for the channel length in saturation.
ETAstatic feedback on VT. Models effect ofVDS on VT, i.e., DIBL
(Drain-Induce Barrier Lowering)
THETAMobility modulation. Models the effect of VGS on surface
mobility.
See Table 4.1 of Kang and Leblebici.
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CMOS Digital Integrated Circuits10
Capacitance Models
Level 1 through 3 use the Myer capacitance model(see Kang and
LeblebiciFig.3.32) as the default for the channel capacitance with the
option of the Ward model (see Kang and Leblebici Fig.4.8) in Levels 2and 3.
For the source and drain capacitances, note the junction equation with
reverse bias Vwith VT, the thermal voltage,
I =Is(eV/VT-1)=-Isfor V-4VT
and recall thatCj=Cj0/(1-V/0)m
where m = 1/2for an abrupt junction and m = 1/3for a graded junction.
The parameters:
ISBulk junction saturation current.
JSBulk junction saturation current density (used with junction areas)
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CMOS Digital Integrated Circuits11
Capacitance Models (Cont.)
PB - 0Bulk junction Potential (Built-in voltage)CJZero-bias bulk junction capacitance per m2
MJmBulk junction grading coefficient
CJSWZero-bias perimeter capacitance per m
MJSWmPerimeter capacitance grading coefficient
FCBulk junction forward bias coefficient used in evaluating capacitanceunder strong forward bias.
CGBOGate-bulk overlap capacitance per meter ofL; should be set to 0 if
modeled as interconnect instead.
CGDOGate-drain overlap capacitance per meter ofW
GDSOGate-source overlap capacitance per meter ofW See Table 4.1. of Kang and Leblebici
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CMOS Digital Integrated Circuits12
More SPICE Models
BSIM (Level 4)
An empirical model that includes:all of the typical small geometry effects
the nonuniform doping profile for ion-implanted devices
an automatic parameter extraction program which produces a consistent
set of parameters
L and W for the channel For BSIM parameters, see Foty Table 8.1
We will not look at these parameters in detail, but it is quite important to
look at the form of the electrical parameters. Each electrical parameters Pis
represented by three process parameters P0, PL, and Pw associated with P
W
WLWP
L
DLLPPP
effeff
WL
0
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CMOS Digital Integrated Circuits13
SPICE Models
BSIM (Cont.)
L and W are drawn dimensions and DL and DW are the net size changes inthe drawn dimensions due to the entire sequence of fabrication steps. The
difference shown give Leffand Weff. The equation forPallows for an
adjustment of the electrical parameter as a function of the effective length
and width of the channel
Parameterextraction uses devices sizes. P0 is for long, wide MOSFET.
BSIM also uses a new approach to capacitance modeling that avoids the
difficulties of errors and lack of charge conservation in the Meyer model and
the errors and convergence problems in the Ward model.
See Massobrio and Antognettip. 219 for trios of parameters.
Note that model file has only numerical values identified by position; this is
an alternate form of the model that cryptic.
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CMOS Digital Integrated Circuits14
More SPICE Models
HSPICE Level 28, BSIM2, BSIM3
HSPICE Level 13 is BSIM
HSPICE Level 28 - a very popular modification of BSIM, but can only be
used in HSPICE
BSIM2 (HSPICE Level 39) typical model today for those not using
HSPICE
BSIM3 Version 3.2 (HSPICE Level 49) a complex new public domain
model that is frequently used today. This is our model unless otherwise
specified. See http:/cmbsd.cm.nctu.edu.tw/~yumin/tutorial/n96g.L49
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CMOS Digital Integrated Circuits15
Which Model Should I Use?
Level 1: At best, for quick estimates not requiring accuracy. Very poor forsmall geometry devices. Viewed as obsolete by some.
Level 2: Due to convergence problems and slow computation rate,abandoned in favor of Level 3 or higher.
Level 3: Good for MOSFET down to about 2 microns.
BSIMLevel 4 (HSPICE Level 13): good for small geometry MOSFETS
with L down to 1 micron and tox down to 150 Angstroms. Problems nearVsat; negative output conductance; discontinuity in current at VT. Forsubmicron dimensions, replaced by BSIM2 and HSPICE Level 28.
BSIM2 (HSPICE Level 39): Good for small geometry MOSFETs with Ldown to 0.2 micron and tox down to 36 Angstroms.
HSPICE Level 28: BSIM with its problems solved; good choice for
HSPICE users. BSIM3 Version 3 (HSPICE Level 49): Most accurate, but complex.
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Summary
Learned the element description line for MOSFET
Reviewed the first generation SPICE model parameters, levels 1, 2, and 3
Reviewed the device capacitances and associated parameters for the BSIM
model
Obtained a sense of the form of the parameters for the BSIM model
Obtained an awareness of some of the newer models Obtained a comparative viewpoint of the models and their use.