Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

LCLS TimingOutline

Scope The order of thingsIntroducing the PNET VME receiver Status of the PNET VME receiverSystem diagramLooking at timing pulse to pulseLCLS MPGEVG Conclusions

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

ScopeLCLS timing system is used to transmit a fiducial 360 Hz signal to all triggered devices in LCLSSystem requirements (speed and content) are known: receive 128 bit PNET data at 360 Hz; append add’l info; operate at 120 HzThe component parts are known: PNET VME receiver, EVG-200 and EVR-200The interfaces are being defined

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

The order of thingsThe one and only SLC Master Pattern Generator (MPG)

Takes as input: 360 Hz fiducial from SLC PDU is the signal to create a new PNET buffer Performs tasks:

creates PNET buffersresponds to faults

Outputs PNET buffers to all micros and PNET VME receiver on the next 1/360 s fiducial

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

Introducing the PNET VME receiverN

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

Status of the VME PNET receiverHardware prototype is finished (1 instance)Board is 3 slots wide to accommodate on board cable modem interface to PNETEngineering Design Specification doc writtenDriver and device support (bi, mbbiDirect to access each variable in PNETbuffer) written. Compiled only for Synergy PPC running RTEMS 4.6.2

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

System Diagram

LCLS MPS(new)

MKSU MPS

MPG

SCP

EVG

EVR

PNET

Arrives within 8.3 ms(1-120 Hz beam pulse)

PNET

Arrives within 24.9 ms(3-120 Hz beam pulses)

EVR

Bit pattern of instructions for current beam pulse + fault indicators

CPU

CPU

LCLS MPG

SLC-AWARE IOC SLC-AWARE IOC

CPU

Slow control (eg setup commands)

Mode of running (eg rate limit)

LCLS beam loss

monitor(new)

PEP beam loss

monitor(existing)

LINAC vacuum interlock (existing)

Within 1/360 s

LCLS vacuum (new)

LCLS power

supplies (new)

Orbit tolerances

Turn on (to drive beam to dump)/clear Kicker

Turn off/clear

Laser

Kicker status

Laser status

RF 119 MHz clock with

360 Hz fiducial(existing)

Gated data acquisition application (eg. BPM)

Gated data acquisition application (eg. BPM)

BPM

hw

BPM

hw

Needs to be added so that LCLS vacuum leak detection shuts off klystron

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

Looking at timing pulse to pulse Time

in milliseconds(the 360 Hz fiducial)

0.00

2.78

5.56

120 Hz signal

SLC PDU

MPG ISR Each micro VME PNET receiver

sends intr3 to MPG

sends intr4 to MPG

- receives intr 3- reads fault bits from camac- if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (createdlast intr)- sends (modified) PB2- finds which BGRP to execute- based on fault bits and BGRP var (from operator), find MGRP- execute MGRP which creates PB3

- receives intr 4- updates PB3 if new faults- sends PB3-creates PB4

- is interrupted by the arrival of PB2- xlate 5-bit base beamcode + modifier bits in PB2 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB2 will happen next fiducial- set up camac FC F19A9 so that “1/360s early” cmds from PB1 will happen next fiducial- set up camac FC F19A8 so that “on time” cmds from PB0 will execute next fiducial- looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next-saves PB2 to current full sec buffer

PBx = PNETbuffer 'x' is 16 bytes (128 bits);4 "one second"s worth of PNET buffers is kept in 4 separate arrays

- receives PB2- does checksum(s) and - if error, appends flag- appends epicsTimeStamp- sets flag that data2 ready

LCLS MPG

receives flag that data2 readyadds additional cmds for new apps ext to SCPappends faults that occurred since PB2 createdsets flag that EB2 ready

EBx = EVG buffer 'x' is ~24 bytes (192 bits)

128 µs + several µs for speed of light travel

BGRP=PEPII

BGRP=CRYO

- is interrupted by the arrival of PB3- xlate 5-bit base beamcode + modifier bits in PB3 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB3 will happen next fiducial- set up camac FC F19A9 so that “1/360s early” cmds from PB2 will happen next fiducial- set up camac FC F19A8 so that “on time” cmds from PB1 will execute next fiducial- looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next-saves PB3 to current full sec buffer

- receives PB3- does checksum(s) and - if error, appends flag- appends epicsTimeStamp- sets flag that data3 ready

receives flag that data2 readyadds additional cmds for new apps ext to SCPappends faults that occurred since PB2 createdsets flag that EB2 ready

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

Looking at timing pulse to pulse Time

in milliseconds(the 360 Hz fiducial)

5.56

8.33

11.11

13.89

120 Hz signal

SLC PDU MPG ISR Each micro VME PNET receiver

sends intr5 to MPG

sends intr6 to MPG

LCLS MPG

BGRP=PEPII

BGRP=LCLS

BGRP=CRYO

sends intr7 to MPG

sends intr8 to MPG

- receives intr 5- updates PB4 if new faults- sends PB4-creates PB5

- is interrupted by the arrival of PB4- xlate 5-bit base beamcode + modifier bits in PB4 into 8 bit beamcode and set up camac FC F19A10 so that “2/360s early” cmds in PB4 will happen next fiducial- set up camac FC F19A9 so that “1/360s early” cmds from PB3 will happen next fiducial- set up camac FC F19A8 so that “on time” cmds from PB2 will execute next fiducial- looks for YY=243. If found, mark current full sec buffer not to be overwritten OR if full, mark next-saves PB4 to current full sec buffer

BGRP=LCLS

- receives PB4- does checksum(s) and - if error, appends flag- appends epicsTimeStamp- sets flag that data4 ready

...

Pattern repeats

receives flag that data4 readyadds additional cmds for new apps ext to SCPappends faults that occurred since PB4 createdsets flag that EB4 ready

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

Looking at timing pulse to pulse Time

in milliseconds(the 360 Hz fiducial)

0.00

2.78

5.56

8.33

11.11

120 Hz signal

SLC PDU MPG ISR VME PNET receiver LCLS MPG EVG Each EVR

sends intr3 to MPG

SLC-aware IOC

Sees flag that EB2 ready

Sends EB2 at 125MHz

Receives EB2 < 1 μs later

(50 ns/2 B)*24B + overhead + fiber length travel time

- receives intr 3- reads fault bits from camac- if BCS fault bit asserted, ISR sets BCSFAULT modifier bit in PB2 (createdlast intr)- sends (modified) PB2- finds which BGRP to execute- based on fault bits and BGRP var (from operator), find MGRP- execute MGRP which creates PB3

- receives PB2- does checksum(s) and - if error, appends flag- appends epicsTimeStamp- sets flag that data2 ready

128 µs + several µs for speed of

light travel

receives flag that data2 readyadds additional cmds for new apps ext to SCPappends faults that occurred since PB2 createdsets flag that EB2 ready

...

Pattern repeats

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

LCLS MPGTakes the PNETbuffer with appended epicsTimeStamp and checksum fault indicatorsAdds on LCLS application commandsAdds on any newly detected faultsInforms EVG that data is ready

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

EVGOn board FPGA packages/chunks 24 byte LCLS MPG data and sends to EVR at 125 MHzData arrives in EVR in 0.6 microseconds + fiber travel time (which depends on distance)

Dayle Kotturi EPICS Collaboration Meeting at SLAC dayle@slac.stanford.edu

April 27-29, 2005

ConclusionsLCLS MPG needs to be designedLCLS MPG/EVG interface needs definingEVR/SLC-aware IOC interface needs definingPerformance and reliability from PNET through to EVG must be measuredBut I guess there has been some progress…