layout

VLSI Engineering (EC31004) Spring 2010

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EC31004: VLSI Engineering Notes Filename: VLSI_Eng_CMOS_Layout_.doc

Last updated: 15 Mar 2010 (working document)

Content

1. Circuit layout ..........................................................................................................................................................2

1.1. Layout and various design flows ......................................................................................................................2

1.1.1. FPGA based design ....................................................................................................................................3

1.1.2. Gate array based design..............................................................................................................................7

1.1.3. Standard-cell based design .........................................................................................................................8

1.1.4. Full-custom based design .........................................................................................................................12

1.2. Full-custom layout techniques ........................................................................................................................13

1.2.1. Transistor using multiple fingers..............................................................................................................15

1.2.2. Stacking of multiple transistors ................................................................................................................18

1.2.3. Matching of transistors.............................................................................................................................18

1.3. CMOS Latch-up .............................................................................................................................................20

1.4. Stick diagrams ................................................................................................................................................28

1.5. Resistor layout ................................................................................................................................................33

1.5.1. Sheet resistance ........................................................................................................................................33

1.6. Capacitor layout..............................................................................................................................................38


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1. Circuit layout

1.1. Layout and various design flows

FPGA Gate array Standard-cell Full-custom


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1.1.1. FPGA based design

Figure 1. FPGA based IC layout : two-dimensional array of CLBs


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Figure 2. FPGA based IC layout: switch matrix connecting the CLBs


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Figure 3. FPGA based IC layout: Internal of a CLB Xilinx XC4000 family example


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Figure 4. FPGA based IC layout: internal of a 16x2 single-port memory block Xilinx XC4000 family example


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1.1.2. Gate array based design

First-phase: generic-mask for array of transistors Second-phase: circuit specific mask for transistor interconnects

Figure 5. Gate-array based IC layout: Transistors in first-phase, circuit-specific metal-layers in second-phase


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1.1.3. Standard-cell based design

Standard-cell library o Development resource and development time for full-custom

Each library-cell has the following information: o Logic simulation model o Delay-time vs. load capacitance o Timing simulation model o Fault simulation model o Place-and-route data and mask-design data

System integration: o Rows of cells channel


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Figure 6. A standard-cell IC layout block-diagram


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Figure 7. A standard-cell IC layout with one global signal-bus


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Figure 8. Standard-cell IC layout showing channel routing without using over-the-cell routing


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1.1.4. Full-custom based design

Layout starting from device level

Figure 9. NMOS transistor layout in n-well process

Figure 10. PMOS transistor layout in n-well process


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Figure 11. CMOS inverter layout in n-well process

1.2. Full-custom layout techniques


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Figure 12. Various transistor custom layout scheme and the effect on drain-capacitance


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1.2.1. Transistor using multiple fingers

Figure 13. Using multiple fingers of wide transistor

Reduction in height for very wide transistors Reduction in distributed resistance along the poly-gate (from poly-gate to Metal-1 contact)


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Figure 14. Transistor layout examples: 1 finger vs. 2 finger vs. 3 finger


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Figure 15. Custom layout examples for 2-input NAND gate with and without fingers


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1.2.2. Stacking of multiple transistors

Figure 16. Transistor layout: transistor stacking

Reduction in size happening because of: o Common M2-drain and M1-source (M2-source or M1-drain) area o Removal of contacts from M2-drain and M1-source (or M2-source and M1-drain)

1.2.3. Matching of transistors

Multiple objectives of matching o Achieving the geometric ratio needed in electrical design o Minimizing the effect of spatial gradation of process parameters o Minimizing the effect of adjacent device (passive / active) structure


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Figure 17. Transistor layout matching: before layout optimization

Figure 18. Transistor layout matching: after layout optimization


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Figure 19. Layout matching: (1) size matching, (2) gradient, (3) parasitic coupling

1.3. CMOS Latch-up

Parasitic shorting of VDD and GND In normal operation, the parasitic transistors are OFF Triggering through the undesired transient-current through VDD or GND


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Figure 20. CMOS inverter vertical cross-section showing parasitic transistor


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VDD

GND

RWELL

RSUB

Figure 21. CMOS inverter parasitic transistors: equivalent circuit for latch-up consideration

Example: o Current surge from VDD voltage drop across RWELL VBE developed for the parasitic PNP transistor

o The current in-turn drops across RSUB VBE developed for the parasitic NPN transistor

o The current in-turn drops across RWELL and so on


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Current in the loop is self-sustained once it develops thyristor characteristics Layout guidelines: weaken the parasitic effect

o Increase # of contacts for WELL and P-SUB (in the above example) reduce RSUB and RWELL o Use continuous strip of guard-band or guard-rail for substrate and well contact o Reduce physical spacing between PMOS and P-sub contact

Reduce physical spacing between NMOS and N-well contact

o Avoid resistive VDD and GND (e.g. do not use poly-Si or diffusion area; instead, use metal) o Place internal circuitry away from external pads o Consider latch-up possibility when SOURCE terminal of NMOS or PMOS are not at the same

potential of p-substrate or N-well, respectively


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Figure 22. Transistor with multiple gates: internal area may not be covered by tub / substrate contacts


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Figure 23. Hard-tie for tub (well) / substrate contacts


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Figure 24. Soft-tie for tub (well) / substrate contacts


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1.4. Stick diagrams

Figure 25. inverter schematic and corresponding stick-diagram and its actual layout (standard-cell approach)


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Figure 26. inverter schematic and corresponding stick-diagram using fingered transistors (standard-cell approach)


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Figure 27. inverter layout using fingered transistors (standard-cell approach) and the equivalent circuit


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Figure 28. CMOS NOR gate layout : stick-diagram and actual layout (standard-cell approach)


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Figure 29. CMOS NAND2 gate layout : stick-diagram and actual layout (standard-cell approach)


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1.5. Resistor layout

1.5.1. Sheet resistance

Resistance per-square Let, conductor length = L, conductor width = W, conductor thickness = t, resistivity of material =

R = RS (L / W),

where, sheet resistance, RS = ( / t) Resistance = (Sheet resistance) * (Length-to-width ratio)

Figure 30. sheet resistance

Example [in ohm / square]: o Metal1-Metal2 : 0.05 to 0.10 o Top-metal : 0.03 to 0.05


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o Poly-Si : 15 to 30 o Poly-Si with silicide (e.g. TiSi2) : 4 to 5 o Diffusion (n+, p+) : 50 to 150 o n-well / p-well : 1K to 2K

Figure 31. resistor: unit-cell and large resistor using multiple unit-cells


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Figure 32. resistor: use of guard-rings to reduce noise injection from substrate


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Figure 33. resistor: matching of two resistors


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Figure 34. resistor matching: interdigitated or interlacing approach

Figure 35. resistor matching: common-centroid approach


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1.6. Capacitor layout

Figure 36. capacitor: poly-poly cap example


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Figure 37. capacitor: area-capacitance and fringing capacitance

Area-capacitance and Fringe-capacitance Area-capacitance per unit-area and fringe-capacitance per unit-length between the layers (e.g. Metal1 to

Metal2) are given for any particular process


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Figure 38. capacitor: poly-poly cap using multiple fingers


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Figure 39. capacitor: poly-poly cap using unit-cell: close to circular shape (sharp corners avoided)

Typical capacitance values for thin-oxide / gate-oxide of thickness (xOX) 100 angstrom = 864 x 10-18 F / um2 Typical capacitance values (0.25 um process) for adjacent layers -- examples:

Typ. area-capacitance (10-18 F / um2) Typ. fringe-capacitance (10-18 F / um)

Metal1 poly-Si 57 54

Metal2 Metal1 36 45

Metal3 Metal2 41 49

Metal4 Metal3 35 45


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Metal5 Metal4 38 52

Typical capacitance values (0.25 um process) for different layers -- examples: Typ. area-capacitance (10-18 F / um2) Typ. fringe-capacitance (10-18 F / um)

Metal3 Metal1 15 27

Metal4 Metal2 15 27

Metal4 Metal1 8.9 18

Metal5 Metal3 14 27



layout

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ic layout

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