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Laser fabrication technologies
Brian Corbett
An overview of the principal technological processes used in therealisation of high brightness laser diodes.
Presented at the Bright.EU plenary meeting in Aachen 8th Feb. 2006
Outline of technological steps for example processOptical lithographyPlasma fundamentalsEtchingDielectric depositionMetallisationEvaporationSpecial techniquesProcess completionFacet coating
Outline
Wavelengths635, 650nm AlGaInP/GaAs808nm AlGaAs/GaAs920nm InGaAs dots/GaAs
InGaAs/AlGaInP/GaAs980nm InGaAs/AlGaInP/GaAs
Laser categoriesBroad AreaBroad area with taperRidge to provide index guidingCurved facetsLaser bars--------------Buried Heterostructures VCSELs
EpitaxyLayered structure that need to be structured spatially and verticallyCan include etch stop layers
Lasers and Bright.EU
Majorflat
Minor flat
Diameter: 50, 75mm
Process sequence (example)
GaAs Substrate
300µm – 650µm
p-type layers
n-type layers
1.5µm
1.5µm
0.3µmActive layers
GaAs is a fragile material in comparison with Silicon
GaAs wafer
Ridge waveguide process sequence
1. Etch waveguide to desired depth0. Starting wafer cross-section
3µm
2. Deposit dielectric isolation
0.1µm-0.2µm
3. Open dielectric for p-contact
Ridge waveguide process sequence
5. Deposit p-contact metal 6. Electroplate additional metal
7. Thin substrate and deposit n-contact
100-140µm
8. Anneal9. Cleave into bars10. Facet coat11. Attach to sub-mount12. Wirebond
Example ridge
Many alternative (and better) process strategies including self-alignment
Process technologies
LithographyPlasma techniques
RIE/ICPPECVDSputtering
Evaporation
Optical lithography
NAKd λ=min
Broadband exposure (0.8 µm)G-line exposure 436nm (0.6 µm )I-line exposure 365nm (0.35 µm)
Environmental requirementsTemperature, humidity need to be tightly controlledVery clean processing conditions are required Carried out in ‘yellow room’ as white light will expose the resist
ObjectiveTransfer pattern from a mask into a temporary (resist) layer sufficient to permit spatially dependent processing steps
Resolution
ToolsContact between mask and resistStepper – projection of reticle onto resist; step and repeat
Resist
Semiconductor
UV LIGHT
Expose
Develop
Mask
Semiconductor
Dehydrate BakeSurface PrimeResist Spin Positive and negative resistsSoft Bake Removes solvents from the resist Exposure to UV Contact aligners, projection aligners, steppersPost Exposure Bake To reduce standing wave effects in exposed resistDevelopHard Bake Removes residual solvent & Improves thermal stability
Lithography process steps
Quartz with pattern etched in chrome surface
Positive resists
Positive resist used in all small geometries (<3 µm)Exposed areas of resist are removed during the develop stepResin based polymer containing a photoactive compound (PAC)Resist comes in liquid form due to the presence of solvents in the resinPAC when exposed to UV radiation in the presence of moisture forms a carboxylic acidThis acid is removed during the develop stage by the alkaline based developer Unexposed areas of resist are also soluble in developer solution
Difference in develop rates between exposed and unexposed areas is ~1000:1 Resist profiles of 90º are possible
AZ 5214 no reflow AZ 5214 reflow
Other resist issues
Critical dimensions realisedWafer flatnessContact distance
“Poisson spot”Resist thickness
Planar surface for best contact - topographyStep height, reflectometryResidual resist after develop
Resist etch resistanceHarden processes (DUV)Transfer into dielectric mask
Resist removal after processSolventsO2 plasma
Alignment between levels0.5 – 1µm
Planarisation
Photosensitive dielectricsBenzocyclobutene (BCB)Polybenzoxazole (PBO)Polyimide
Etch or expose back
MetalDeposit
Plasmas
A partially ionised gasfree electrons collide with neutral atoms/molecules creating reactive speciespositively charged; negatively charged; neutrals
Provides a transport mechanism to take these species to a wafer surfacemotion through gas velocity and electric fieldsInteraction resulting in deposition, reaction, desorption,…
Basis of most forms of etching, sputter deposition, PECVD, resist removal
Generally RF power capacitively coupled plasmas at 13.56MHz
Plasma formation and characteristics
Electrons accelerated in electric fieldCan follow field for 1-100 MHzenergetic 100-1000eV
Ions at thermal energyElectrons initially escape from plasma
Low pressureDC field forms to repel electrons from wallsAC voltage imposed on negative bias
z
VDC
Powered electrode
Groundedelectrode
Lower density of electrons adjacentto electrodes
Less recombinationDark sheath
RF
Gas in
Gas out
LowPressureChamberFew Pa
Plasma sheath
t
Electron current
VDC
Macroscopic parametersGas PressureRF powerGas Flows
Positive ion current
Plasma sheath oscillatingIons which are ‘revealed’ are accelerated
Direction providedNeutrals unaffected in flux/directionNegative ions (Cl, F) accelerated
Strongly affect DC bias
Microscopic parameterselectron densitygas species……
Langmuir probe:Metal needle Bias +/- to extract energy dependent ion and electron current
Microscopic parameter measurements
Optical Emission Spectroscopy (OES)
V
I Electronflux
+ve ionflux
Vf
Extractne, nI, Te, spatial distribution
DifficultiesProbe shieldingProbe contaminationSecondary electrons….
Pres
sure
Ener
gy
Sele
ctiv
ity
Anis
otro
py
Physical Processes
ChemicalProcesses
Sputter Etch &Ion Beam Milling
High Density Plasma Etch
Reactive ion Etch
Plasma Etch
Chemical Etch
Plasma Etch Process Parameters
Reactive Ion Etching (RIE)
Etch mechanism:Formation of reactive speciesTransport to the surfaceAdsorption of reactive species onto surfaceChemisorptionReactionDesorption
Chemical; High pressure, low bias, Highly reactive speciesPhysical; Low pressure, high bias, low-reactive speciesPhysical-chemical Use ion direction to control the etch
Chemical Etching
UndercuttingSidewall polymer deposition
Trenching
+
Physical Etching
Resist Erosion
MaskingMaterial
Requirements from etch
Sidewall passivation
ApplicationsRidge formation for index guidingCavity spoilersCurved facet
Lithographic definition – suitable mask Generally require strong anisotropy (non-selective)Smooth etched surface; smooth sidewallsControlled etch rate and profile
SiClx, B2Cl4 rather than polymers
Inductively Coupled Plasma (ICP) Etching
ICP
Limitations of RIECannot separate ion energy from species generation (density)As increase RF power for higher density -> higher ion energy
-> more damage; less anisotropySeparate out plasma generation from ion energy
ICP or ECR (Electron Cyclotron Resonance)
RF
RF
High density plasma
Gas in
Gas out
Etch chemistries
Oxide / Nitride etch CF4 / CHF3 basedCF2 is produced by the reaction: CHF3 ---> CF2 + H + FCF2 can then polymerise to form a teflon-like polymerCan also etch GaAs
GaAs etch Cl2; BCl3; SiCl4 basedDesorption of Ga chlorides slower than As chloridesHigher temperature to maintain stoichiometry
InP Etch CH4/H2 based; Cl2Need small O2/Ar to reduce polymer buildupNeed high temperatures (>1600C) for Cl based etching to desorb InCl
C C C C C C C
F
F F F F F
F F F F F F
F F
Curved facetCurved facet
3- level resist process
Etch rate of resist similar to material – need a more robust mask process
Etch issues
Uniformity of etchLayer selectivityEtch depth control
Monitoring reflectivity from a multilayer structureOES of plasma contents
Hydrogen passivationEtch depth dependence on opening
Etch dependent on mask
SiO2 Resist
Wet Etching
Used inEtch stop layer - Highly selective etching
eg GaAs over Al0.2Ga0.8As using citric acid based etch Contact layer etchSubstrate etch
Because the etch is purely chemical wet etches are:isotropic i.e. vertical and lateral etch rates equalcrystallographic
Different etch rate for different materials (layers)Limitation is size of detail which can be etched consistentlyCan be difficult to control temp,pH etc.
Resist
Perpendicular tomajor flat
Parallel tomajor flat
Plasma Enhanced Chemical Vapour Deposition(PECVD)
PECVD - Plasma Enhanced CVDSilicon dioxide, Silicon Nitride
LPCVD - Low pressure CVDPolysilicon, silicon nitride and tungsten deposition
APCVD - Atmospheric pressure CVDSilicon dioxide
MOCVDEpitaxy
Silicon Dioxide: SiH4 + 2N2O -----> SiO2 + 2H2 + 2N2
Silane and nitrous oxide react to give silicon dioxide Plasma oxides are generally poorer quality than LPCVD oxidesPlasma oxides tend to contain large amounts of hydrogen (>12 wt%)
due to incomplete dissociation of silane
PECVD Process: High pressure (500mTorr); Substrate temperature 250-3500C
Silicon Nitride: SiH4 + NH3 + N2 -----> SixNy(H)
Deposition temperature is 300 - 350ºCGood barriers to moisture and ionic contaminationPlasma nitride films also have large amounts of hydrogen (>20 wt%)Better wet etch resistance than SiO2
Silicon Oxynitride: SiH4 +NH3 + N2O -------> SixOyNz(H)
Properties somewhere between that of nitride and oxideUsed when requires the optical properties of oxide and the barrier properties
of nitride
PECVD
Issues:
Step coverageStress controlParticulatesHydrogen incorporation
RF Sputtering
Energetic ions used to sputter metals / oxides from a target using a plasmaResults in the metals / oxides being re-deposited on surface of interest
Ar plasma typical but Ar/O2 for some dielectrics
Not used as often in III-V as not so compatible with resistsRequiring subsequent metal / oxide etch
Metallisation requirements
Low resistivity contact (ρc < 10-6 Ωcm2) to p-type and n-type GaAsRc = ρc / Area
Excellent adhesion
Reliable (Spiking, electro-migration; environmental)
Easy to solder / wire bond, Excellent current spreading in metal film
Low cost
Ease of deposition
Low thermal budget
High thermal conductivity
Electron beam evaporation
ElectronBeam source
Box coaterHigh vacuum – 10-7 TorrMFP = km3-6kW electron beam gunsMultiple cruciblesMetals and dielectrics meltedBeam swept for uniform evaporationDeposition rate monitored by ultrasonicresonant frequency or optical monitorfor dielectricsHeated substrates (option)O2 environment for dielectricsIon flux for densification of dielectricsCo-evaporationTrade off in heating vs cost with distance from source to substrates
Vacuum pumpsPower supply (kV)Water cooling
Rotating holder
Shutter
Lift-off metallisation process
ResistDispense
Undercutresist
Evaporatemetal
Removeresist
Best to match resist thickness to metal thickness
Single layer process Dual layer process
P- type Metallisation
EC
q(Φs - Φm) = qV0
EV
EF
W
Metal p-GaAs
Φb = (χ + Eg) - Φm 1
21: Hole Tunnelling2: Thermionic Emission
Φmqχ
Mechanism:
High doping density at surfaceNo oxide at surface – surface preparation
P-type: Cr – Au; Zn – Au,…….Lasers:
(Pt) - Ti – Pt – Au with electroplated AuTi Adhesion layerPt Tunelling contact and Diffusion barrier to AuAu Current spreading layer
GaAs Electronics:(Pt) - Ti – Pt – Cu
N-typeLasers:
Au - Ge - Ni – AuAuGe Eutectic and dopantNi Barrier layer
Electronics:Pd- Ge – CuPd-In
Metal choice
Avoiding Au
Au-As phase diagram Au-Ga phase diagram
Annealing
Reduce contact resistance by annealing the contact metal at high temperaturesTypically: 300 – 6000C in a non-oxidising environment eg forming gas: H2/N2Expel hydrogen eg after CH4/H2 etching
Furnace anneal
Rapid Thermal Processing (RTP)Lamp heatedFast temperature riseControlled temperature profileReduced thermal load
Gratings
FIBE
Selective oxidation
Implantation
Intermixing
Back-side processing
Other techniques
Selective Oxidation
2AlAs + 3H2O → Al2O3 + 2AsH3
Oxidation rate depends on:N2 flow, temperature…Precise Al contentDoping type (n / p)Doping element (C/Be) & level
furnace controller
outerwall
controllerN2regulator
N2 flow meter
Bath temperature and stirrer controller water
traps
steam inlet pipe
steam outlet pipe
temperaturefeedbackcontroller
Substrate thinning
Substrate needs to be thinned to 100-140µm to enable cleaving
MethodsChemical polishing Br:MeOH and bubbling
Ammonia:Peroxide (pH controlled)
Mechanical Polishing
Automated systems available
Cleaving wafer into laser barsCleaving <011> and <011> directions to realise 90 degree facetsOnly single direction on off-axis substrates
Automated equipment with advanced positioning, imaging system and pattern recognitionDiamond scribe tool for precision 3-5 micron scribe line on epi-sideCleave into bars from the bottom of the wafer,
Skip-scribe
Stretch filmfor bars
Notch
Cleave
Facet coating
SiO2 Etch mask
Nitride
Oxide
Nitride
Nitride
Oxide
Oxide
Epi Surface
ObjectiveTo provide controlled reflectivity and surface passivation
Issues Stoichiometry Densification (using ion gun)
Wide choice of dielectrics – SiO2, Al2O3, HfO2, ZrO2, Ti2O3, MgF2, ZnSe,…HR – sequence of λ/4n thick layersAR – 10% - 0.001%
MethodsEvaporationSputteringPECVD
Acknowledgement:Prepared with assistance from Brendan O’Neill and James O’Callaghan
Reference:R. Williams, “Modern GaAs processing methods” 2nd EditionPub: Artech House ISBN 0-89006-343-5