large area ultra-thin detector ladders based on cmos monolithic pixel sensors
DESCRIPTION
Large Area Ultra-Thin Detector Ladders based on CMOS Monolithic Pixel Sensors. Wojciech Dulinski IPHC Strasbourg, France on behalf of PLUME , SERVIETTE and CERNVIETTE Collaborations. Outline Short status of MAPS development at IPHC - PowerPoint PPT PresentationTRANSCRIPT
IEEE NSS-MIC 2011, Valencia, Spain
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Large Area Ultra-Thin Detector Ladders based on CMOS Monolithic Pixel Sensors
Wojciech DulinskiWojciech DulinskiIPHC Strasbourg, FranceIPHC Strasbourg, France
on behalf of on behalf of PLUMEPLUME, , SERVIETTESERVIETTE and and CERNVIETTECERNVIETTE Collaborations Collaborations
Outline Short status of MAPS development at IPHC PLUME: the lightweight ladder based on standard flex PCB SERVIETTE and CERNVIETTE: ultra-thin chip embedding in plastics project (two different process approach) Conclusions and prospects
IEEE NSS-MIC 2011, Valencia, Spain
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Monolithic Active Pixel Sensor: effective use of a thin epitaxial layer (10 – 20 µm) for MIP tracking
IPHC-DUT [email protected] 714-18/01/2008
iPHC
Metal layers
Polysilicon
P-Well N-Well P-Well
N+ N+ P+ N+
Dielectric for insulation and passivation
Charged particles
100% efficiency.
Radiation
--
--
--
- ++
+++
++
- +- +- +
P-substrate (~100s m thick)
P-epitaxial layer(up to to 20 m thick)
Potential barriers
epi
sub
N
Nln
q
kTV
R.T.
Fast and more efficient charge collection radiation tolerant MAPS
past present
Industrial availability of high resistivity substrate (epi) in a standard CMOS
process
IEEE NSS-MIC 2011, Valencia, Spain
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Present status of MAPS: just two examples of mature designs
Mimosa 26
Binary, sparsified readout sensor for EUDET beam telescope > 2 cm2 active area, 0.7 Mpixel tracker- Medium speed readout (100 µm integration 10 kFrame/s)- Spatial resolution < 4 µm for a pitch of 18.4 µm- Efficiency for MIP > 99.5 %- Fake hit rate < 10-6 - Radiation hardness > 1013 n/cm2 (high resistivity epi substrate)- Easy to use, “off-shell” product: used already in several application
Ultimate: 4 cm2 sensor for STAR Microvertex upgrade- similar measured tracking performance as Mimosa26
- Radiation hardness >1014 n/cm2 with CMOS MAPS attainable? First indications: yes!
IEEE NSS-MIC 2011, Valencia, Spain
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Potentially extremely thin (~25 µm of silicon in total, ~0.027 % X0), flexible (!)
and still fully efficient for MIP tracking!
Problem: how to handle, interconnect and at the end built a low mass ladder with such a thin device?
One of the main feature of MAPS
IEEE NSS-MIC 2011, Valencia, Spain
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First real scale exercise: new STAR Microvertex Detector
Estimated 0.37% X0/ladder. Can we do better?
Data taking (1/4 of detector) expected in 2013, full detector installation in 2014
IEEE NSS-MIC 2011, Valencia, Spain
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Three RD mini-collaborations initiated by IPHC ~2 years ago,Three RD mini-collaborations initiated by IPHC ~2 years ago, in order to develop new methods of ultra-thin ladders construction in order to develop new methods of ultra-thin ladders construction
PLUMEPLUME, , SERVIETTESERVIETTE and and CERNVIETTECERNVIETTE Collaborations Collaborations
11IPHC/IN2P3 Strasbourg, FranceIPHC/IN2P3 Strasbourg, France55University of Bristol, UKUniversity of Bristol, UK
66DESY, Hamburg, GermanyDESY, Hamburg, Germany77University of Oxford, UKUniversity of Oxford, UK22IMEC, Leuven, BelgiumIMEC, Leuven, Belgium
33CMST, University of Gent, BelgiumCMST, University of Gent, Belgium44IFK, Goethe University, Frankfurt/M, GermanyIFK, Goethe University, Frankfurt/M, Germany
88CERN, GenevaCERN, Geneva
IEEE NSS-MIC 2011, Valencia, Spain
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PLUME concept: double-sided ladder (ILC compatible)
-2x6 Mimosa26 sensors thinned down to 50 µm-Standard double-side kapton PCB: Cu conductor (20 µm/layer)
-SiC foam (8%) for spacer between layers-Estimated 0.6 % X0/two sensor layers
IEEE NSS-MIC 2011, Valencia, Spain
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bare low mass cable
module with 6 sensors
bare low mass cable
complete ladder(2 modules)
PLUME prototype: assembling steps
IEEE NSS-MIC 2011, Valencia, Spain
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Heat dissipation: moderate air blow seems to solve a lot of “hot spots” problems
Electrical parameters (threshold dispersion, fake hit rate) almost unchanged…
IEEE NSS-MIC 2011, Valencia, Spain
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Current status of PLUME prototype: ready for beam tests next week!
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- Partner restricted PTW Oct. 2010 - HUMAN++
Stands for :
ULTRA THIN FILM CHIP PACKAGING
Polyimide 1
Polyimide 2
In short : Off-the-shelf die
Thinned down to ± 20-30 µm
Packaged between two polyimide foils
Metallisation : fan-out
Circuit contact through vias
Result : Flexible package, no wire bonding
Thin : 50-70 µm
Embeddable in commercial flexible PCB
SERVIETTE project: use of UTCP by IMEC…
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•Placement (face up) of IC
• Polyimide on rigid carrier with release layer (KCl)
• Dispense/spin of BCB
• Chip thinning
• Metallization: TiW (50nm) + Cu(1µm)
• Electroplating : Cu (5µm)
• Lithography to pattern metal• Encapsulation polyimide spinning• Release from carrier
•Photo definable polyimide spinning (20µm))
• Opening vias using lithography• Cleaning of contact pads
UTCP flow: overview
60 m
IEEE NSS-MIC 2011, Valencia, Spain
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First results: Mimosa18 mechanical grade sample
Submitted for fabrication more thana year ago, very slow progress since, on stand-by
till thinned chip placement problems solved. Aluminum conductor, multiple metal layers and
multiple chips still far ahead…
IEEE NSS-MIC 2011, Valencia, Spain
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CERNVIETTE: use of a “standard” flex PCB process for chip embedding in plastic foils (Rui de Oliveira, Serge Ferry)
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• Gluing between two kapton foils
• Metallization: Al (5-10 µm)• Lithography to pattern metal
• Opening vias using lithography
• Gluing of another kapton foil for deposition of second metal layer
• Single module: intermediate tests
• Complete ladder assembling, laser cut along sensor edges
IEEE NSS-MIC 2011, Valencia, Spain
Thin layer of epoxy glue 3 to 10 µm
Copper
Copper substrate 1.5mm
Acrylic glue Polyimide
Acrylic glue
Silicon chip
Polyimide
acrylic glue 60 µm
150
µm
CERNVIETTE: stack formation
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1-Gluing at 200 deg, 22kg/cm2 under vacuum2-Photolithographic method and chemical etching by ethylene diamine to
create vias on top of bonding pads
3-Plasma etching of glue in vias
4-Aluminium coating by sputtering deposition in vacuum machine
CERNVIETTE: processing steps
IEEE NSS-MIC 2011, Valencia, Spain
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5-Photolithographic method and etching with phosphoric acid to pattern aluminium layer (strip, pads).
Step 1 to 5 can be repeated to create more metal layers and interconnexions
6-Chemical Etching of copper substrate
CERNVIETTE: processing steps
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CERNVIETTE: solid state flexible sensor wrapped over cylindrical shape (R=20 mm) and pretty well protected
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Major failure: too short plasma etching of glue layer, no electrical contacts… But excellent metal adhesion
and thickness uniformity!
Second (corrected) iteration expected to be ready next week
IEEE NSS-MIC 2011, Valencia, Spain
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CERNVIETTE: details of 4 metal layer flex (~0.12% X0)
Impedance of readout lines (last metal, 100 µm width, 100 µm gap) as a function of kapton thickness: 100 Ω
for 60 µm thick kapton (last layer)
IEEE NSS-MIC 2011, Valencia, Spain
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- Construction methods of ultra-light sensor ladders are progressing rapidly, embedding in polymer seems to be a new interesting option
- It is at present our preferred solution in order to take full profit from MAPS high precision tracking performances AND to equip with a reasonable budget large area detectors (replacement of silicon strips, tracking calorimeters…)
Conclusions
Outlook - Double-sided PLUME module (0.6 % X0) fully operational, ready for beam tests starting next
month. The next version (Al instead of Cu conductor, less dense SiC foam 0.3 % X0) in 2012
- Second iteration of single Mimosa26 embedded in kapton (CERNVIETTE) next week, full PLUME compatible ladder (six M26) planned for beginning of the next year
- CERNVIETTE process may by much less critical, if the last metal layer on the chip is used for better (less dense) “bonding pads” distribution 7 metal CIS 0.18 µm process available!
- Start to think about stitching exercise: wafer scale, up to 10x10 cm2 monolithic sensor possible